Searched refs:ctl_status_2 (Results 1 – 1 of 1) sorted by relevance
362 union cvmx_pci_ctl_status_2 ctl_status_2; in octeon_pci_initialize() local386 ctl_status_2.u32 = 0; in octeon_pci_initialize()387 ctl_status_2.s.tsr_hwm = 1; /* Initializes to 0. Must be set in octeon_pci_initialize()389 ctl_status_2.s.bar2pres = 1; /* Enable BAR2 */ in octeon_pci_initialize()390 ctl_status_2.s.bar2_enb = 1; in octeon_pci_initialize()391 ctl_status_2.s.bar2_cax = 1; /* Don't use L2 */ in octeon_pci_initialize()392 ctl_status_2.s.bar2_esx = 1; in octeon_pci_initialize()393 ctl_status_2.s.pmo_amod = 1; /* Round robin priority */ in octeon_pci_initialize()396 ctl_status_2.s.bb1_hole = OCTEON_PCI_BAR1_HOLE_BITS; in octeon_pci_initialize()397 ctl_status_2.s.bb1_siz = 1; /* BAR1 is 2GB */ in octeon_pci_initialize()[all …]
