Searched refs:cp_hqd_pq_base_hi (Results 1 – 19 of 19) sorted by relevance
193 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); in __update_mqd()353 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); in update_mqd_hiq()
185 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); in __update_mqd()
176 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); in update_mqd()
230 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); in update_mqd()
251 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); in update_mqd()
88 uint32_t cp_hqd_pq_base_hi; member
297 uint32_t cp_hqd_pq_base_hi; member
307 uint32_t cp_hqd_pq_base_hi; member
812 uint32_t cp_hqd_pq_base_hi; // offset: 137 (0x89) member
814 uint32_t cp_hqd_pq_base_hi; member
674 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); in mes_v10_1_mqd_init()769 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi);
754 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); in mes_v11_0_mqd_init()844 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); in mes_v11_0_queue_init_register()
2770 u32 cp_hqd_pq_base_hi; member2888 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); in gfx_v7_0_mqd_init()
1541 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); in gfx_v9_4_3_xcc_mqd_init()1653 mqd->cp_hqd_pq_base_hi); in gfx_v9_4_3_xcc_kiq_init_register()
3794 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); in gfx_v11_0_compute_mqd_init()3919 mqd->cp_hqd_pq_base_hi); in gfx_v11_0_kiq_init_register()
3311 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); in gfx_v9_0_mqd_init()3422 mqd->cp_hqd_pq_base_hi); in gfx_v9_0_kiq_init_register()
6567 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); in gfx_v10_0_compute_mqd_init()6677 mqd->cp_hqd_pq_base_hi); in gfx_v10_0_kiq_init_register()
4460 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); in gfx_v8_0_mqd_init()
4443 u32 cp_hqd_pq_base_hi; member4653 mqd->queue_state.cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); in cik_cp_compute_resume()4655 WREG32(CP_HQD_PQ_BASE_HI, mqd->queue_state.cp_hqd_pq_base_hi); in cik_cp_compute_resume()
