Searched refs:clock_div (Results 1 – 5 of 5) sorted by relevance
49 uint32_t clock_div = 0; in cvmx_helper_qlm_jtag_init() local54 clock_div++; in cvmx_helper_qlm_jtag_init()63 jtgc.s.clk_div = clock_div; in cvmx_helper_qlm_jtag_init()
1454 int clock_div = 7; /* 0=30 1=25 2=20 3=15 4=12 5=7.5 6=6 7=3fps ?? */ in cit_get_clock_div() local1462 while (clock_div > 3 && in cit_get_clock_div()1465 fps[clock_div - 1] * 3 / 2) in cit_get_clock_div()1466 clock_div--; in cit_get_clock_div()1472 clock_div, fps[clock_div]); in cit_get_clock_div()1474 return clock_div; in cit_get_clock_div()1480 int clock_div; in cit_start_model0() local1482 clock_div = cit_get_clock_div(gspca_dev); in cit_start_model0()1483 if (clock_div < 0) in cit_start_model0()1484 return clock_div; in cit_start_model0()[all …]
174 u32 clock_div; in pci1xxxx_rs485_config() local187 clock_div = readl(port->membase + UART_BAUD_CLK_DIVISOR_REG); in pci1xxxx_rs485_config()189 FIELD_GET(BAUD_CLOCK_DIV_INT_MSK, clock_div) * in pci1xxxx_rs485_config()
418 u_char clock_div; member508 cyber2000_grphw(EXT_DCLK_DIV, hw->clock_div, cfb); in cyber2000fb_set_timing()740 hw->clock_div = div2 << 6 | (best_div1 - 1); in cyber2000fb_decode_clock()745 hw->clock_div |= EXT_DCLK_DIV_VFSEL; in cyber2000fb_decode_clock()
387 u8 clock_div; /* Clock divider */ member
