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Searched refs:clk_type (Results 1 – 25 of 49) sorted by relevance

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/Linux-v6.6/drivers/gpu/drm/amd/display/dc/
Ddm_services_types.h82 #define DC_DECODE_PP_CLOCK_TYPE(clk_type) \ argument
83 (clk_type) == DM_PP_CLOCK_TYPE_DISPLAY_CLK ? "Display" : \
84 (clk_type) == DM_PP_CLOCK_TYPE_ENGINE_CLK ? "Engine" : \
85 (clk_type) == DM_PP_CLOCK_TYPE_MEMORY_CLK ? "Memory" : \
86 (clk_type) == DM_PP_CLOCK_TYPE_DCFCLK ? "DCF" : \
87 (clk_type) == DM_PP_CLOCK_TYPE_DCEFCLK ? "DCEF" : \
88 (clk_type) == DM_PP_CLOCK_TYPE_SOCCLK ? "SoC" : \
89 (clk_type) == DM_PP_CLOCK_TYPE_PIXELCLK ? "Pixel" : \
90 (clk_type) == DM_PP_CLOCK_TYPE_DISPLAYPHYCLK ? "Display PHY" : \
91 (clk_type) == DM_PP_CLOCK_TYPE_DPPCLK ? "DPP" : \
[all …]
Ddm_services.h192 enum dm_pp_clock_type clk_type,
197 enum dm_pp_clock_type clk_type,
202 enum dm_pp_clock_type clk_type,
/Linux-v6.6/sound/soc/intel/skylake/
Dskl-ssp-clk.c57 static int skl_get_vbus_id(u32 index, u8 clk_type) in skl_get_vbus_id() argument
59 switch (clk_type) { in skl_get_vbus_id()
74 static void skl_fill_clk_ipc(struct skl_clk_rate_cfg_table *rcfg, u8 clk_type) in skl_fill_clk_ipc() argument
84 if (clk_type == SKL_SCLK_FS) { in skl_fill_clk_ipc()
107 u32 vbus_id, u8 clk_type, in skl_send_clk_dma_control() argument
125 if (clk_type == SKL_SCLK_FS) { in skl_send_clk_dma_control()
132 if (clk_type == SKL_SCLK) in skl_send_clk_dma_control()
181 int vbus_id, clk_type; in skl_clk_change_status() local
183 clk_type = skl_get_clk_type(clkdev->id); in skl_clk_change_status()
184 if (clk_type < 0) in skl_clk_change_status()
[all …]
/Linux-v6.6/drivers/gpu/drm/amd/pm/swsmu/smu13/
Dsmu_v13_0_5_ppt.c587 enum smu_clk_type clk_type, in smu_v13_0_5_get_current_clk_freq() argument
592 switch (clk_type) { in smu_v13_0_5_get_current_clk_freq()
618 enum smu_clk_type clk_type, in smu_v13_0_5_get_dpm_level_count() argument
623 switch (clk_type) { in smu_v13_0_5_get_dpm_level_count()
647 enum smu_clk_type clk_type, in smu_v13_0_5_get_dpm_freq_by_index() argument
653 if (!clk_table || clk_type >= SMU_CLK_COUNT) in smu_v13_0_5_get_dpm_freq_by_index()
656 switch (clk_type) { in smu_v13_0_5_get_dpm_freq_by_index()
691 enum smu_clk_type clk_type) in smu_v13_0_5_clk_dpm_is_enabled() argument
695 switch (clk_type) { in smu_v13_0_5_clk_dpm_is_enabled()
720 enum smu_clk_type clk_type, in smu_v13_0_5_get_dpm_ultimate_freq() argument
[all …]
Dsmu_v13_0_4_ppt.c377 enum smu_clk_type clk_type, in smu_v13_0_4_get_current_clk_freq() argument
382 switch (clk_type) { in smu_v13_0_4_get_current_clk_freq()
413 enum smu_clk_type clk_type, in smu_v13_0_4_get_dpm_freq_by_index() argument
419 if (!clk_table || clk_type >= SMU_CLK_COUNT) in smu_v13_0_4_get_dpm_freq_by_index()
422 switch (clk_type) { in smu_v13_0_4_get_dpm_freq_by_index()
457 enum smu_clk_type clk_type, in smu_v13_0_4_get_dpm_level_count() argument
462 switch (clk_type) { in smu_v13_0_4_get_dpm_level_count()
486 enum smu_clk_type clk_type, char *buf) in smu_v13_0_4_print_clk_levels() argument
494 switch (clk_type) { in smu_v13_0_4_print_clk_levels()
513 ret = smu_v13_0_4_get_current_clk_freq(smu, clk_type, &cur_value); in smu_v13_0_4_print_clk_levels()
[all …]
Dyellow_carp_ppt.c718 enum smu_clk_type clk_type, in yellow_carp_get_current_clk_freq() argument
723 switch (clk_type) { in yellow_carp_get_current_clk_freq()
752 enum smu_clk_type clk_type, in yellow_carp_get_dpm_level_count() argument
757 switch (clk_type) { in yellow_carp_get_dpm_level_count()
781 enum smu_clk_type clk_type, in yellow_carp_get_dpm_freq_by_index() argument
787 if (!clk_table || clk_type >= SMU_CLK_COUNT) in yellow_carp_get_dpm_freq_by_index()
790 switch (clk_type) { in yellow_carp_get_dpm_freq_by_index()
825 enum smu_clk_type clk_type) in yellow_carp_clk_dpm_is_enabled() argument
829 switch (clk_type) { in yellow_carp_clk_dpm_is_enabled()
854 enum smu_clk_type clk_type, in yellow_carp_get_dpm_ultimate_freq() argument
[all …]
Dsmu_v13_0.c1082 enum amd_pp_clock_type clk_type = clock_req->clock_type; in smu_v13_0_display_clock_voltage_request() local
1089 switch (clk_type) { in smu_v13_0_display_clock_voltage_request()
1546 int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, in smu_v13_0_get_dpm_ultimate_freq() argument
1553 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) { in smu_v13_0_get_dpm_ultimate_freq()
1554 switch (clk_type) { in smu_v13_0_get_dpm_ultimate_freq()
1582 clk_type); in smu_v13_0_get_dpm_ultimate_freq()
1615 enum smu_clk_type clk_type, in smu_v13_0_set_soft_freq_limited_range() argument
1622 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) in smu_v13_0_set_soft_freq_limited_range()
1627 clk_type); in smu_v13_0_set_soft_freq_limited_range()
1652 enum smu_clk_type clk_type, in smu_v13_0_set_hard_freq_limited_range() argument
[all …]
Dsmu_v13_0_6_ppt.c212 enum smu_clk_type clk_type; member
386 enum smu_clk_type clk_type, in smu_v13_0_6_get_dpm_ultimate_freq() argument
395 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) { in smu_v13_0_6_get_dpm_ultimate_freq()
396 switch (clk_type) { in smu_v13_0_6_get_dpm_ultimate_freq()
436 if (!(clk_type == SMU_GFXCLK || clk_type == SMU_SCLK)) { in smu_v13_0_6_get_dpm_ultimate_freq()
438 smu, CMN2ASIC_MAPPING_CLK, clk_type); in smu_v13_0_6_get_dpm_ultimate_freq()
447 if (clk_type == SMU_GFXCLK || clk_type == SMU_SCLK) in smu_v13_0_6_get_dpm_ultimate_freq()
458 if (clk_type == SMU_GFXCLK || clk_type == SMU_SCLK) in smu_v13_0_6_get_dpm_ultimate_freq()
471 enum smu_clk_type clk_type, in smu_v13_0_6_get_dpm_level_count() argument
476 ret = smu_v13_0_get_dpm_freq_by_index(smu, clk_type, 0xff, levels); in smu_v13_0_6_get_dpm_level_count()
[all …]
/Linux-v6.6/drivers/clk/imx/
Dclk-scu.h34 int num_parents, u32 rsrc_id, u8 clk_type);
38 u32 rsrc_id, u8 clk_type);
52 u8 clk_type) in imx_clk_scu() argument
54 return imx_clk_scu_alloc_dev(name, NULL, 0, rsrc_id, clk_type); in imx_clk_scu()
58 int num_parents, u32 rsrc_id, u8 clk_type) in imx_clk_scu2() argument
60 return imx_clk_scu_alloc_dev(name, parents, num_parents, rsrc_id, clk_type); in imx_clk_scu2()
Dclk-scu.c31 u8 clk_type; member
50 u8 clk_type; member
241 msg.data.req.clk = clk->clk_type; in clk_scu_recalc_rate()
332 msg.clk = clk->clk_type; in clk_scu_set_rate()
350 msg.data.req.clk = clk->clk_type; in clk_scu_get_parent()
377 msg.clk = clk->clk_type; in clk_scu_set_parent()
422 clk->clk_type, true, false); in clk_scu_prepare()
437 clk->clk_type, false, false); in clk_scu_unprepare()
469 u32 rsrc_id, u8 clk_type) in __imx_clk_scu() argument
481 clk->clk_type = clk_type; in __imx_clk_scu()
[all …]
/Linux-v6.6/drivers/gpu/drm/amd/pm/swsmu/
Damdgpu_smu.c60 enum smu_clk_type clk_type,
130 enum smu_clk_type clk_type, in smu_set_soft_freq_range() argument
138 clk_type, in smu_set_soft_freq_range()
146 enum smu_clk_type clk_type, in smu_get_dpm_freq_range() argument
157 clk_type, in smu_get_dpm_freq_range()
390 enum smu_clk_type clk_type; in smu_restore_dpm_user_profile() local
392 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { in smu_restore_dpm_user_profile()
397 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && in smu_restore_dpm_user_profile()
398 smu->user_dpm_profile.clk_mask[clk_type]) { in smu_restore_dpm_user_profile()
399 ret = smu_force_smuclk_levels(smu, clk_type, in smu_restore_dpm_user_profile()
[all …]
/Linux-v6.6/drivers/gpu/drm/amd/pm/swsmu/smu11/
Dvangogh_ppt.c540 static int vangogh_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type, in vangogh_get_dpm_clk_limited() argument
545 if (!clk_table || clk_type >= SMU_CLK_COUNT) in vangogh_get_dpm_clk_limited()
548 switch (clk_type) { in vangogh_get_dpm_clk_limited()
584 enum smu_clk_type clk_type, char *buf) in vangogh_print_legacy_clk_levels() argument
601 switch (clk_type) { in vangogh_print_legacy_clk_levels()
656 switch (clk_type) { in vangogh_print_legacy_clk_levels()
663 idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i; in vangogh_print_legacy_clk_levels()
664 ret = vangogh_get_dpm_clk_limited(smu, clk_type, idx, &value); in vangogh_print_legacy_clk_levels()
686 enum smu_clk_type clk_type, char *buf) in vangogh_print_clk_levels() argument
704 switch (clk_type) { in vangogh_print_clk_levels()
[all …]
Dcyan_skillfish_ppt.c260 enum smu_clk_type clk_type, in cyan_skillfish_get_current_clk_freq() argument
265 switch (clk_type) { in cyan_skillfish_get_current_clk_freq()
291 enum smu_clk_type clk_type, in cyan_skillfish_print_clk_levels() argument
300 switch (clk_type) { in cyan_skillfish_print_clk_levels()
327 ret = cyan_skillfish_get_current_clk_freq(smu, clk_type, &cur_value); in cyan_skillfish_print_clk_levels()
334 ret = cyan_skillfish_get_current_clk_freq(smu, clk_type, &cur_value); in cyan_skillfish_print_clk_levels()
536 enum smu_clk_type clk_type, in cyan_skillfish_get_dpm_ultimate_freq() argument
543 switch (clk_type) { in cyan_skillfish_get_dpm_ultimate_freq()
550 ret = cyan_skillfish_get_current_clk_freq(smu, clk_type, &low); in cyan_skillfish_get_dpm_ultimate_freq()
Dsmu_v11_0.c1056 enum amd_pp_clock_type clk_type = clock_req->clock_type; in smu_v11_0_display_clock_voltage_request() local
1063 switch (clk_type) { in smu_v11_0_display_clock_voltage_request()
1696 int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, in smu_v11_0_get_dpm_ultimate_freq() argument
1703 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) { in smu_v11_0_get_dpm_ultimate_freq()
1704 switch (clk_type) { in smu_v11_0_get_dpm_ultimate_freq()
1732 clk_type); in smu_v11_0_get_dpm_ultimate_freq()
1756 enum smu_clk_type clk_type, in smu_v11_0_set_soft_freq_limited_range() argument
1763 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) in smu_v11_0_set_soft_freq_limited_range()
1768 clk_type); in smu_v11_0_set_soft_freq_limited_range()
1793 enum smu_clk_type clk_type, in smu_v11_0_set_hard_freq_limited_range() argument
[all …]
Dnavi10_ppt.c1185 enum smu_clk_type clk_type, in navi10_get_current_clk_freq_by_table() argument
1193 clk_type); in navi10_get_current_clk_freq_by_table()
1225 static bool navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type) in navi10_is_support_fine_grained_dpm() argument
1233 clk_type); in navi10_is_support_fine_grained_dpm()
1256 enum smu_clk_type clk_type, in navi10_emit_clk_levels() argument
1275 switch (clk_type) { in navi10_emit_clk_levels()
1285 ret = navi10_get_current_clk_freq_by_table(smu, clk_type, &cur_value); in navi10_emit_clk_levels()
1289 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count); in navi10_emit_clk_levels()
1293 if (!navi10_is_support_fine_grained_dpm(smu, clk_type)) { in navi10_emit_clk_levels()
1296 clk_type, i, &value); in navi10_emit_clk_levels()
[all …]
/Linux-v6.6/drivers/gpu/drm/amd/pm/swsmu/smu12/
Drenoir_ppt.c202 static int renoir_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type, in renoir_get_dpm_clk_limited() argument
207 if (!clk_table || clk_type >= SMU_CLK_COUNT) in renoir_get_dpm_clk_limited()
210 switch (clk_type) { in renoir_get_dpm_clk_limited()
281 enum smu_clk_type clk_type, in renoir_get_dpm_ultimate_freq() argument
289 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) { in renoir_get_dpm_ultimate_freq()
290 switch (clk_type) { in renoir_get_dpm_ultimate_freq()
325 switch (clk_type) { in renoir_get_dpm_ultimate_freq()
337 ret = renoir_get_dpm_clk_limited(smu, clk_type, mclk_mask, max); in renoir_get_dpm_ultimate_freq()
342 ret = renoir_get_dpm_clk_limited(smu, clk_type, soc_mask, max); in renoir_get_dpm_ultimate_freq()
353 switch (clk_type) { in renoir_get_dpm_ultimate_freq()
[all …]
Dsmu_v12_0.c213 int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type, in smu_v12_0_set_soft_freq_limited_range() argument
218 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) in smu_v12_0_set_soft_freq_limited_range()
221 switch (clk_type) { in smu_v12_0_set_soft_freq_limited_range()
/Linux-v6.6/drivers/gpu/drm/amd/pm/swsmu/inc/
Dsmu_v11_0.h254 int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
257 int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
261 enum smu_clk_type clk_type,
272 enum smu_clk_type clk_type,
277 enum smu_clk_type clk_type,
281 enum smu_clk_type clk_type,
285 enum smu_clk_type clk_type,
Dsmu_v13_0.h225 int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
228 int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
232 enum smu_clk_type clk_type,
243 enum smu_clk_type clk_type,
247 enum smu_clk_type clk_type, uint16_t level,
Damdgpu_smu.h616 int (*print_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf);
629 …int (*emit_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf, int *offset…
637 int (*force_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask);
660 enum smu_clk_type clk_type,
1210 …int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, u…
1216 …int (*set_soft_freq_limited_range)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t m…
1476 int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
1479 int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
/Linux-v6.6/drivers/gpu/drm/amd/display/amdgpu_dm/
Damdgpu_dm_pp_smu.c111 enum dm_pp_clock_type clk_type, in get_default_clock_levels() argument
120 switch (clk_type) { in get_default_clock_levels()
294 enum dm_pp_clock_type clk_type, in dm_pp_get_clock_levels_by_type() argument
303 dc_to_pp_clock_type(clk_type), &pp_clks)) { in dm_pp_get_clock_levels_by_type()
305 get_default_clock_levels(clk_type, dc_clks); in dm_pp_get_clock_levels_by_type()
309 pp_to_dc_clock_levels(&pp_clks, dc_clks, clk_type); in dm_pp_get_clock_levels_by_type()
332 if (clk_type == DM_PP_CLOCK_TYPE_ENGINE_CLK) { in dm_pp_get_clock_levels_by_type()
345 } else if (clk_type == DM_PP_CLOCK_TYPE_MEMORY_CLK) { in dm_pp_get_clock_levels_by_type()
361 enum dm_pp_clock_type clk_type, in dm_pp_get_clock_levels_by_type_with_latency() argument
369 dc_to_pp_clock_type(clk_type), in dm_pp_get_clock_levels_by_type_with_latency()
[all …]
/Linux-v6.6/drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/
Ddce120_clk_mgr.c98 clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DISPLAY_CLK; in dce12_update_clocks()
113 clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DISPLAYPHYCLK; in dce12_update_clocks()
/Linux-v6.6/drivers/input/
Devdev.c49 enum input_clock_type clk_type; member
146 struct timespec64 ts = ktime_to_timespec64(ev_time[client->clk_type]); in __evdev_queue_syn_dropped()
177 enum input_clock_type clk_type; in evdev_set_clk_type() local
182 clk_type = INPUT_CLK_REAL; in evdev_set_clk_type()
185 clk_type = INPUT_CLK_MONO; in evdev_set_clk_type()
188 clk_type = INPUT_CLK_BOOT; in evdev_set_clk_type()
194 if (client->clk_type != clk_type) { in evdev_set_clk_type()
195 client->clk_type = clk_type; in evdev_set_clk_type()
256 ts = ktime_to_timespec64(ev_time[client->clk_type]); in evdev_pass_values()
/Linux-v6.6/drivers/phy/
Dphy-xgene.c535 enum clk_type_t clk_type; /* Input clock selection */ member
706 enum clk_type_t clk_type) in xgene_phy_cfg_cmu_clk_type() argument
719 if (clk_type == CLK_EXT_DIFF) { in xgene_phy_cfg_cmu_clk_type()
729 } else if (clk_type == CLK_INT_DIFF) { in xgene_phy_cfg_cmu_clk_type()
739 } else if (clk_type == CLK_INT_SING) { in xgene_phy_cfg_cmu_clk_type()
760 enum clk_type_t clk_type) in xgene_phy_sata_cfg_cmu_core() argument
806 if (clk_type == CLK_EXT_DIFF) in xgene_phy_sata_cfg_cmu_core()
1137 enum clk_type_t clk_type) in xgene_phy_cal_rdy_chk() argument
1237 enum clk_type_t clk_type) in xgene_phy_pdwn_force_vco() argument
1254 enum clk_type_t clk_type, int ssc_enable) in xgene_phy_hw_init_sata() argument
[all …]
/Linux-v6.6/drivers/nfc/s3fwrn5/
Dnci.h44 __u8 clk_type; member

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