Searched refs:clk_select (Results 1 – 6 of 6) sorted by relevance
37 enum fsl_pwm_clk clk_select; member78 if (a->clk_select != b->clk_select) in fsl_pwm_periodcfg_are_equal()121 rate = clk_get_rate(fpc->clk[fpc->period.clk_select]); in fsl_pwm_ticks_to_ns()146 periodcfg->clk_select = index; in fsl_pwm_calculate_period_clk()254 if (fpc->period.clk_select != periodcfg.clk_select) { in fsl_pwm_apply_config()256 enum fsl_pwm_clk oldclk = fpc->period.clk_select; in fsl_pwm_apply_config()257 enum fsl_pwm_clk newclk = periodcfg.clk_select; in fsl_pwm_apply_config()271 FTM_SC_CLK(periodcfg.clk_select)); in fsl_pwm_apply_config()319 clk_disable_unprepare(fpc->clk[fpc->period.clk_select]); in fsl_pwm_apply()331 ret = clk_prepare_enable(fpc->clk[fpc->period.clk_select]); in fsl_pwm_apply()[all …]
1058 enum smu_clk_type clk_select = 0; in smu_v11_0_display_clock_voltage_request() local1065 clk_select = SMU_DCEFCLK; in smu_v11_0_display_clock_voltage_request()1068 clk_select = SMU_DISPCLK; in smu_v11_0_display_clock_voltage_request()1071 clk_select = SMU_PIXCLK; in smu_v11_0_display_clock_voltage_request()1074 clk_select = SMU_PHYCLK; in smu_v11_0_display_clock_voltage_request()1077 clk_select = SMU_UCLK; in smu_v11_0_display_clock_voltage_request()1088 if (clk_select == SMU_UCLK && smu->disable_uclk_switch) in smu_v11_0_display_clock_voltage_request()1091 ret = smu_v11_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0); in smu_v11_0_display_clock_voltage_request()1093 if(clk_select == SMU_UCLK) in smu_v11_0_display_clock_voltage_request()
1084 enum smu_clk_type clk_select = 0; in smu_v13_0_display_clock_voltage_request() local1091 clk_select = SMU_DCEFCLK; in smu_v13_0_display_clock_voltage_request()1094 clk_select = SMU_DISPCLK; in smu_v13_0_display_clock_voltage_request()1097 clk_select = SMU_PIXCLK; in smu_v13_0_display_clock_voltage_request()1100 clk_select = SMU_PHYCLK; in smu_v13_0_display_clock_voltage_request()1103 clk_select = SMU_UCLK; in smu_v13_0_display_clock_voltage_request()1114 if (clk_select == SMU_UCLK && smu->disable_uclk_switch) in smu_v13_0_display_clock_voltage_request()1117 ret = smu_v13_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0); in smu_v13_0_display_clock_voltage_request()1119 if (clk_select == SMU_UCLK) in smu_v13_0_display_clock_voltage_request()
1570 PPCLK_e clk_select = 0; in vega12_display_clock_voltage_request() local1576 clk_select = PPCLK_DCEFCLK; in vega12_display_clock_voltage_request()1579 clk_select = PPCLK_DISPCLK; in vega12_display_clock_voltage_request()1582 clk_select = PPCLK_PIXCLK; in vega12_display_clock_voltage_request()1585 clk_select = PPCLK_PHYCLK; in vega12_display_clock_voltage_request()1594 clk_request = (clk_select << 16) | clk_freq; in vega12_display_clock_voltage_request()
2294 PPCLK_e clk_select = 0; in vega20_display_clock_voltage_request() local2300 clk_select = PPCLK_DCEFCLK; in vega20_display_clock_voltage_request()2303 clk_select = PPCLK_DISPCLK; in vega20_display_clock_voltage_request()2306 clk_select = PPCLK_PIXCLK; in vega20_display_clock_voltage_request()2309 clk_select = PPCLK_PHYCLK; in vega20_display_clock_voltage_request()2318 clk_request = (clk_select << 16) | clk_freq; in vega20_display_clock_voltage_request()
4006 DSPCLK_e clk_select = 0; in vega10_display_clock_voltage_request() local4011 clk_select = DSPCLK_DCEFCLK; in vega10_display_clock_voltage_request()4014 clk_select = DSPCLK_DISPCLK; in vega10_display_clock_voltage_request()4017 clk_select = DSPCLK_PIXCLK; in vega10_display_clock_voltage_request()4020 clk_select = DSPCLK_PHYCLK; in vega10_display_clock_voltage_request()4029 clk_request = (clk_freq << 16) | clk_select; in vega10_display_clock_voltage_request()
