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Searched refs:channel_writel (Results 1 – 9 of 9) sorted by relevance

/Linux-v6.6/drivers/dma/dw/
Didma32.c137 channel_writel(dwc, CFG_LO, cfglo); in idma32_initialize_chan_xbar()
138 channel_writel(dwc, CFG_HI, cfghi); in idma32_initialize_chan_xbar()
157 channel_writel(dwc, CFG_LO, cfglo); in idma32_initialize_chan_generic()
158 channel_writel(dwc, CFG_HI, cfghi); in idma32_initialize_chan_generic()
168 channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP); in idma32_suspend_chan()
178 channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP); in idma32_resume_chan()
Ddw.c28 channel_writel(dwc, CFG_LO, cfglo); in dw_dma_initialize_chan()
29 channel_writel(dwc, CFG_HI, cfghi); in dw_dma_initialize_chan()
36 channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP); in dw_dma_suspend_chan()
43 channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP); in dw_dma_resume_chan()
Dcore.c160 channel_writel(dwc, SAR, lli_read(desc, sar)); in dwc_do_single_block()
161 channel_writel(dwc, DAR, lli_read(desc, dar)); in dwc_do_single_block()
162 channel_writel(dwc, CTL_LO, ctllo); in dwc_do_single_block()
163 channel_writel(dwc, CTL_HI, lli_read(desc, ctlhi)); in dwc_do_single_block()
210 channel_writel(dwc, LLP, first->txd.phys | lms); in dwc_dostart()
211 channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); in dwc_dostart()
212 channel_writel(dwc, CTL_HI, 0); in dwc_dostart()
Dregs.h305 #define channel_writel(dwc, name, val) \ macro
/Linux-v6.6/drivers/dma/
Dpch_dma.c112 #define channel_writel(pdc, name, val) \ macro
337 channel_writel(pd_chan, DEV_ADDR, desc->regs.dev_addr); in pdc_dostart()
338 channel_writel(pd_chan, MEM_ADDR, desc->regs.mem_addr); in pdc_dostart()
339 channel_writel(pd_chan, SIZE, desc->regs.size); in pdc_dostart()
340 channel_writel(pd_chan, NEXT, desc->regs.next); in pdc_dostart()
343 channel_writel(pd_chan, NEXT, desc->txd.phys); in pdc_dostart()
775 channel_writel(pd_chan, DEV_ADDR, pd->ch_regs[i].dev_addr); in pch_dma_restore_regs()
776 channel_writel(pd_chan, MEM_ADDR, pd->ch_regs[i].mem_addr); in pch_dma_restore_regs()
777 channel_writel(pd_chan, SIZE, pd->ch_regs[i].size); in pch_dma_restore_regs()
778 channel_writel(pd_chan, NEXT, pd->ch_regs[i].next); in pch_dma_restore_regs()
Didma64.c67 channel_writel(idma64c, CFG_LO, cfglo); in idma64_chan_init()
68 channel_writel(idma64c, CFG_HI, cfghi); in idma64_chan_init()
97 channel_writel(idma64c, CTL_HI, IDMA64C_CTLH_BLOCK_TS(~0UL)); in idma64_chan_start()
98 channel_writel(idma64c, CTL_LO, IDMA64C_CTLL_LLP_S_EN | IDMA64C_CTLL_LLP_D_EN); in idma64_chan_start()
429 channel_writel(idma64c, CFG_LO, cfglo | IDMA64C_CFGL_CH_SUSP); in idma64_chan_deactivate()
441 channel_writel(idma64c, CFG_LO, cfglo & ~IDMA64C_CFGL_CH_SUSP); in idma64_chan_activate()
Dat_hdmac.c292 #define channel_writel(atchan, name, val) \ macro
565 channel_writel(atchan, SADDR, 0); in atc_dostart()
566 channel_writel(atchan, DADDR, 0); in atc_dostart()
567 channel_writel(atchan, CTRLA, 0); in atc_dostart()
568 channel_writel(atchan, CTRLB, 0); in atc_dostart()
569 channel_writel(atchan, DSCR, desc->sg[0].lli_phys); in atc_dostart()
570 channel_writel(atchan, SPIP, in atc_dostart()
573 channel_writel(atchan, DPIP, in atc_dostart()
1746 channel_writel(atchan, CFG, cfg); in atc_alloc_chan_resources()
2199 channel_writel(atchan, SADDR, 0); in atc_resume_cyclic()
[all …]
Dtxx9dmac.c54 #define channel_writel(dc, name, val) \ macro
313 channel_writel(dc, CCR, TXX9_DMA_CCR_CHRST); in txx9dmac_reset_chan()
319 channel_writel(dc, CHAR, 0); in txx9dmac_reset_chan()
320 channel_writel(dc, SAR, 0); in txx9dmac_reset_chan()
321 channel_writel(dc, DAR, 0); in txx9dmac_reset_chan()
323 channel_writel(dc, CNTR, 0); in txx9dmac_reset_chan()
324 channel_writel(dc, SAIR, 0); in txx9dmac_reset_chan()
325 channel_writel(dc, DAIR, 0); in txx9dmac_reset_chan()
326 channel_writel(dc, CCR, 0); in txx9dmac_reset_chan()
519 channel_writel(dc, CSR, errors); in txx9dmac_handle_error()
Didma64.h164 #define channel_writel(idma64c, reg, value) \ macro