Searched refs:cfg01 (Results 1 – 2 of 2) sorted by relevance
25 union cvmx_pci_cfg01 cfg01; in octeon_pci_poll() local27 cfg01.u32 = octeon_npi_read32(CVMX_NPI_PCI_CFG01); in octeon_pci_poll()28 if (cfg01.s.dpe) { /* Detected parity error */ in octeon_pci_poll()30 cfg01.s.dpe = 1; /* Reset */ in octeon_pci_poll()31 octeon_npi_write32(CVMX_NPI_PCI_CFG01, cfg01.u32); in octeon_pci_poll()33 if (cfg01.s.sse) { in octeon_pci_poll()35 cfg01.s.sse = 1; /* Reset */ in octeon_pci_poll()36 octeon_npi_write32(CVMX_NPI_PCI_CFG01, cfg01.u32); in octeon_pci_poll()38 if (cfg01.s.rma) { in octeon_pci_poll()40 cfg01.s.rma = 1; /* Reset */ in octeon_pci_poll()[all …]
360 union cvmx_pci_cfg01 cfg01; in octeon_pci_initialize() local478 cfg01.u32 = 0; in octeon_pci_initialize()479 cfg01.s.msae = 1; /* Memory Space Access Enable */ in octeon_pci_initialize()480 cfg01.s.me = 1; /* Master Enable */ in octeon_pci_initialize()481 cfg01.s.pee = 1; /* PERR# Enable */ in octeon_pci_initialize()482 cfg01.s.see = 1; /* System Error Enable */ in octeon_pci_initialize()483 cfg01.s.fbbe = 1; /* Fast Back to Back Transaction Enable */ in octeon_pci_initialize()485 octeon_npi_write32(CVMX_NPI_PCI_CFG01, cfg01.u32); in octeon_pci_initialize()
