Searched refs:buf_mask (Results 1 – 13 of 13) sorted by relevance
58 start = s_start & ring->buf_mask; in amdgpu_ring_mux_copy_pkt_from_sw_ring()59 end = s_end & ring->buf_mask; in amdgpu_ring_mux_copy_pkt_from_sw_ring()110 if (chunk->cntl_offset <= e->ring->buf_mask) in amdgpu_mux_resubmit_chunks()113 if (chunk->ce_offset <= e->ring->buf_mask) in amdgpu_mux_resubmit_chunks()115 if (chunk->de_offset <= e->ring->buf_mask) in amdgpu_mux_resubmit_chunks()296 start = e->start_ptr_in_hw_ring & mux->real_ring->buf_mask; in amdgpu_ring_mux_get_rptr()297 end = e->end_ptr_in_hw_ring & mux->real_ring->buf_mask; in amdgpu_ring_mux_get_rptr()306 e->sw_rptr = (e->sw_cptr + offset) & ring->buf_mask; in amdgpu_ring_mux_get_rptr()429 offset = ring->wptr & ring->buf_mask; in amdgpu_sw_ring_ib_mark_offset()457 chunk->cntl_offset = ring->buf_mask + 1; in amdgpu_ring_mux_start_ib()[all …]
323 ring->buf_mask = (ring->ring_size / 4) - 1; in amdgpu_ring_init()325 0xffffffffffffffff : ring->buf_mask; in amdgpu_ring_init()481 early[0] = amdgpu_ring_get_rptr(ring) & ring->buf_mask; in amdgpu_debugfs_ring_read()482 early[1] = amdgpu_ring_get_wptr(ring) & ring->buf_mask; in amdgpu_debugfs_ring_read()483 early[2] = ring->wptr & ring->buf_mask; in amdgpu_debugfs_ring_read()
256 uint32_t buf_mask; member366 while (i <= ring->buf_mask) in amdgpu_ring_clear_ring()375 ring->ring[ring->wptr++ & ring->buf_mask] = v; in amdgpu_ring_write()389 occupied = ring->wptr & ring->buf_mask; in amdgpu_ring_write_multiple()391 chunk1 = ring->buf_mask + 1 - occupied; in amdgpu_ring_write_multiple()
100 ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */ in sdma_v5_2_ring_init_cond_exec()111 BUG_ON(offset > ring->buf_mask); in sdma_v5_2_ring_patch_cond_exec()114 cur = (ring->wptr - 1) & ring->buf_mask; in sdma_v5_2_ring_patch_cond_exec()118 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; in sdma_v5_2_ring_patch_cond_exec()
90 ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */ in sdma_v6_0_ring_init_cond_exec()101 BUG_ON(offset > ring->buf_mask); in sdma_v6_0_ring_patch_cond_exec()104 cur = (ring->wptr - 1) & ring->buf_mask; in sdma_v6_0_ring_patch_cond_exec()108 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; in sdma_v6_0_ring_patch_cond_exec()
260 ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */ in sdma_v5_0_ring_init_cond_exec()271 BUG_ON(offset > ring->buf_mask); in sdma_v5_0_ring_patch_cond_exec()274 cur = (ring->wptr - 1) & ring->buf_mask; in sdma_v5_0_ring_patch_cond_exec()278 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; in sdma_v5_0_ring_patch_cond_exec()
833 amdgpu_ring_write(kiq_ring, lower_32_bits(ring->wptr & ring->buf_mask)); in gfx_v9_0_kiq_unmap_queues()5197 if (offset + (payload_size >> 2) <= ring->buf_mask + 1) { in gfx_v9_0_ring_patch_ce_meta()5201 (ring->buf_mask + 1 - offset) << 2); in gfx_v9_0_ring_patch_ce_meta()5202 payload_size -= (ring->buf_mask + 1 - offset) << 2; in gfx_v9_0_ring_patch_ce_meta()5204 ce_payload_cpu_addr + ((ring->buf_mask + 1 - offset) << 2), in gfx_v9_0_ring_patch_ce_meta()5232 if (offset + (payload_size >> 2) <= ring->buf_mask + 1) { in gfx_v9_0_ring_patch_de_meta()5236 (ring->buf_mask + 1 - offset) << 2); in gfx_v9_0_ring_patch_de_meta()5237 payload_size -= (ring->buf_mask + 1 - offset) << 2; in gfx_v9_0_ring_patch_de_meta()5239 de_payload_cpu_addr + ((ring->buf_mask + 1 - offset) << 2), in gfx_v9_0_ring_patch_de_meta()5610 ret = ring->wptr & ring->buf_mask; in gfx_v9_0_ring_emit_init_cond_exec()[all …]
5161 wptr_tmp = ring->wptr & ring->buf_mask; in gfx_v11_0_ring_set_wptr_gfx()5224 wptr_tmp = ring->wptr & ring->buf_mask; in gfx_v11_0_ring_set_wptr_compute()5511 ret = ring->wptr & ring->buf_mask; in gfx_v11_0_ring_emit_init_cond_exec()5520 BUG_ON(offset > ring->buf_mask); in gfx_v11_0_ring_emit_patch_cond_exec()5523 cur = (ring->wptr - 1) & ring->buf_mask; in gfx_v11_0_ring_emit_patch_cond_exec()5527 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; in gfx_v11_0_ring_emit_patch_cond_exec()
8178 wptr_tmp = ring->wptr & ring->buf_mask; in gfx_v10_0_ring_set_wptr_gfx()8241 wptr_tmp = ring->wptr & ring->buf_mask; in gfx_v10_0_ring_set_wptr_compute()8522 ret = ring->wptr & ring->buf_mask; in gfx_v10_0_ring_emit_init_cond_exec()8532 BUG_ON(offset > ring->buf_mask); in gfx_v10_0_ring_emit_patch_cond_exec()8535 cur = (ring->wptr - 1) & ring->buf_mask; in gfx_v10_0_ring_emit_patch_cond_exec()8539 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; in gfx_v10_0_ring_emit_patch_cond_exec()
6338 ret = ring->wptr & ring->buf_mask; in gfx_v8_0_ring_emit_init_cond_exec()6347 BUG_ON(offset > ring->buf_mask); in gfx_v8_0_ring_emit_patch_cond_exec()6350 cur = (ring->wptr & ring->buf_mask) - 1; in gfx_v8_0_ring_emit_patch_cond_exec()
95 dma->dma_out_mask = video->buf_mask; in isp_video_capture_start_streaming()198 video->buf_mask |= BIT(ivb->index); in isp_video_capture_buffer_queue()222 video->buf_mask = (1UL << video->buf_count) - 1; in isp_video_capture_buffer_queue()250 video->buf_mask &= ~BIT(buf_index); in fimc_isp_video_irq_handler()251 fimc_is_hw_set_isp_buf_mask(is, video->buf_mask); in fimc_isp_video_irq_handler()
137 unsigned int buf_mask; member
985 buf_mask
