Searched refs:base_drexi0 (Results 1 – 1 of 1) sorted by relevance
156 void __iomem *base_drexi0; member387 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGAREF); in exynos5_set_bypass_dram_timings()390 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGROW1); in exynos5_set_bypass_dram_timings()394 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGDATA1); in exynos5_set_bypass_dram_timings()398 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGPOWER1); in exynos5_set_bypass_dram_timings()427 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGAREF); in exynos5_dram_change_timings()430 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGROW0); in exynos5_dram_change_timings()434 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGDATA0); in exynos5_dram_change_timings()438 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGPOWER0); in exynos5_dram_change_timings()766 writel(PERF_CNT2, dmc->base_drexi0 + DREX_INTENS_PPC); in exynos5_dmc_start_perf_events()[all …]
