1 /*
2 * Copyright 2022 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include <linux/firmware.h>
24
25 #include "amdgpu.h"
26 #include "amdgpu_gfx.h"
27 #include "soc15.h"
28 #include "soc15d.h"
29 #include "soc15_common.h"
30 #include "vega10_enum.h"
31
32 #include "v9_structs.h"
33
34 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h"
35
36 #include "gc/gc_9_4_3_offset.h"
37 #include "gc/gc_9_4_3_sh_mask.h"
38
39 #include "gfx_v9_4_3.h"
40 #include "amdgpu_xcp.h"
41
42 MODULE_FIRMWARE("amdgpu/gc_9_4_3_mec.bin");
43 MODULE_FIRMWARE("amdgpu/gc_9_4_3_rlc.bin");
44
45 #define GFX9_MEC_HPD_SIZE 4096
46 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
47
48 #define GOLDEN_GB_ADDR_CONFIG 0x2a114042
49 #define CP_HQD_PERSISTENT_STATE_DEFAULT 0xbe05301
50
51 struct amdgpu_gfx_ras gfx_v9_4_3_ras;
52
53 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev);
54 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev);
55 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev);
56 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev);
57 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev,
58 struct amdgpu_cu_info *cu_info);
59
gfx_v9_4_3_kiq_set_resources(struct amdgpu_ring * kiq_ring,uint64_t queue_mask)60 static void gfx_v9_4_3_kiq_set_resources(struct amdgpu_ring *kiq_ring,
61 uint64_t queue_mask)
62 {
63 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
64 amdgpu_ring_write(kiq_ring,
65 PACKET3_SET_RESOURCES_VMID_MASK(0) |
66 /* vmid_mask:0* queue_type:0 (KIQ) */
67 PACKET3_SET_RESOURCES_QUEUE_TYPE(0));
68 amdgpu_ring_write(kiq_ring,
69 lower_32_bits(queue_mask)); /* queue mask lo */
70 amdgpu_ring_write(kiq_ring,
71 upper_32_bits(queue_mask)); /* queue mask hi */
72 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
73 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
74 amdgpu_ring_write(kiq_ring, 0); /* oac mask */
75 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
76 }
77
gfx_v9_4_3_kiq_map_queues(struct amdgpu_ring * kiq_ring,struct amdgpu_ring * ring)78 static void gfx_v9_4_3_kiq_map_queues(struct amdgpu_ring *kiq_ring,
79 struct amdgpu_ring *ring)
80 {
81 struct amdgpu_device *adev = kiq_ring->adev;
82 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
83 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
84 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
85
86 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
87 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
88 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
89 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
90 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
91 PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
92 PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
93 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
94 /*queue_type: normal compute queue */
95 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) |
96 /* alloc format: all_on_one_pipe */
97 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) |
98 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
99 /* num_queues: must be 1 */
100 PACKET3_MAP_QUEUES_NUM_QUEUES(1));
101 amdgpu_ring_write(kiq_ring,
102 PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
103 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
104 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
105 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
106 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
107 }
108
gfx_v9_4_3_kiq_unmap_queues(struct amdgpu_ring * kiq_ring,struct amdgpu_ring * ring,enum amdgpu_unmap_queues_action action,u64 gpu_addr,u64 seq)109 static void gfx_v9_4_3_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
110 struct amdgpu_ring *ring,
111 enum amdgpu_unmap_queues_action action,
112 u64 gpu_addr, u64 seq)
113 {
114 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
115
116 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
117 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
118 PACKET3_UNMAP_QUEUES_ACTION(action) |
119 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
120 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
121 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
122 amdgpu_ring_write(kiq_ring,
123 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
124
125 if (action == PREEMPT_QUEUES_NO_UNMAP) {
126 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
127 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
128 amdgpu_ring_write(kiq_ring, seq);
129 } else {
130 amdgpu_ring_write(kiq_ring, 0);
131 amdgpu_ring_write(kiq_ring, 0);
132 amdgpu_ring_write(kiq_ring, 0);
133 }
134 }
135
gfx_v9_4_3_kiq_query_status(struct amdgpu_ring * kiq_ring,struct amdgpu_ring * ring,u64 addr,u64 seq)136 static void gfx_v9_4_3_kiq_query_status(struct amdgpu_ring *kiq_ring,
137 struct amdgpu_ring *ring,
138 u64 addr,
139 u64 seq)
140 {
141 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
142
143 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
144 amdgpu_ring_write(kiq_ring,
145 PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
146 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
147 PACKET3_QUERY_STATUS_COMMAND(2));
148 /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
149 amdgpu_ring_write(kiq_ring,
150 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
151 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
152 amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
153 amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
154 amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
155 amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
156 }
157
gfx_v9_4_3_kiq_invalidate_tlbs(struct amdgpu_ring * kiq_ring,uint16_t pasid,uint32_t flush_type,bool all_hub)158 static void gfx_v9_4_3_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
159 uint16_t pasid, uint32_t flush_type,
160 bool all_hub)
161 {
162 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
163 amdgpu_ring_write(kiq_ring,
164 PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
165 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
166 PACKET3_INVALIDATE_TLBS_PASID(pasid) |
167 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
168 }
169
170 static const struct kiq_pm4_funcs gfx_v9_4_3_kiq_pm4_funcs = {
171 .kiq_set_resources = gfx_v9_4_3_kiq_set_resources,
172 .kiq_map_queues = gfx_v9_4_3_kiq_map_queues,
173 .kiq_unmap_queues = gfx_v9_4_3_kiq_unmap_queues,
174 .kiq_query_status = gfx_v9_4_3_kiq_query_status,
175 .kiq_invalidate_tlbs = gfx_v9_4_3_kiq_invalidate_tlbs,
176 .set_resources_size = 8,
177 .map_queues_size = 7,
178 .unmap_queues_size = 6,
179 .query_status_size = 7,
180 .invalidate_tlbs_size = 2,
181 };
182
gfx_v9_4_3_set_kiq_pm4_funcs(struct amdgpu_device * adev)183 static void gfx_v9_4_3_set_kiq_pm4_funcs(struct amdgpu_device *adev)
184 {
185 int i, num_xcc;
186
187 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
188 for (i = 0; i < num_xcc; i++)
189 adev->gfx.kiq[i].pmf = &gfx_v9_4_3_kiq_pm4_funcs;
190 }
191
gfx_v9_4_3_init_golden_registers(struct amdgpu_device * adev)192 static void gfx_v9_4_3_init_golden_registers(struct amdgpu_device *adev)
193 {
194 int i, num_xcc, dev_inst;
195
196 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
197 for (i = 0; i < num_xcc; i++) {
198 dev_inst = GET_INST(GC, i);
199
200 WREG32_SOC15(GC, dev_inst, regGB_ADDR_CONFIG,
201 GOLDEN_GB_ADDR_CONFIG);
202 /* Golden settings applied by driver for ASIC with rev_id 0 */
203 if (adev->rev_id == 0) {
204 WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL1,
205 REDUCE_FIFO_DEPTH_BY_2, 2);
206 } else {
207 WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL2,
208 SPARE, 0x1);
209 }
210 }
211 }
212
gfx_v9_4_3_write_data_to_reg(struct amdgpu_ring * ring,int eng_sel,bool wc,uint32_t reg,uint32_t val)213 static void gfx_v9_4_3_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
214 bool wc, uint32_t reg, uint32_t val)
215 {
216 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
217 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
218 WRITE_DATA_DST_SEL(0) |
219 (wc ? WR_CONFIRM : 0));
220 amdgpu_ring_write(ring, reg);
221 amdgpu_ring_write(ring, 0);
222 amdgpu_ring_write(ring, val);
223 }
224
gfx_v9_4_3_wait_reg_mem(struct amdgpu_ring * ring,int eng_sel,int mem_space,int opt,uint32_t addr0,uint32_t addr1,uint32_t ref,uint32_t mask,uint32_t inv)225 static void gfx_v9_4_3_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
226 int mem_space, int opt, uint32_t addr0,
227 uint32_t addr1, uint32_t ref, uint32_t mask,
228 uint32_t inv)
229 {
230 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
231 amdgpu_ring_write(ring,
232 /* memory (1) or register (0) */
233 (WAIT_REG_MEM_MEM_SPACE(mem_space) |
234 WAIT_REG_MEM_OPERATION(opt) | /* wait */
235 WAIT_REG_MEM_FUNCTION(3) | /* equal */
236 WAIT_REG_MEM_ENGINE(eng_sel)));
237
238 if (mem_space)
239 BUG_ON(addr0 & 0x3); /* Dword align */
240 amdgpu_ring_write(ring, addr0);
241 amdgpu_ring_write(ring, addr1);
242 amdgpu_ring_write(ring, ref);
243 amdgpu_ring_write(ring, mask);
244 amdgpu_ring_write(ring, inv); /* poll interval */
245 }
246
gfx_v9_4_3_ring_test_ring(struct amdgpu_ring * ring)247 static int gfx_v9_4_3_ring_test_ring(struct amdgpu_ring *ring)
248 {
249 uint32_t scratch_reg0_offset, xcc_offset;
250 struct amdgpu_device *adev = ring->adev;
251 uint32_t tmp = 0;
252 unsigned i;
253 int r;
254
255 /* Use register offset which is local to XCC in the packet */
256 xcc_offset = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0);
257 scratch_reg0_offset = SOC15_REG_OFFSET(GC, GET_INST(GC, ring->xcc_id), regSCRATCH_REG0);
258 WREG32(scratch_reg0_offset, 0xCAFEDEAD);
259
260 r = amdgpu_ring_alloc(ring, 3);
261 if (r)
262 return r;
263
264 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
265 amdgpu_ring_write(ring, xcc_offset - PACKET3_SET_UCONFIG_REG_START);
266 amdgpu_ring_write(ring, 0xDEADBEEF);
267 amdgpu_ring_commit(ring);
268
269 for (i = 0; i < adev->usec_timeout; i++) {
270 tmp = RREG32(scratch_reg0_offset);
271 if (tmp == 0xDEADBEEF)
272 break;
273 udelay(1);
274 }
275
276 if (i >= adev->usec_timeout)
277 r = -ETIMEDOUT;
278 return r;
279 }
280
gfx_v9_4_3_ring_test_ib(struct amdgpu_ring * ring,long timeout)281 static int gfx_v9_4_3_ring_test_ib(struct amdgpu_ring *ring, long timeout)
282 {
283 struct amdgpu_device *adev = ring->adev;
284 struct amdgpu_ib ib;
285 struct dma_fence *f = NULL;
286
287 unsigned index;
288 uint64_t gpu_addr;
289 uint32_t tmp;
290 long r;
291
292 r = amdgpu_device_wb_get(adev, &index);
293 if (r)
294 return r;
295
296 gpu_addr = adev->wb.gpu_addr + (index * 4);
297 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
298 memset(&ib, 0, sizeof(ib));
299 r = amdgpu_ib_get(adev, NULL, 16,
300 AMDGPU_IB_POOL_DIRECT, &ib);
301 if (r)
302 goto err1;
303
304 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
305 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
306 ib.ptr[2] = lower_32_bits(gpu_addr);
307 ib.ptr[3] = upper_32_bits(gpu_addr);
308 ib.ptr[4] = 0xDEADBEEF;
309 ib.length_dw = 5;
310
311 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
312 if (r)
313 goto err2;
314
315 r = dma_fence_wait_timeout(f, false, timeout);
316 if (r == 0) {
317 r = -ETIMEDOUT;
318 goto err2;
319 } else if (r < 0) {
320 goto err2;
321 }
322
323 tmp = adev->wb.wb[index];
324 if (tmp == 0xDEADBEEF)
325 r = 0;
326 else
327 r = -EINVAL;
328
329 err2:
330 amdgpu_ib_free(adev, &ib, NULL);
331 dma_fence_put(f);
332 err1:
333 amdgpu_device_wb_free(adev, index);
334 return r;
335 }
336
337
338 /* This value might differs per partition */
gfx_v9_4_3_get_gpu_clock_counter(struct amdgpu_device * adev)339 static uint64_t gfx_v9_4_3_get_gpu_clock_counter(struct amdgpu_device *adev)
340 {
341 uint64_t clock;
342
343 mutex_lock(&adev->gfx.gpu_clock_mutex);
344 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
345 clock = (uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_LSB) |
346 ((uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
347 mutex_unlock(&adev->gfx.gpu_clock_mutex);
348
349 return clock;
350 }
351
gfx_v9_4_3_free_microcode(struct amdgpu_device * adev)352 static void gfx_v9_4_3_free_microcode(struct amdgpu_device *adev)
353 {
354 amdgpu_ucode_release(&adev->gfx.pfp_fw);
355 amdgpu_ucode_release(&adev->gfx.me_fw);
356 amdgpu_ucode_release(&adev->gfx.ce_fw);
357 amdgpu_ucode_release(&adev->gfx.rlc_fw);
358 amdgpu_ucode_release(&adev->gfx.mec_fw);
359 amdgpu_ucode_release(&adev->gfx.mec2_fw);
360
361 kfree(adev->gfx.rlc.register_list_format);
362 }
363
gfx_v9_4_3_init_rlc_microcode(struct amdgpu_device * adev,const char * chip_name)364 static int gfx_v9_4_3_init_rlc_microcode(struct amdgpu_device *adev,
365 const char *chip_name)
366 {
367 char fw_name[30];
368 int err;
369 const struct rlc_firmware_header_v2_0 *rlc_hdr;
370 uint16_t version_major;
371 uint16_t version_minor;
372
373 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
374
375 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name);
376 if (err)
377 goto out;
378 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
379
380 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
381 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
382 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor);
383 out:
384 if (err)
385 amdgpu_ucode_release(&adev->gfx.rlc_fw);
386
387 return err;
388 }
389
gfx_v9_4_3_should_disable_gfxoff(struct pci_dev * pdev)390 static bool gfx_v9_4_3_should_disable_gfxoff(struct pci_dev *pdev)
391 {
392 return true;
393 }
394
gfx_v9_4_3_check_if_need_gfxoff(struct amdgpu_device * adev)395 static void gfx_v9_4_3_check_if_need_gfxoff(struct amdgpu_device *adev)
396 {
397 if (gfx_v9_4_3_should_disable_gfxoff(adev->pdev))
398 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
399 }
400
gfx_v9_4_3_init_cp_compute_microcode(struct amdgpu_device * adev,const char * chip_name)401 static int gfx_v9_4_3_init_cp_compute_microcode(struct amdgpu_device *adev,
402 const char *chip_name)
403 {
404 char fw_name[30];
405 int err;
406
407 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
408
409 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name);
410 if (err)
411 goto out;
412 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1);
413 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT);
414
415 adev->gfx.mec2_fw_version = adev->gfx.mec_fw_version;
416 adev->gfx.mec2_feature_version = adev->gfx.mec_feature_version;
417
418 gfx_v9_4_3_check_if_need_gfxoff(adev);
419
420 out:
421 if (err)
422 amdgpu_ucode_release(&adev->gfx.mec_fw);
423 return err;
424 }
425
gfx_v9_4_3_init_microcode(struct amdgpu_device * adev)426 static int gfx_v9_4_3_init_microcode(struct amdgpu_device *adev)
427 {
428 const char *chip_name;
429 int r;
430
431 chip_name = "gc_9_4_3";
432
433 r = gfx_v9_4_3_init_rlc_microcode(adev, chip_name);
434 if (r)
435 return r;
436
437 r = gfx_v9_4_3_init_cp_compute_microcode(adev, chip_name);
438 if (r)
439 return r;
440
441 return r;
442 }
443
gfx_v9_4_3_mec_fini(struct amdgpu_device * adev)444 static void gfx_v9_4_3_mec_fini(struct amdgpu_device *adev)
445 {
446 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
447 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
448 }
449
gfx_v9_4_3_mec_init(struct amdgpu_device * adev)450 static int gfx_v9_4_3_mec_init(struct amdgpu_device *adev)
451 {
452 int r, i, num_xcc;
453 u32 *hpd;
454 const __le32 *fw_data;
455 unsigned fw_size;
456 u32 *fw;
457 size_t mec_hpd_size;
458
459 const struct gfx_firmware_header_v1_0 *mec_hdr;
460
461 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
462 for (i = 0; i < num_xcc; i++)
463 bitmap_zero(adev->gfx.mec_bitmap[i].queue_bitmap,
464 AMDGPU_MAX_COMPUTE_QUEUES);
465
466 /* take ownership of the relevant compute queues */
467 amdgpu_gfx_compute_queue_acquire(adev);
468 mec_hpd_size =
469 adev->gfx.num_compute_rings * num_xcc * GFX9_MEC_HPD_SIZE;
470 if (mec_hpd_size) {
471 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
472 AMDGPU_GEM_DOMAIN_VRAM |
473 AMDGPU_GEM_DOMAIN_GTT,
474 &adev->gfx.mec.hpd_eop_obj,
475 &adev->gfx.mec.hpd_eop_gpu_addr,
476 (void **)&hpd);
477 if (r) {
478 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
479 gfx_v9_4_3_mec_fini(adev);
480 return r;
481 }
482
483 if (amdgpu_emu_mode == 1) {
484 for (i = 0; i < mec_hpd_size / 4; i++) {
485 memset((void *)(hpd + i), 0, 4);
486 if (i % 50 == 0)
487 msleep(1);
488 }
489 } else {
490 memset(hpd, 0, mec_hpd_size);
491 }
492
493 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
494 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
495 }
496
497 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
498
499 fw_data = (const __le32 *)
500 (adev->gfx.mec_fw->data +
501 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
502 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
503
504 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
505 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
506 &adev->gfx.mec.mec_fw_obj,
507 &adev->gfx.mec.mec_fw_gpu_addr,
508 (void **)&fw);
509 if (r) {
510 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r);
511 gfx_v9_4_3_mec_fini(adev);
512 return r;
513 }
514
515 memcpy(fw, fw_data, fw_size);
516
517 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
518 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
519
520 return 0;
521 }
522
gfx_v9_4_3_xcc_select_se_sh(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 instance,int xcc_id)523 static void gfx_v9_4_3_xcc_select_se_sh(struct amdgpu_device *adev, u32 se_num,
524 u32 sh_num, u32 instance, int xcc_id)
525 {
526 u32 data;
527
528 if (instance == 0xffffffff)
529 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
530 INSTANCE_BROADCAST_WRITES, 1);
531 else
532 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
533 INSTANCE_INDEX, instance);
534
535 if (se_num == 0xffffffff)
536 data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
537 SE_BROADCAST_WRITES, 1);
538 else
539 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
540
541 if (sh_num == 0xffffffff)
542 data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
543 SH_BROADCAST_WRITES, 1);
544 else
545 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
546
547 WREG32_SOC15_RLC_SHADOW_EX(reg, GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX, data);
548 }
549
wave_read_ind(struct amdgpu_device * adev,uint32_t xcc_id,uint32_t simd,uint32_t wave,uint32_t address)550 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t address)
551 {
552 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX,
553 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
554 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
555 (address << SQ_IND_INDEX__INDEX__SHIFT) |
556 (SQ_IND_INDEX__FORCE_READ_MASK));
557 return RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA);
558 }
559
wave_read_regs(struct amdgpu_device * adev,uint32_t xcc_id,uint32_t simd,uint32_t wave,uint32_t thread,uint32_t regno,uint32_t num,uint32_t * out)560 static void wave_read_regs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
561 uint32_t wave, uint32_t thread,
562 uint32_t regno, uint32_t num, uint32_t *out)
563 {
564 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX,
565 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
566 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
567 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
568 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
569 (SQ_IND_INDEX__FORCE_READ_MASK) |
570 (SQ_IND_INDEX__AUTO_INCR_MASK));
571 while (num--)
572 *(out++) = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA);
573 }
574
gfx_v9_4_3_read_wave_data(struct amdgpu_device * adev,uint32_t xcc_id,uint32_t simd,uint32_t wave,uint32_t * dst,int * no_fields)575 static void gfx_v9_4_3_read_wave_data(struct amdgpu_device *adev,
576 uint32_t xcc_id, uint32_t simd, uint32_t wave,
577 uint32_t *dst, int *no_fields)
578 {
579 /* type 1 wave data */
580 dst[(*no_fields)++] = 1;
581 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_STATUS);
582 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_LO);
583 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_HI);
584 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_LO);
585 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_HI);
586 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_HW_ID);
587 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW0);
588 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW1);
589 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_GPR_ALLOC);
590 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_LDS_ALLOC);
591 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_TRAPSTS);
592 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_STS);
593 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_DBG0);
594 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_M0);
595 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_MODE);
596 }
597
gfx_v9_4_3_read_wave_sgprs(struct amdgpu_device * adev,uint32_t xcc_id,uint32_t simd,uint32_t wave,uint32_t start,uint32_t size,uint32_t * dst)598 static void gfx_v9_4_3_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
599 uint32_t wave, uint32_t start,
600 uint32_t size, uint32_t *dst)
601 {
602 wave_read_regs(adev, xcc_id, simd, wave, 0,
603 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
604 }
605
gfx_v9_4_3_read_wave_vgprs(struct amdgpu_device * adev,uint32_t xcc_id,uint32_t simd,uint32_t wave,uint32_t thread,uint32_t start,uint32_t size,uint32_t * dst)606 static void gfx_v9_4_3_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
607 uint32_t wave, uint32_t thread,
608 uint32_t start, uint32_t size,
609 uint32_t *dst)
610 {
611 wave_read_regs(adev, xcc_id, simd, wave, thread,
612 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
613 }
614
gfx_v9_4_3_select_me_pipe_q(struct amdgpu_device * adev,u32 me,u32 pipe,u32 q,u32 vm,u32 xcc_id)615 static void gfx_v9_4_3_select_me_pipe_q(struct amdgpu_device *adev,
616 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id)
617 {
618 soc15_grbm_select(adev, me, pipe, q, vm, GET_INST(GC, xcc_id));
619 }
620
621
gfx_v9_4_3_switch_compute_partition(struct amdgpu_device * adev,int num_xccs_per_xcp)622 static int gfx_v9_4_3_switch_compute_partition(struct amdgpu_device *adev,
623 int num_xccs_per_xcp)
624 {
625 int ret, i, num_xcc;
626 u32 tmp = 0, regval;
627
628 if (adev->psp.funcs) {
629 ret = psp_spatial_partition(&adev->psp,
630 NUM_XCC(adev->gfx.xcc_mask) /
631 num_xccs_per_xcp);
632 if (ret)
633 return ret;
634 }
635
636 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
637
638 for (i = 0; i < num_xcc; i++) {
639 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP,
640 num_xccs_per_xcp);
641 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, VIRTUAL_XCC_ID,
642 i % num_xccs_per_xcp);
643 regval = RREG32_SOC15(GC, GET_INST(GC, i), regCP_HYP_XCP_CTL);
644 if (regval != tmp)
645 WREG32_SOC15(GC, GET_INST(GC, i), regCP_HYP_XCP_CTL,
646 tmp);
647 }
648
649 adev->gfx.num_xcc_per_xcp = num_xccs_per_xcp;
650
651 return 0;
652 }
653
gfx_v9_4_3_ih_to_xcc_inst(struct amdgpu_device * adev,int ih_node)654 static int gfx_v9_4_3_ih_to_xcc_inst(struct amdgpu_device *adev, int ih_node)
655 {
656 int xcc;
657
658 xcc = hweight8(adev->gfx.xcc_mask & GENMASK(ih_node / 2, 0));
659 if (!xcc) {
660 dev_err(adev->dev, "Couldn't find xcc mapping from IH node");
661 return -EINVAL;
662 }
663
664 return xcc - 1;
665 }
666
667 static const struct amdgpu_gfx_funcs gfx_v9_4_3_gfx_funcs = {
668 .get_gpu_clock_counter = &gfx_v9_4_3_get_gpu_clock_counter,
669 .select_se_sh = &gfx_v9_4_3_xcc_select_se_sh,
670 .read_wave_data = &gfx_v9_4_3_read_wave_data,
671 .read_wave_sgprs = &gfx_v9_4_3_read_wave_sgprs,
672 .read_wave_vgprs = &gfx_v9_4_3_read_wave_vgprs,
673 .select_me_pipe_q = &gfx_v9_4_3_select_me_pipe_q,
674 .switch_partition_mode = &gfx_v9_4_3_switch_compute_partition,
675 .ih_node_to_logical_xcc = &gfx_v9_4_3_ih_to_xcc_inst,
676 };
677
gfx_v9_4_3_gpu_early_init(struct amdgpu_device * adev)678 static int gfx_v9_4_3_gpu_early_init(struct amdgpu_device *adev)
679 {
680 u32 gb_addr_config;
681
682 adev->gfx.funcs = &gfx_v9_4_3_gfx_funcs;
683 adev->gfx.ras = &gfx_v9_4_3_ras;
684
685 switch (adev->ip_versions[GC_HWIP][0]) {
686 case IP_VERSION(9, 4, 3):
687 adev->gfx.config.max_hw_contexts = 8;
688 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
689 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
690 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
691 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
692 gb_addr_config = RREG32_SOC15(GC, GET_INST(GC, 0), regGB_ADDR_CONFIG);
693 break;
694 default:
695 BUG();
696 break;
697 }
698
699 adev->gfx.config.gb_addr_config = gb_addr_config;
700
701 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
702 REG_GET_FIELD(
703 adev->gfx.config.gb_addr_config,
704 GB_ADDR_CONFIG,
705 NUM_PIPES);
706
707 adev->gfx.config.max_tile_pipes =
708 adev->gfx.config.gb_addr_config_fields.num_pipes;
709
710 adev->gfx.config.gb_addr_config_fields.num_banks = 1 <<
711 REG_GET_FIELD(
712 adev->gfx.config.gb_addr_config,
713 GB_ADDR_CONFIG,
714 NUM_BANKS);
715 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
716 REG_GET_FIELD(
717 adev->gfx.config.gb_addr_config,
718 GB_ADDR_CONFIG,
719 MAX_COMPRESSED_FRAGS);
720 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
721 REG_GET_FIELD(
722 adev->gfx.config.gb_addr_config,
723 GB_ADDR_CONFIG,
724 NUM_RB_PER_SE);
725 adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
726 REG_GET_FIELD(
727 adev->gfx.config.gb_addr_config,
728 GB_ADDR_CONFIG,
729 NUM_SHADER_ENGINES);
730 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
731 REG_GET_FIELD(
732 adev->gfx.config.gb_addr_config,
733 GB_ADDR_CONFIG,
734 PIPE_INTERLEAVE_SIZE));
735
736 return 0;
737 }
738
gfx_v9_4_3_compute_ring_init(struct amdgpu_device * adev,int ring_id,int xcc_id,int mec,int pipe,int queue)739 static int gfx_v9_4_3_compute_ring_init(struct amdgpu_device *adev, int ring_id,
740 int xcc_id, int mec, int pipe, int queue)
741 {
742 unsigned irq_type;
743 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
744 unsigned int hw_prio;
745 uint32_t xcc_doorbell_start;
746
747 ring = &adev->gfx.compute_ring[xcc_id * adev->gfx.num_compute_rings +
748 ring_id];
749
750 /* mec0 is me1 */
751 ring->xcc_id = xcc_id;
752 ring->me = mec + 1;
753 ring->pipe = pipe;
754 ring->queue = queue;
755
756 ring->ring_obj = NULL;
757 ring->use_doorbell = true;
758 xcc_doorbell_start = adev->doorbell_index.mec_ring0 +
759 xcc_id * adev->doorbell_index.xcc_doorbell_range;
760 ring->doorbell_index = (xcc_doorbell_start + ring_id) << 1;
761 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr +
762 (ring_id + xcc_id * adev->gfx.num_compute_rings) *
763 GFX9_MEC_HPD_SIZE;
764 ring->vm_hub = AMDGPU_GFXHUB(xcc_id);
765 sprintf(ring->name, "comp_%d.%d.%d.%d",
766 ring->xcc_id, ring->me, ring->pipe, ring->queue);
767
768 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
769 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
770 + ring->pipe;
771 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
772 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
773 /* type-2 packets are deprecated on MEC, use type-3 instead */
774 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
775 hw_prio, NULL);
776 }
777
gfx_v9_4_3_sw_init(void * handle)778 static int gfx_v9_4_3_sw_init(void *handle)
779 {
780 int i, j, k, r, ring_id, xcc_id, num_xcc;
781 struct amdgpu_kiq *kiq;
782 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
783
784 adev->gfx.mec.num_mec = 2;
785 adev->gfx.mec.num_pipe_per_mec = 4;
786 adev->gfx.mec.num_queue_per_pipe = 8;
787
788 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
789
790 /* EOP Event */
791 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq);
792 if (r)
793 return r;
794
795 /* Privileged reg */
796 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT,
797 &adev->gfx.priv_reg_irq);
798 if (r)
799 return r;
800
801 /* Privileged inst */
802 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT,
803 &adev->gfx.priv_inst_irq);
804 if (r)
805 return r;
806
807 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
808
809 r = adev->gfx.rlc.funcs->init(adev);
810 if (r) {
811 DRM_ERROR("Failed to init rlc BOs!\n");
812 return r;
813 }
814
815 r = gfx_v9_4_3_mec_init(adev);
816 if (r) {
817 DRM_ERROR("Failed to init MEC BOs!\n");
818 return r;
819 }
820
821 /* set up the compute queues - allocate horizontally across pipes */
822 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) {
823 ring_id = 0;
824 for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
825 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
826 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec;
827 k++) {
828 if (!amdgpu_gfx_is_mec_queue_enabled(
829 adev, xcc_id, i, k, j))
830 continue;
831
832 r = gfx_v9_4_3_compute_ring_init(adev,
833 ring_id,
834 xcc_id,
835 i, k, j);
836 if (r)
837 return r;
838
839 ring_id++;
840 }
841 }
842 }
843
844 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE, xcc_id);
845 if (r) {
846 DRM_ERROR("Failed to init KIQ BOs!\n");
847 return r;
848 }
849
850 kiq = &adev->gfx.kiq[xcc_id];
851 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq, xcc_id);
852 if (r)
853 return r;
854
855 /* create MQD for all compute queues as wel as KIQ for SRIOV case */
856 r = amdgpu_gfx_mqd_sw_init(adev,
857 sizeof(struct v9_mqd_allocation), xcc_id);
858 if (r)
859 return r;
860 }
861
862 r = gfx_v9_4_3_gpu_early_init(adev);
863 if (r)
864 return r;
865
866 r = amdgpu_gfx_ras_sw_init(adev);
867 if (r)
868 return r;
869
870
871 if (!amdgpu_sriov_vf(adev))
872 r = amdgpu_gfx_sysfs_init(adev);
873
874 return r;
875 }
876
gfx_v9_4_3_sw_fini(void * handle)877 static int gfx_v9_4_3_sw_fini(void *handle)
878 {
879 int i, num_xcc;
880 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
881
882 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
883 for (i = 0; i < adev->gfx.num_compute_rings * num_xcc; i++)
884 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
885
886 for (i = 0; i < num_xcc; i++) {
887 amdgpu_gfx_mqd_sw_fini(adev, i);
888 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[i].ring);
889 amdgpu_gfx_kiq_fini(adev, i);
890 }
891
892 gfx_v9_4_3_mec_fini(adev);
893 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj);
894 gfx_v9_4_3_free_microcode(adev);
895 if (!amdgpu_sriov_vf(adev))
896 amdgpu_gfx_sysfs_fini(adev);
897
898 return 0;
899 }
900
901 #define DEFAULT_SH_MEM_BASES (0x6000)
gfx_v9_4_3_xcc_init_compute_vmid(struct amdgpu_device * adev,int xcc_id)902 static void gfx_v9_4_3_xcc_init_compute_vmid(struct amdgpu_device *adev,
903 int xcc_id)
904 {
905 int i;
906 uint32_t sh_mem_config;
907 uint32_t sh_mem_bases;
908 uint32_t data;
909
910 /*
911 * Configure apertures:
912 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
913 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
914 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
915 */
916 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
917
918 sh_mem_config = SH_MEM_ADDRESS_MODE_64 |
919 SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
920 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
921
922 mutex_lock(&adev->srbm_mutex);
923 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
924 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id));
925 /* CP and shaders */
926 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_CONFIG, sh_mem_config);
927 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, sh_mem_bases);
928
929 /* Enable trap for each kfd vmid. */
930 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL);
931 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);
932 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL, data);
933 }
934 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));
935 mutex_unlock(&adev->srbm_mutex);
936
937 /* Initialize all compute VMIDs to have no GDS, GWS, or OA
938 acccess. These should be enabled by FW for target VMIDs. */
939 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
940 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * i, 0);
941 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * i, 0);
942 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, i, 0);
943 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, i, 0);
944 }
945 }
946
gfx_v9_4_3_xcc_init_gds_vmid(struct amdgpu_device * adev,int xcc_id)947 static void gfx_v9_4_3_xcc_init_gds_vmid(struct amdgpu_device *adev, int xcc_id)
948 {
949 int vmid;
950
951 /*
952 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
953 * access. Compute VMIDs should be enabled by FW for target VMIDs,
954 * the driver can enable them for graphics. VMID0 should maintain
955 * access so that HWS firmware can save/restore entries.
956 */
957 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
958 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * vmid, 0);
959 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * vmid, 0);
960 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, vmid, 0);
961 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, vmid, 0);
962 }
963 }
964
gfx_v9_4_3_xcc_constants_init(struct amdgpu_device * adev,int xcc_id)965 static void gfx_v9_4_3_xcc_constants_init(struct amdgpu_device *adev,
966 int xcc_id)
967 {
968 u32 tmp;
969 int i;
970
971 /* XXX SH_MEM regs */
972 /* where to put LDS, scratch, GPUVM in FSA64 space */
973 mutex_lock(&adev->srbm_mutex);
974 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) {
975 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id));
976 /* CP and shaders */
977 if (i == 0) {
978 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
979 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
980 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE,
981 !!adev->gmc.noretry);
982 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id),
983 regSH_MEM_CONFIG, tmp);
984 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id),
985 regSH_MEM_BASES, 0);
986 } else {
987 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
988 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
989 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE,
990 !!adev->gmc.noretry);
991 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id),
992 regSH_MEM_CONFIG, tmp);
993 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
994 (adev->gmc.private_aperture_start >>
995 48));
996 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
997 (adev->gmc.shared_aperture_start >>
998 48));
999 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id),
1000 regSH_MEM_BASES, tmp);
1001 }
1002 }
1003 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, 0));
1004
1005 mutex_unlock(&adev->srbm_mutex);
1006
1007 gfx_v9_4_3_xcc_init_compute_vmid(adev, xcc_id);
1008 gfx_v9_4_3_xcc_init_gds_vmid(adev, xcc_id);
1009 }
1010
gfx_v9_4_3_constants_init(struct amdgpu_device * adev)1011 static void gfx_v9_4_3_constants_init(struct amdgpu_device *adev)
1012 {
1013 int i, num_xcc;
1014
1015 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1016
1017 gfx_v9_4_3_get_cu_info(adev, &adev->gfx.cu_info);
1018 adev->gfx.config.db_debug2 =
1019 RREG32_SOC15(GC, GET_INST(GC, 0), regDB_DEBUG2);
1020
1021 for (i = 0; i < num_xcc; i++)
1022 gfx_v9_4_3_xcc_constants_init(adev, i);
1023 }
1024
1025 static void
gfx_v9_4_3_xcc_enable_save_restore_machine(struct amdgpu_device * adev,int xcc_id)1026 gfx_v9_4_3_xcc_enable_save_restore_machine(struct amdgpu_device *adev,
1027 int xcc_id)
1028 {
1029 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_SRM_CNTL, SRM_ENABLE, 1);
1030 }
1031
gfx_v9_4_3_xcc_init_pg(struct amdgpu_device * adev,int xcc_id)1032 static void gfx_v9_4_3_xcc_init_pg(struct amdgpu_device *adev, int xcc_id)
1033 {
1034 /*
1035 * Rlc save restore list is workable since v2_1.
1036 * And it's needed by gfxoff feature.
1037 */
1038 if (adev->gfx.rlc.is_rlc_v2_1)
1039 gfx_v9_4_3_xcc_enable_save_restore_machine(adev, xcc_id);
1040 }
1041
gfx_v9_4_3_xcc_disable_gpa_mode(struct amdgpu_device * adev,int xcc_id)1042 static void gfx_v9_4_3_xcc_disable_gpa_mode(struct amdgpu_device *adev, int xcc_id)
1043 {
1044 uint32_t data;
1045
1046 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG);
1047 data |= CPC_PSP_DEBUG__UTCL2IUGPAOVERRIDE_MASK;
1048 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG, data);
1049 }
1050
gfx_v9_4_3_is_rlc_enabled(struct amdgpu_device * adev)1051 static bool gfx_v9_4_3_is_rlc_enabled(struct amdgpu_device *adev)
1052 {
1053 uint32_t rlc_setting;
1054
1055 /* if RLC is not enabled, do nothing */
1056 rlc_setting = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CNTL);
1057 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
1058 return false;
1059
1060 return true;
1061 }
1062
gfx_v9_4_3_xcc_set_safe_mode(struct amdgpu_device * adev,int xcc_id)1063 static void gfx_v9_4_3_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id)
1064 {
1065 uint32_t data;
1066 unsigned i;
1067
1068 data = RLC_SAFE_MODE__CMD_MASK;
1069 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
1070 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data);
1071
1072 /* wait for RLC_SAFE_MODE */
1073 for (i = 0; i < adev->usec_timeout; i++) {
1074 if (!REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
1075 break;
1076 udelay(1);
1077 }
1078 }
1079
gfx_v9_4_3_xcc_unset_safe_mode(struct amdgpu_device * adev,int xcc_id)1080 static void gfx_v9_4_3_xcc_unset_safe_mode(struct amdgpu_device *adev,
1081 int xcc_id)
1082 {
1083 uint32_t data;
1084
1085 data = RLC_SAFE_MODE__CMD_MASK;
1086 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data);
1087 }
1088
gfx_v9_4_3_init_rlcg_reg_access_ctrl(struct amdgpu_device * adev)1089 static void gfx_v9_4_3_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev)
1090 {
1091 int xcc_id, num_xcc;
1092 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl;
1093
1094 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1095 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) {
1096 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[GET_INST(GC, xcc_id)];
1097 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG0);
1098 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG1);
1099 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG2);
1100 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG3);
1101 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_CNTL);
1102 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX);
1103 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPARE_INT);
1104 }
1105 }
1106
gfx_v9_4_3_rlc_init(struct amdgpu_device * adev)1107 static int gfx_v9_4_3_rlc_init(struct amdgpu_device *adev)
1108 {
1109 /* init spm vmid with 0xf */
1110 if (adev->gfx.rlc.funcs->update_spm_vmid)
1111 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
1112
1113 return 0;
1114 }
1115
gfx_v9_4_3_xcc_wait_for_rlc_serdes(struct amdgpu_device * adev,int xcc_id)1116 static void gfx_v9_4_3_xcc_wait_for_rlc_serdes(struct amdgpu_device *adev,
1117 int xcc_id)
1118 {
1119 u32 i, j, k;
1120 u32 mask;
1121
1122 mutex_lock(&adev->grbm_idx_mutex);
1123 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1124 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1125 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff,
1126 xcc_id);
1127 for (k = 0; k < adev->usec_timeout; k++) {
1128 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_CU_MASTER_BUSY) == 0)
1129 break;
1130 udelay(1);
1131 }
1132 if (k == adev->usec_timeout) {
1133 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff,
1134 0xffffffff,
1135 0xffffffff, xcc_id);
1136 mutex_unlock(&adev->grbm_idx_mutex);
1137 DRM_INFO("Timeout wait for RLC serdes %u,%u\n",
1138 i, j);
1139 return;
1140 }
1141 }
1142 }
1143 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff,
1144 xcc_id);
1145 mutex_unlock(&adev->grbm_idx_mutex);
1146
1147 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
1148 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
1149 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
1150 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
1151 for (k = 0; k < adev->usec_timeout; k++) {
1152 if ((RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
1153 break;
1154 udelay(1);
1155 }
1156 }
1157
gfx_v9_4_3_xcc_enable_gui_idle_interrupt(struct amdgpu_device * adev,bool enable,int xcc_id)1158 static void gfx_v9_4_3_xcc_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1159 bool enable, int xcc_id)
1160 {
1161 u32 tmp;
1162
1163 /* These interrupts should be enabled to drive DS clock */
1164
1165 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0);
1166
1167 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
1168 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
1169 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
1170
1171 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0, tmp);
1172 }
1173
gfx_v9_4_3_xcc_rlc_stop(struct amdgpu_device * adev,int xcc_id)1174 static void gfx_v9_4_3_xcc_rlc_stop(struct amdgpu_device *adev, int xcc_id)
1175 {
1176 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL,
1177 RLC_ENABLE_F32, 0);
1178 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id);
1179 gfx_v9_4_3_xcc_wait_for_rlc_serdes(adev, xcc_id);
1180 }
1181
gfx_v9_4_3_rlc_stop(struct amdgpu_device * adev)1182 static void gfx_v9_4_3_rlc_stop(struct amdgpu_device *adev)
1183 {
1184 int i, num_xcc;
1185
1186 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1187 for (i = 0; i < num_xcc; i++)
1188 gfx_v9_4_3_xcc_rlc_stop(adev, i);
1189 }
1190
gfx_v9_4_3_xcc_rlc_reset(struct amdgpu_device * adev,int xcc_id)1191 static void gfx_v9_4_3_xcc_rlc_reset(struct amdgpu_device *adev, int xcc_id)
1192 {
1193 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET,
1194 SOFT_RESET_RLC, 1);
1195 udelay(50);
1196 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET,
1197 SOFT_RESET_RLC, 0);
1198 udelay(50);
1199 }
1200
gfx_v9_4_3_rlc_reset(struct amdgpu_device * adev)1201 static void gfx_v9_4_3_rlc_reset(struct amdgpu_device *adev)
1202 {
1203 int i, num_xcc;
1204
1205 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1206 for (i = 0; i < num_xcc; i++)
1207 gfx_v9_4_3_xcc_rlc_reset(adev, i);
1208 }
1209
gfx_v9_4_3_xcc_rlc_start(struct amdgpu_device * adev,int xcc_id)1210 static void gfx_v9_4_3_xcc_rlc_start(struct amdgpu_device *adev, int xcc_id)
1211 {
1212 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL,
1213 RLC_ENABLE_F32, 1);
1214 udelay(50);
1215
1216 /* carrizo do enable cp interrupt after cp inited */
1217 if (!(adev->flags & AMD_IS_APU)) {
1218 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id);
1219 udelay(50);
1220 }
1221 }
1222
gfx_v9_4_3_rlc_start(struct amdgpu_device * adev)1223 static void gfx_v9_4_3_rlc_start(struct amdgpu_device *adev)
1224 {
1225 #ifdef AMDGPU_RLC_DEBUG_RETRY
1226 u32 rlc_ucode_ver;
1227 #endif
1228 int i, num_xcc;
1229
1230 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1231 for (i = 0; i < num_xcc; i++) {
1232 gfx_v9_4_3_xcc_rlc_start(adev, i);
1233 #ifdef AMDGPU_RLC_DEBUG_RETRY
1234 /* RLC_GPM_GENERAL_6 : RLC Ucode version */
1235 rlc_ucode_ver = RREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_6);
1236 if (rlc_ucode_ver == 0x108) {
1237 dev_info(adev->dev,
1238 "Using rlc debug ucode. regRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n",
1239 rlc_ucode_ver, adev->gfx.rlc_fw_version);
1240 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles,
1241 * default is 0x9C4 to create a 100us interval */
1242 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_TIMER_INT_3, 0x9C4);
1243 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr
1244 * to disable the page fault retry interrupts, default is
1245 * 0x100 (256) */
1246 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_12, 0x100);
1247 }
1248 #endif
1249 }
1250 }
1251
gfx_v9_4_3_xcc_rlc_load_microcode(struct amdgpu_device * adev,int xcc_id)1252 static int gfx_v9_4_3_xcc_rlc_load_microcode(struct amdgpu_device *adev,
1253 int xcc_id)
1254 {
1255 const struct rlc_firmware_header_v2_0 *hdr;
1256 const __le32 *fw_data;
1257 unsigned i, fw_size;
1258
1259 if (!adev->gfx.rlc_fw)
1260 return -EINVAL;
1261
1262 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
1263 amdgpu_ucode_print_rlc_hdr(&hdr->header);
1264
1265 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1266 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1267 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
1268
1269 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR,
1270 RLCG_UCODE_LOADING_START_ADDRESS);
1271 for (i = 0; i < fw_size; i++) {
1272 if (amdgpu_emu_mode == 1 && i % 100 == 0) {
1273 dev_info(adev->dev, "Write RLC ucode data %u DWs\n", i);
1274 msleep(1);
1275 }
1276 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
1277 }
1278 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
1279
1280 return 0;
1281 }
1282
gfx_v9_4_3_xcc_rlc_resume(struct amdgpu_device * adev,int xcc_id)1283 static int gfx_v9_4_3_xcc_rlc_resume(struct amdgpu_device *adev, int xcc_id)
1284 {
1285 int r;
1286
1287 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1288 gfx_v9_4_3_xcc_rlc_stop(adev, xcc_id);
1289 /* legacy rlc firmware loading */
1290 r = gfx_v9_4_3_xcc_rlc_load_microcode(adev, xcc_id);
1291 if (r)
1292 return r;
1293 gfx_v9_4_3_xcc_rlc_start(adev, xcc_id);
1294 }
1295
1296 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id);
1297 /* disable CG */
1298 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, 0);
1299 gfx_v9_4_3_xcc_init_pg(adev, xcc_id);
1300 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id);
1301
1302 return 0;
1303 }
1304
gfx_v9_4_3_rlc_resume(struct amdgpu_device * adev)1305 static int gfx_v9_4_3_rlc_resume(struct amdgpu_device *adev)
1306 {
1307 int r, i, num_xcc;
1308
1309 if (amdgpu_sriov_vf(adev))
1310 return 0;
1311
1312 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1313 for (i = 0; i < num_xcc; i++) {
1314 r = gfx_v9_4_3_xcc_rlc_resume(adev, i);
1315 if (r)
1316 return r;
1317 }
1318
1319 return 0;
1320 }
1321
gfx_v9_4_3_update_spm_vmid(struct amdgpu_device * adev,unsigned vmid)1322 static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev,
1323 unsigned vmid)
1324 {
1325 u32 reg, data;
1326
1327 reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL);
1328 if (amdgpu_sriov_is_pp_one_vf(adev))
1329 data = RREG32_NO_KIQ(reg);
1330 else
1331 data = RREG32(reg);
1332
1333 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
1334 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
1335
1336 if (amdgpu_sriov_is_pp_one_vf(adev))
1337 WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data);
1338 else
1339 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data);
1340 }
1341
1342 static const struct soc15_reg_rlcg rlcg_access_gc_9_4_3[] = {
1343 {SOC15_REG_ENTRY(GC, 0, regGRBM_GFX_INDEX)},
1344 {SOC15_REG_ENTRY(GC, 0, regSQ_IND_INDEX)},
1345 };
1346
gfx_v9_4_3_check_rlcg_range(struct amdgpu_device * adev,uint32_t offset,struct soc15_reg_rlcg * entries,int arr_size)1347 static bool gfx_v9_4_3_check_rlcg_range(struct amdgpu_device *adev,
1348 uint32_t offset,
1349 struct soc15_reg_rlcg *entries, int arr_size)
1350 {
1351 int i, inst;
1352 uint32_t reg;
1353
1354 if (!entries)
1355 return false;
1356
1357 for (i = 0; i < arr_size; i++) {
1358 const struct soc15_reg_rlcg *entry;
1359
1360 entry = &entries[i];
1361 inst = adev->ip_map.logical_to_dev_inst ?
1362 adev->ip_map.logical_to_dev_inst(
1363 adev, entry->hwip, entry->instance) :
1364 entry->instance;
1365 reg = adev->reg_offset[entry->hwip][inst][entry->segment] +
1366 entry->reg;
1367 if (offset == reg)
1368 return true;
1369 }
1370
1371 return false;
1372 }
1373
gfx_v9_4_3_is_rlcg_access_range(struct amdgpu_device * adev,u32 offset)1374 static bool gfx_v9_4_3_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
1375 {
1376 return gfx_v9_4_3_check_rlcg_range(adev, offset,
1377 (void *)rlcg_access_gc_9_4_3,
1378 ARRAY_SIZE(rlcg_access_gc_9_4_3));
1379 }
1380
gfx_v9_4_3_xcc_cp_compute_enable(struct amdgpu_device * adev,bool enable,int xcc_id)1381 static void gfx_v9_4_3_xcc_cp_compute_enable(struct amdgpu_device *adev,
1382 bool enable, int xcc_id)
1383 {
1384 if (enable) {
1385 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 0);
1386 } else {
1387 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL,
1388 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
1389 adev->gfx.kiq[xcc_id].ring.sched.ready = false;
1390 }
1391 udelay(50);
1392 }
1393
gfx_v9_4_3_xcc_cp_compute_load_microcode(struct amdgpu_device * adev,int xcc_id)1394 static int gfx_v9_4_3_xcc_cp_compute_load_microcode(struct amdgpu_device *adev,
1395 int xcc_id)
1396 {
1397 const struct gfx_firmware_header_v1_0 *mec_hdr;
1398 const __le32 *fw_data;
1399 unsigned i;
1400 u32 tmp;
1401 u32 mec_ucode_addr_offset;
1402 u32 mec_ucode_data_offset;
1403
1404 if (!adev->gfx.mec_fw)
1405 return -EINVAL;
1406
1407 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id);
1408
1409 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1410 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
1411
1412 fw_data = (const __le32 *)
1413 (adev->gfx.mec_fw->data +
1414 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
1415 tmp = 0;
1416 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
1417 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
1418 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL, tmp);
1419
1420 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_LO,
1421 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000);
1422 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_HI,
1423 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
1424
1425 mec_ucode_addr_offset =
1426 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_ADDR);
1427 mec_ucode_data_offset =
1428 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_DATA);
1429
1430 /* MEC1 */
1431 WREG32(mec_ucode_addr_offset, mec_hdr->jt_offset);
1432 for (i = 0; i < mec_hdr->jt_size; i++)
1433 WREG32(mec_ucode_data_offset,
1434 le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
1435
1436 WREG32(mec_ucode_addr_offset, adev->gfx.mec_fw_version);
1437 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
1438
1439 return 0;
1440 }
1441
1442 /* KIQ functions */
gfx_v9_4_3_xcc_kiq_setting(struct amdgpu_ring * ring,int xcc_id)1443 static void gfx_v9_4_3_xcc_kiq_setting(struct amdgpu_ring *ring, int xcc_id)
1444 {
1445 uint32_t tmp;
1446 struct amdgpu_device *adev = ring->adev;
1447
1448 /* tell RLC which is KIQ queue */
1449 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS);
1450 tmp &= 0xffffff00;
1451 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
1452 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp);
1453 tmp |= 0x80;
1454 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp);
1455 }
1456
gfx_v9_4_3_mqd_set_priority(struct amdgpu_ring * ring,struct v9_mqd * mqd)1457 static void gfx_v9_4_3_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *mqd)
1458 {
1459 struct amdgpu_device *adev = ring->adev;
1460
1461 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
1462 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) {
1463 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
1464 mqd->cp_hqd_queue_priority =
1465 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
1466 }
1467 }
1468 }
1469
gfx_v9_4_3_xcc_mqd_init(struct amdgpu_ring * ring,int xcc_id)1470 static int gfx_v9_4_3_xcc_mqd_init(struct amdgpu_ring *ring, int xcc_id)
1471 {
1472 struct amdgpu_device *adev = ring->adev;
1473 struct v9_mqd *mqd = ring->mqd_ptr;
1474 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
1475 uint32_t tmp;
1476
1477 mqd->header = 0xC0310800;
1478 mqd->compute_pipelinestat_enable = 0x00000001;
1479 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
1480 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
1481 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
1482 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
1483 mqd->compute_misc_reserved = 0x00000003;
1484
1485 mqd->dynamic_cu_mask_addr_lo =
1486 lower_32_bits(ring->mqd_gpu_addr
1487 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask));
1488 mqd->dynamic_cu_mask_addr_hi =
1489 upper_32_bits(ring->mqd_gpu_addr
1490 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask));
1491
1492 eop_base_addr = ring->eop_gpu_addr >> 8;
1493 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
1494 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
1495
1496 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
1497 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL);
1498 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
1499 (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1));
1500
1501 mqd->cp_hqd_eop_control = tmp;
1502
1503 /* enable doorbell? */
1504 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL);
1505
1506 if (ring->use_doorbell) {
1507 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1508 DOORBELL_OFFSET, ring->doorbell_index);
1509 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1510 DOORBELL_EN, 1);
1511 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1512 DOORBELL_SOURCE, 0);
1513 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1514 DOORBELL_HIT, 0);
1515 } else {
1516 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1517 DOORBELL_EN, 0);
1518 }
1519
1520 mqd->cp_hqd_pq_doorbell_control = tmp;
1521
1522 /* disable the queue if it's active */
1523 ring->wptr = 0;
1524 mqd->cp_hqd_dequeue_request = 0;
1525 mqd->cp_hqd_pq_rptr = 0;
1526 mqd->cp_hqd_pq_wptr_lo = 0;
1527 mqd->cp_hqd_pq_wptr_hi = 0;
1528
1529 /* set the pointer to the MQD */
1530 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
1531 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
1532
1533 /* set MQD vmid to 0 */
1534 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL);
1535 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
1536 mqd->cp_mqd_control = tmp;
1537
1538 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
1539 hqd_gpu_addr = ring->gpu_addr >> 8;
1540 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
1541 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
1542
1543 /* set up the HQD, this is similar to CP_RB0_CNTL */
1544 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL);
1545 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
1546 (order_base_2(ring->ring_size / 4) - 1));
1547 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
1548 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
1549 #ifdef __BIG_ENDIAN
1550 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
1551 #endif
1552 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
1553 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
1554 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
1555 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
1556 mqd->cp_hqd_pq_control = tmp;
1557
1558 /* set the wb address whether it's enabled or not */
1559 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
1560 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
1561 mqd->cp_hqd_pq_rptr_report_addr_hi =
1562 upper_32_bits(wb_gpu_addr) & 0xffff;
1563
1564 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
1565 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
1566 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
1567 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
1568
1569 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
1570 ring->wptr = 0;
1571 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR);
1572
1573 /* set the vmid for the queue */
1574 mqd->cp_hqd_vmid = 0;
1575
1576 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE);
1577 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
1578 mqd->cp_hqd_persistent_state = tmp;
1579
1580 /* set MIN_IB_AVAIL_SIZE */
1581 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL);
1582 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
1583 mqd->cp_hqd_ib_control = tmp;
1584
1585 /* set static priority for a queue/ring */
1586 gfx_v9_4_3_mqd_set_priority(ring, mqd);
1587 mqd->cp_hqd_quantum = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_QUANTUM);
1588
1589 /* map_queues packet doesn't need activate the queue,
1590 * so only kiq need set this field.
1591 */
1592 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
1593 mqd->cp_hqd_active = 1;
1594
1595 return 0;
1596 }
1597
gfx_v9_4_3_xcc_kiq_init_register(struct amdgpu_ring * ring,int xcc_id)1598 static int gfx_v9_4_3_xcc_kiq_init_register(struct amdgpu_ring *ring,
1599 int xcc_id)
1600 {
1601 struct amdgpu_device *adev = ring->adev;
1602 struct v9_mqd *mqd = ring->mqd_ptr;
1603 int j;
1604
1605 /* disable wptr polling */
1606 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0);
1607
1608 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR,
1609 mqd->cp_hqd_eop_base_addr_lo);
1610 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR_HI,
1611 mqd->cp_hqd_eop_base_addr_hi);
1612
1613 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
1614 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL,
1615 mqd->cp_hqd_eop_control);
1616
1617 /* enable doorbell? */
1618 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL,
1619 mqd->cp_hqd_pq_doorbell_control);
1620
1621 /* disable the queue if it's active */
1622 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) {
1623 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1);
1624 for (j = 0; j < adev->usec_timeout; j++) {
1625 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1))
1626 break;
1627 udelay(1);
1628 }
1629 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST,
1630 mqd->cp_hqd_dequeue_request);
1631 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR,
1632 mqd->cp_hqd_pq_rptr);
1633 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO,
1634 mqd->cp_hqd_pq_wptr_lo);
1635 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI,
1636 mqd->cp_hqd_pq_wptr_hi);
1637 }
1638
1639 /* set the pointer to the MQD */
1640 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR,
1641 mqd->cp_mqd_base_addr_lo);
1642 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR_HI,
1643 mqd->cp_mqd_base_addr_hi);
1644
1645 /* set MQD vmid to 0 */
1646 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL,
1647 mqd->cp_mqd_control);
1648
1649 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
1650 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE,
1651 mqd->cp_hqd_pq_base_lo);
1652 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE_HI,
1653 mqd->cp_hqd_pq_base_hi);
1654
1655 /* set up the HQD, this is similar to CP_RB0_CNTL */
1656 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL,
1657 mqd->cp_hqd_pq_control);
1658
1659 /* set the wb address whether it's enabled or not */
1660 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR,
1661 mqd->cp_hqd_pq_rptr_report_addr_lo);
1662 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
1663 mqd->cp_hqd_pq_rptr_report_addr_hi);
1664
1665 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
1666 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR,
1667 mqd->cp_hqd_pq_wptr_poll_addr_lo);
1668 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR_HI,
1669 mqd->cp_hqd_pq_wptr_poll_addr_hi);
1670
1671 /* enable the doorbell if requested */
1672 if (ring->use_doorbell) {
1673 WREG32_SOC15(
1674 GC, GET_INST(GC, xcc_id),
1675 regCP_MEC_DOORBELL_RANGE_LOWER,
1676 ((adev->doorbell_index.kiq +
1677 xcc_id * adev->doorbell_index.xcc_doorbell_range) *
1678 2) << 2);
1679 WREG32_SOC15(
1680 GC, GET_INST(GC, xcc_id),
1681 regCP_MEC_DOORBELL_RANGE_UPPER,
1682 ((adev->doorbell_index.userqueue_end +
1683 xcc_id * adev->doorbell_index.xcc_doorbell_range) *
1684 2) << 2);
1685 }
1686
1687 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL,
1688 mqd->cp_hqd_pq_doorbell_control);
1689
1690 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
1691 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO,
1692 mqd->cp_hqd_pq_wptr_lo);
1693 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI,
1694 mqd->cp_hqd_pq_wptr_hi);
1695
1696 /* set the vmid for the queue */
1697 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID, mqd->cp_hqd_vmid);
1698
1699 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE,
1700 mqd->cp_hqd_persistent_state);
1701
1702 /* activate the queue */
1703 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE,
1704 mqd->cp_hqd_active);
1705
1706 if (ring->use_doorbell)
1707 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_STATUS, DOORBELL_ENABLE, 1);
1708
1709 return 0;
1710 }
1711
gfx_v9_4_3_xcc_q_fini_register(struct amdgpu_ring * ring,int xcc_id)1712 static int gfx_v9_4_3_xcc_q_fini_register(struct amdgpu_ring *ring,
1713 int xcc_id)
1714 {
1715 struct amdgpu_device *adev = ring->adev;
1716 int j;
1717
1718 /* disable the queue if it's active */
1719 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) {
1720
1721 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1);
1722
1723 for (j = 0; j < adev->usec_timeout; j++) {
1724 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1))
1725 break;
1726 udelay(1);
1727 }
1728
1729 if (j == AMDGPU_MAX_USEC_TIMEOUT) {
1730 DRM_DEBUG("%s dequeue request failed.\n", ring->name);
1731
1732 /* Manual disable if dequeue request times out */
1733 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 0);
1734 }
1735
1736 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST,
1737 0);
1738 }
1739
1740 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IQ_TIMER, 0);
1741 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL, 0);
1742 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, CP_HQD_PERSISTENT_STATE_DEFAULT);
1743 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000);
1744 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0);
1745 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 0);
1746 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 0);
1747 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 0);
1748
1749 return 0;
1750 }
1751
gfx_v9_4_3_xcc_kiq_init_queue(struct amdgpu_ring * ring,int xcc_id)1752 static int gfx_v9_4_3_xcc_kiq_init_queue(struct amdgpu_ring *ring, int xcc_id)
1753 {
1754 struct amdgpu_device *adev = ring->adev;
1755 struct v9_mqd *mqd = ring->mqd_ptr;
1756 struct v9_mqd *tmp_mqd;
1757
1758 gfx_v9_4_3_xcc_kiq_setting(ring, xcc_id);
1759
1760 /* GPU could be in bad state during probe, driver trigger the reset
1761 * after load the SMU, in this case , the mqd is not be initialized.
1762 * driver need to re-init the mqd.
1763 * check mqd->cp_hqd_pq_control since this value should not be 0
1764 */
1765 tmp_mqd = (struct v9_mqd *)adev->gfx.kiq[xcc_id].mqd_backup;
1766 if (amdgpu_in_reset(adev) && tmp_mqd->cp_hqd_pq_control) {
1767 /* for GPU_RESET case , reset MQD to a clean status */
1768 if (adev->gfx.kiq[xcc_id].mqd_backup)
1769 memcpy(mqd, adev->gfx.kiq[xcc_id].mqd_backup, sizeof(struct v9_mqd_allocation));
1770
1771 /* reset ring buffer */
1772 ring->wptr = 0;
1773 amdgpu_ring_clear_ring(ring);
1774 mutex_lock(&adev->srbm_mutex);
1775 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id));
1776 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id);
1777 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));
1778 mutex_unlock(&adev->srbm_mutex);
1779 } else {
1780 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
1781 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
1782 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
1783 mutex_lock(&adev->srbm_mutex);
1784 if (amdgpu_sriov_vf(adev) && adev->in_suspend)
1785 amdgpu_ring_clear_ring(ring);
1786 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id));
1787 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id);
1788 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id);
1789 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));
1790 mutex_unlock(&adev->srbm_mutex);
1791
1792 if (adev->gfx.kiq[xcc_id].mqd_backup)
1793 memcpy(adev->gfx.kiq[xcc_id].mqd_backup, mqd, sizeof(struct v9_mqd_allocation));
1794 }
1795
1796 return 0;
1797 }
1798
gfx_v9_4_3_xcc_kcq_init_queue(struct amdgpu_ring * ring,int xcc_id)1799 static int gfx_v9_4_3_xcc_kcq_init_queue(struct amdgpu_ring *ring, int xcc_id)
1800 {
1801 struct amdgpu_device *adev = ring->adev;
1802 struct v9_mqd *mqd = ring->mqd_ptr;
1803 int mqd_idx = ring - &adev->gfx.compute_ring[0];
1804 struct v9_mqd *tmp_mqd;
1805
1806 /* Same as above kiq init, driver need to re-init the mqd if mqd->cp_hqd_pq_control
1807 * is not be initialized before
1808 */
1809 tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx];
1810
1811 if (!tmp_mqd->cp_hqd_pq_control ||
1812 (!amdgpu_in_reset(adev) && !adev->in_suspend)) {
1813 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
1814 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
1815 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
1816 mutex_lock(&adev->srbm_mutex);
1817 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id));
1818 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id);
1819 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));
1820 mutex_unlock(&adev->srbm_mutex);
1821
1822 if (adev->gfx.mec.mqd_backup[mqd_idx])
1823 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation));
1824 } else {
1825 /* restore MQD to a clean status */
1826 if (adev->gfx.mec.mqd_backup[mqd_idx])
1827 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation));
1828 /* reset ring buffer */
1829 ring->wptr = 0;
1830 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0);
1831 amdgpu_ring_clear_ring(ring);
1832 }
1833
1834 return 0;
1835 }
1836
gfx_v9_4_3_xcc_kcq_fini_register(struct amdgpu_device * adev,int xcc_id)1837 static int gfx_v9_4_3_xcc_kcq_fini_register(struct amdgpu_device *adev, int xcc_id)
1838 {
1839 struct amdgpu_ring *ring;
1840 int j;
1841
1842 for (j = 0; j < adev->gfx.num_compute_rings; j++) {
1843 ring = &adev->gfx.compute_ring[j + xcc_id * adev->gfx.num_compute_rings];
1844 if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
1845 mutex_lock(&adev->srbm_mutex);
1846 soc15_grbm_select(adev, ring->me,
1847 ring->pipe,
1848 ring->queue, 0, GET_INST(GC, xcc_id));
1849 gfx_v9_4_3_xcc_q_fini_register(ring, xcc_id);
1850 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));
1851 mutex_unlock(&adev->srbm_mutex);
1852 }
1853 }
1854
1855 return 0;
1856 }
1857
gfx_v9_4_3_xcc_kiq_resume(struct amdgpu_device * adev,int xcc_id)1858 static int gfx_v9_4_3_xcc_kiq_resume(struct amdgpu_device *adev, int xcc_id)
1859 {
1860 struct amdgpu_ring *ring;
1861 int r;
1862
1863 ring = &adev->gfx.kiq[xcc_id].ring;
1864
1865 r = amdgpu_bo_reserve(ring->mqd_obj, false);
1866 if (unlikely(r != 0))
1867 return r;
1868
1869 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
1870 if (unlikely(r != 0)) {
1871 amdgpu_bo_unreserve(ring->mqd_obj);
1872 return r;
1873 }
1874
1875 gfx_v9_4_3_xcc_kiq_init_queue(ring, xcc_id);
1876 amdgpu_bo_kunmap(ring->mqd_obj);
1877 ring->mqd_ptr = NULL;
1878 amdgpu_bo_unreserve(ring->mqd_obj);
1879 return 0;
1880 }
1881
gfx_v9_4_3_xcc_kcq_resume(struct amdgpu_device * adev,int xcc_id)1882 static int gfx_v9_4_3_xcc_kcq_resume(struct amdgpu_device *adev, int xcc_id)
1883 {
1884 struct amdgpu_ring *ring = NULL;
1885 int r = 0, i;
1886
1887 gfx_v9_4_3_xcc_cp_compute_enable(adev, true, xcc_id);
1888
1889 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
1890 ring = &adev->gfx.compute_ring[i + xcc_id * adev->gfx.num_compute_rings];
1891
1892 r = amdgpu_bo_reserve(ring->mqd_obj, false);
1893 if (unlikely(r != 0))
1894 goto done;
1895 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
1896 if (!r) {
1897 r = gfx_v9_4_3_xcc_kcq_init_queue(ring, xcc_id);
1898 amdgpu_bo_kunmap(ring->mqd_obj);
1899 ring->mqd_ptr = NULL;
1900 }
1901 amdgpu_bo_unreserve(ring->mqd_obj);
1902 if (r)
1903 goto done;
1904 }
1905
1906 r = amdgpu_gfx_enable_kcq(adev, xcc_id);
1907 done:
1908 return r;
1909 }
1910
gfx_v9_4_3_xcc_cp_resume(struct amdgpu_device * adev,int xcc_id)1911 static int gfx_v9_4_3_xcc_cp_resume(struct amdgpu_device *adev, int xcc_id)
1912 {
1913 struct amdgpu_ring *ring;
1914 int r, j;
1915
1916 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id);
1917
1918 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1919 gfx_v9_4_3_xcc_disable_gpa_mode(adev, xcc_id);
1920
1921 r = gfx_v9_4_3_xcc_cp_compute_load_microcode(adev, xcc_id);
1922 if (r)
1923 return r;
1924 }
1925
1926 r = gfx_v9_4_3_xcc_kiq_resume(adev, xcc_id);
1927 if (r)
1928 return r;
1929
1930 r = gfx_v9_4_3_xcc_kcq_resume(adev, xcc_id);
1931 if (r)
1932 return r;
1933
1934 for (j = 0; j < adev->gfx.num_compute_rings; j++) {
1935 ring = &adev->gfx.compute_ring
1936 [j + xcc_id * adev->gfx.num_compute_rings];
1937 r = amdgpu_ring_test_helper(ring);
1938 if (r)
1939 return r;
1940 }
1941
1942 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id);
1943
1944 return 0;
1945 }
1946
gfx_v9_4_3_cp_resume(struct amdgpu_device * adev)1947 static int gfx_v9_4_3_cp_resume(struct amdgpu_device *adev)
1948 {
1949 int r = 0, i, num_xcc;
1950
1951 if (amdgpu_xcp_query_partition_mode(adev->xcp_mgr,
1952 AMDGPU_XCP_FL_NONE) ==
1953 AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE)
1954 r = amdgpu_xcp_switch_partition_mode(adev->xcp_mgr,
1955 amdgpu_user_partt_mode);
1956
1957 if (r)
1958 return r;
1959
1960 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1961 for (i = 0; i < num_xcc; i++) {
1962 r = gfx_v9_4_3_xcc_cp_resume(adev, i);
1963 if (r)
1964 return r;
1965 }
1966
1967 return 0;
1968 }
1969
gfx_v9_4_3_xcc_cp_enable(struct amdgpu_device * adev,bool enable,int xcc_id)1970 static void gfx_v9_4_3_xcc_cp_enable(struct amdgpu_device *adev, bool enable,
1971 int xcc_id)
1972 {
1973 gfx_v9_4_3_xcc_cp_compute_enable(adev, enable, xcc_id);
1974 }
1975
gfx_v9_4_3_xcc_fini(struct amdgpu_device * adev,int xcc_id)1976 static void gfx_v9_4_3_xcc_fini(struct amdgpu_device *adev, int xcc_id)
1977 {
1978 if (amdgpu_gfx_disable_kcq(adev, xcc_id))
1979 DRM_ERROR("XCD %d KCQ disable failed\n", xcc_id);
1980
1981 if (amdgpu_sriov_vf(adev)) {
1982 /* must disable polling for SRIOV when hw finished, otherwise
1983 * CPC engine may still keep fetching WB address which is already
1984 * invalid after sw finished and trigger DMAR reading error in
1985 * hypervisor side.
1986 */
1987 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0);
1988 return;
1989 }
1990
1991 /* Use deinitialize sequence from CAIL when unbinding device
1992 * from driver, otherwise KIQ is hanging when binding back
1993 */
1994 if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
1995 mutex_lock(&adev->srbm_mutex);
1996 soc15_grbm_select(adev, adev->gfx.kiq[xcc_id].ring.me,
1997 adev->gfx.kiq[xcc_id].ring.pipe,
1998 adev->gfx.kiq[xcc_id].ring.queue, 0,
1999 GET_INST(GC, xcc_id));
2000 gfx_v9_4_3_xcc_q_fini_register(&adev->gfx.kiq[xcc_id].ring,
2001 xcc_id);
2002 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));
2003 mutex_unlock(&adev->srbm_mutex);
2004 }
2005
2006 gfx_v9_4_3_xcc_kcq_fini_register(adev, xcc_id);
2007 gfx_v9_4_3_xcc_cp_enable(adev, false, xcc_id);
2008 }
2009
gfx_v9_4_3_hw_init(void * handle)2010 static int gfx_v9_4_3_hw_init(void *handle)
2011 {
2012 int r;
2013 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2014
2015 if (!amdgpu_sriov_vf(adev))
2016 gfx_v9_4_3_init_golden_registers(adev);
2017
2018 gfx_v9_4_3_constants_init(adev);
2019
2020 r = adev->gfx.rlc.funcs->resume(adev);
2021 if (r)
2022 return r;
2023
2024 r = gfx_v9_4_3_cp_resume(adev);
2025 if (r)
2026 return r;
2027
2028 return r;
2029 }
2030
gfx_v9_4_3_hw_fini(void * handle)2031 static int gfx_v9_4_3_hw_fini(void *handle)
2032 {
2033 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2034 int i, num_xcc;
2035
2036 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
2037 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
2038
2039 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
2040 for (i = 0; i < num_xcc; i++) {
2041 gfx_v9_4_3_xcc_fini(adev, i);
2042 }
2043
2044 return 0;
2045 }
2046
gfx_v9_4_3_suspend(void * handle)2047 static int gfx_v9_4_3_suspend(void *handle)
2048 {
2049 return gfx_v9_4_3_hw_fini(handle);
2050 }
2051
gfx_v9_4_3_resume(void * handle)2052 static int gfx_v9_4_3_resume(void *handle)
2053 {
2054 return gfx_v9_4_3_hw_init(handle);
2055 }
2056
gfx_v9_4_3_is_idle(void * handle)2057 static bool gfx_v9_4_3_is_idle(void *handle)
2058 {
2059 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2060 int i, num_xcc;
2061
2062 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
2063 for (i = 0; i < num_xcc; i++) {
2064 if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i), regGRBM_STATUS),
2065 GRBM_STATUS, GUI_ACTIVE))
2066 return false;
2067 }
2068 return true;
2069 }
2070
gfx_v9_4_3_wait_for_idle(void * handle)2071 static int gfx_v9_4_3_wait_for_idle(void *handle)
2072 {
2073 unsigned i;
2074 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2075
2076 for (i = 0; i < adev->usec_timeout; i++) {
2077 if (gfx_v9_4_3_is_idle(handle))
2078 return 0;
2079 udelay(1);
2080 }
2081 return -ETIMEDOUT;
2082 }
2083
gfx_v9_4_3_soft_reset(void * handle)2084 static int gfx_v9_4_3_soft_reset(void *handle)
2085 {
2086 u32 grbm_soft_reset = 0;
2087 u32 tmp;
2088 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2089
2090 /* GRBM_STATUS */
2091 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS);
2092 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
2093 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
2094 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
2095 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
2096 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
2097 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
2098 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
2099 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
2100 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
2101 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
2102 }
2103
2104 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
2105 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
2106 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
2107 }
2108
2109 /* GRBM_STATUS2 */
2110 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS2);
2111 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
2112 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
2113 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2114
2115
2116 if (grbm_soft_reset) {
2117 /* stop the rlc */
2118 adev->gfx.rlc.funcs->stop(adev);
2119
2120 /* Disable MEC parsing/prefetching */
2121 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, 0);
2122
2123 if (grbm_soft_reset) {
2124 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET);
2125 tmp |= grbm_soft_reset;
2126 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
2127 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp);
2128 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET);
2129
2130 udelay(50);
2131
2132 tmp &= ~grbm_soft_reset;
2133 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp);
2134 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET);
2135 }
2136
2137 /* Wait a little for things to settle down */
2138 udelay(50);
2139 }
2140 return 0;
2141 }
2142
gfx_v9_4_3_ring_emit_gds_switch(struct amdgpu_ring * ring,uint32_t vmid,uint32_t gds_base,uint32_t gds_size,uint32_t gws_base,uint32_t gws_size,uint32_t oa_base,uint32_t oa_size)2143 static void gfx_v9_4_3_ring_emit_gds_switch(struct amdgpu_ring *ring,
2144 uint32_t vmid,
2145 uint32_t gds_base, uint32_t gds_size,
2146 uint32_t gws_base, uint32_t gws_size,
2147 uint32_t oa_base, uint32_t oa_size)
2148 {
2149 struct amdgpu_device *adev = ring->adev;
2150
2151 /* GDS Base */
2152 gfx_v9_4_3_write_data_to_reg(ring, 0, false,
2153 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_BASE) + 2 * vmid,
2154 gds_base);
2155
2156 /* GDS Size */
2157 gfx_v9_4_3_write_data_to_reg(ring, 0, false,
2158 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_SIZE) + 2 * vmid,
2159 gds_size);
2160
2161 /* GWS */
2162 gfx_v9_4_3_write_data_to_reg(ring, 0, false,
2163 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_GWS_VMID0) + vmid,
2164 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
2165
2166 /* OA */
2167 gfx_v9_4_3_write_data_to_reg(ring, 0, false,
2168 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_OA_VMID0) + vmid,
2169 (1 << (oa_size + oa_base)) - (1 << oa_base));
2170 }
2171
gfx_v9_4_3_early_init(void * handle)2172 static int gfx_v9_4_3_early_init(void *handle)
2173 {
2174 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2175
2176 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
2177 AMDGPU_MAX_COMPUTE_RINGS);
2178 gfx_v9_4_3_set_kiq_pm4_funcs(adev);
2179 gfx_v9_4_3_set_ring_funcs(adev);
2180 gfx_v9_4_3_set_irq_funcs(adev);
2181 gfx_v9_4_3_set_gds_init(adev);
2182 gfx_v9_4_3_set_rlc_funcs(adev);
2183
2184 /* init rlcg reg access ctrl */
2185 gfx_v9_4_3_init_rlcg_reg_access_ctrl(adev);
2186
2187 return gfx_v9_4_3_init_microcode(adev);
2188 }
2189
gfx_v9_4_3_late_init(void * handle)2190 static int gfx_v9_4_3_late_init(void *handle)
2191 {
2192 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2193 int r;
2194
2195 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
2196 if (r)
2197 return r;
2198
2199 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
2200 if (r)
2201 return r;
2202
2203 if (adev->gfx.ras &&
2204 adev->gfx.ras->enable_watchdog_timer)
2205 adev->gfx.ras->enable_watchdog_timer(adev);
2206
2207 return 0;
2208 }
2209
gfx_v9_4_3_xcc_update_sram_fgcg(struct amdgpu_device * adev,bool enable,int xcc_id)2210 static void gfx_v9_4_3_xcc_update_sram_fgcg(struct amdgpu_device *adev,
2211 bool enable, int xcc_id)
2212 {
2213 uint32_t def, data;
2214
2215 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG))
2216 return;
2217
2218 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id),
2219 regRLC_CGTT_MGCG_OVERRIDE);
2220
2221 if (enable)
2222 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
2223 else
2224 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
2225
2226 if (def != data)
2227 WREG32_SOC15(GC, GET_INST(GC, xcc_id),
2228 regRLC_CGTT_MGCG_OVERRIDE, data);
2229
2230 }
2231
gfx_v9_4_3_xcc_update_repeater_fgcg(struct amdgpu_device * adev,bool enable,int xcc_id)2232 static void gfx_v9_4_3_xcc_update_repeater_fgcg(struct amdgpu_device *adev,
2233 bool enable, int xcc_id)
2234 {
2235 uint32_t def, data;
2236
2237 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG))
2238 return;
2239
2240 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id),
2241 regRLC_CGTT_MGCG_OVERRIDE);
2242
2243 if (enable)
2244 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK;
2245 else
2246 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK;
2247
2248 if (def != data)
2249 WREG32_SOC15(GC, GET_INST(GC, xcc_id),
2250 regRLC_CGTT_MGCG_OVERRIDE, data);
2251 }
2252
2253 static void
gfx_v9_4_3_xcc_update_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable,int xcc_id)2254 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(struct amdgpu_device *adev,
2255 bool enable, int xcc_id)
2256 {
2257 uint32_t data, def;
2258
2259 /* It is disabled by HW by default */
2260 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
2261 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
2262 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE);
2263
2264 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
2265 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
2266 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
2267 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
2268
2269 if (def != data)
2270 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data);
2271
2272 /* MGLS is a global flag to control all MGLS in GFX */
2273 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
2274 /* 2 - RLC memory Light sleep */
2275 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
2276 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL);
2277 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
2278 if (def != data)
2279 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data);
2280 }
2281 /* 3 - CP memory Light sleep */
2282 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
2283 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL);
2284 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2285 if (def != data)
2286 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data);
2287 }
2288 }
2289 } else {
2290 /* 1 - MGCG_OVERRIDE */
2291 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE);
2292
2293 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
2294 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
2295 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
2296 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
2297
2298 if (def != data)
2299 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data);
2300
2301 /* 2 - disable MGLS in RLC */
2302 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL);
2303 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
2304 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
2305 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data);
2306 }
2307
2308 /* 3 - disable MGLS in CP */
2309 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL);
2310 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
2311 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2312 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data);
2313 }
2314 }
2315
2316 }
2317
2318 static void
gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(struct amdgpu_device * adev,bool enable,int xcc_id)2319 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
2320 bool enable, int xcc_id)
2321 {
2322 uint32_t def, data;
2323
2324 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
2325
2326 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE);
2327 /* unset CGCG override */
2328 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
2329 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
2330 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
2331 else
2332 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
2333 /* update CGCG and CGLS override bits */
2334 if (def != data)
2335 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data);
2336
2337 /* enable cgcg FSM(0x0000363F) */
2338 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL);
2339
2340 data = (0x36
2341 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
2342 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
2343 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
2344 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
2345 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
2346 if (def != data)
2347 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data);
2348
2349 /* set IDLE_POLL_COUNT(0x00900100) */
2350 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL);
2351 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
2352 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
2353 if (def != data)
2354 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL, data);
2355 } else {
2356 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL);
2357 /* reset CGCG/CGLS bits */
2358 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
2359 /* disable cgcg and cgls in FSM */
2360 if (def != data)
2361 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data);
2362 }
2363
2364 }
2365
gfx_v9_4_3_xcc_update_gfx_clock_gating(struct amdgpu_device * adev,bool enable,int xcc_id)2366 static int gfx_v9_4_3_xcc_update_gfx_clock_gating(struct amdgpu_device *adev,
2367 bool enable, int xcc_id)
2368 {
2369 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id);
2370
2371 if (enable) {
2372 /* FGCG */
2373 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id);
2374 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id);
2375
2376 /* CGCG/CGLS should be enabled after MGCG/MGLS
2377 * === MGCG + MGLS ===
2378 */
2379 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable,
2380 xcc_id);
2381 /* === CGCG + CGLS === */
2382 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable,
2383 xcc_id);
2384 } else {
2385 /* CGCG/CGLS should be disabled before MGCG/MGLS
2386 * === CGCG + CGLS ===
2387 */
2388 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable,
2389 xcc_id);
2390 /* === MGCG + MGLS === */
2391 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable,
2392 xcc_id);
2393
2394 /* FGCG */
2395 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id);
2396 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id);
2397 }
2398
2399 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id);
2400
2401 return 0;
2402 }
2403
2404 static const struct amdgpu_rlc_funcs gfx_v9_4_3_rlc_funcs = {
2405 .is_rlc_enabled = gfx_v9_4_3_is_rlc_enabled,
2406 .set_safe_mode = gfx_v9_4_3_xcc_set_safe_mode,
2407 .unset_safe_mode = gfx_v9_4_3_xcc_unset_safe_mode,
2408 .init = gfx_v9_4_3_rlc_init,
2409 .resume = gfx_v9_4_3_rlc_resume,
2410 .stop = gfx_v9_4_3_rlc_stop,
2411 .reset = gfx_v9_4_3_rlc_reset,
2412 .start = gfx_v9_4_3_rlc_start,
2413 .update_spm_vmid = gfx_v9_4_3_update_spm_vmid,
2414 .is_rlcg_access_range = gfx_v9_4_3_is_rlcg_access_range,
2415 };
2416
gfx_v9_4_3_set_powergating_state(void * handle,enum amd_powergating_state state)2417 static int gfx_v9_4_3_set_powergating_state(void *handle,
2418 enum amd_powergating_state state)
2419 {
2420 return 0;
2421 }
2422
gfx_v9_4_3_set_clockgating_state(void * handle,enum amd_clockgating_state state)2423 static int gfx_v9_4_3_set_clockgating_state(void *handle,
2424 enum amd_clockgating_state state)
2425 {
2426 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2427 int i, num_xcc;
2428
2429 if (amdgpu_sriov_vf(adev))
2430 return 0;
2431
2432 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
2433 switch (adev->ip_versions[GC_HWIP][0]) {
2434 case IP_VERSION(9, 4, 3):
2435 for (i = 0; i < num_xcc; i++)
2436 gfx_v9_4_3_xcc_update_gfx_clock_gating(
2437 adev, state == AMD_CG_STATE_GATE, i);
2438 break;
2439 default:
2440 break;
2441 }
2442 return 0;
2443 }
2444
gfx_v9_4_3_get_clockgating_state(void * handle,u64 * flags)2445 static void gfx_v9_4_3_get_clockgating_state(void *handle, u64 *flags)
2446 {
2447 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2448 int data;
2449
2450 if (amdgpu_sriov_vf(adev))
2451 *flags = 0;
2452
2453 /* AMD_CG_SUPPORT_GFX_MGCG */
2454 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGTT_MGCG_OVERRIDE));
2455 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
2456 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
2457
2458 /* AMD_CG_SUPPORT_GFX_CGCG */
2459 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGCG_CGLS_CTRL));
2460 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
2461 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
2462
2463 /* AMD_CG_SUPPORT_GFX_CGLS */
2464 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
2465 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
2466
2467 /* AMD_CG_SUPPORT_GFX_RLC_LS */
2468 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_MEM_SLP_CNTL));
2469 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
2470 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
2471
2472 /* AMD_CG_SUPPORT_GFX_CP_LS */
2473 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCP_MEM_SLP_CNTL));
2474 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
2475 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
2476 }
2477
gfx_v9_4_3_ring_emit_hdp_flush(struct amdgpu_ring * ring)2478 static void gfx_v9_4_3_ring_emit_hdp_flush(struct amdgpu_ring *ring)
2479 {
2480 struct amdgpu_device *adev = ring->adev;
2481 u32 ref_and_mask, reg_mem_engine;
2482 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
2483
2484 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
2485 switch (ring->me) {
2486 case 1:
2487 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
2488 break;
2489 case 2:
2490 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
2491 break;
2492 default:
2493 return;
2494 }
2495 reg_mem_engine = 0;
2496 } else {
2497 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
2498 reg_mem_engine = 1; /* pfp */
2499 }
2500
2501 gfx_v9_4_3_wait_reg_mem(ring, reg_mem_engine, 0, 1,
2502 adev->nbio.funcs->get_hdp_flush_req_offset(adev),
2503 adev->nbio.funcs->get_hdp_flush_done_offset(adev),
2504 ref_and_mask, ref_and_mask, 0x20);
2505 }
2506
gfx_v9_4_3_ring_emit_ib_compute(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)2507 static void gfx_v9_4_3_ring_emit_ib_compute(struct amdgpu_ring *ring,
2508 struct amdgpu_job *job,
2509 struct amdgpu_ib *ib,
2510 uint32_t flags)
2511 {
2512 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
2513 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
2514
2515 /* Currently, there is a high possibility to get wave ID mismatch
2516 * between ME and GDS, leading to a hw deadlock, because ME generates
2517 * different wave IDs than the GDS expects. This situation happens
2518 * randomly when at least 5 compute pipes use GDS ordered append.
2519 * The wave IDs generated by ME are also wrong after suspend/resume.
2520 * Those are probably bugs somewhere else in the kernel driver.
2521 *
2522 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
2523 * GDS to 0 for this ring (me/pipe).
2524 */
2525 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
2526 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2527 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID);
2528 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
2529 }
2530
2531 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2532 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
2533 amdgpu_ring_write(ring,
2534 #ifdef __BIG_ENDIAN
2535 (2 << 0) |
2536 #endif
2537 lower_32_bits(ib->gpu_addr));
2538 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
2539 amdgpu_ring_write(ring, control);
2540 }
2541
gfx_v9_4_3_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)2542 static void gfx_v9_4_3_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
2543 u64 seq, unsigned flags)
2544 {
2545 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
2546 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
2547 bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY;
2548
2549 /* RELEASE_MEM - flush caches, send int */
2550 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
2551 amdgpu_ring_write(ring, ((writeback ? (EOP_TC_WB_ACTION_EN |
2552 EOP_TC_NC_ACTION_EN) :
2553 (EOP_TCL1_ACTION_EN |
2554 EOP_TC_ACTION_EN |
2555 EOP_TC_WB_ACTION_EN |
2556 EOP_TC_MD_ACTION_EN)) |
2557 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2558 EVENT_INDEX(5)));
2559 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
2560
2561 /*
2562 * the address should be Qword aligned if 64bit write, Dword
2563 * aligned if only send 32bit data low (discard data high)
2564 */
2565 if (write64bit)
2566 BUG_ON(addr & 0x7);
2567 else
2568 BUG_ON(addr & 0x3);
2569 amdgpu_ring_write(ring, lower_32_bits(addr));
2570 amdgpu_ring_write(ring, upper_32_bits(addr));
2571 amdgpu_ring_write(ring, lower_32_bits(seq));
2572 amdgpu_ring_write(ring, upper_32_bits(seq));
2573 amdgpu_ring_write(ring, 0);
2574 }
2575
gfx_v9_4_3_ring_emit_pipeline_sync(struct amdgpu_ring * ring)2576 static void gfx_v9_4_3_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
2577 {
2578 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2579 uint32_t seq = ring->fence_drv.sync_seq;
2580 uint64_t addr = ring->fence_drv.gpu_addr;
2581
2582 gfx_v9_4_3_wait_reg_mem(ring, usepfp, 1, 0,
2583 lower_32_bits(addr), upper_32_bits(addr),
2584 seq, 0xffffffff, 4);
2585 }
2586
gfx_v9_4_3_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned vmid,uint64_t pd_addr)2587 static void gfx_v9_4_3_ring_emit_vm_flush(struct amdgpu_ring *ring,
2588 unsigned vmid, uint64_t pd_addr)
2589 {
2590 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
2591 }
2592
gfx_v9_4_3_ring_get_rptr_compute(struct amdgpu_ring * ring)2593 static u64 gfx_v9_4_3_ring_get_rptr_compute(struct amdgpu_ring *ring)
2594 {
2595 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */
2596 }
2597
gfx_v9_4_3_ring_get_wptr_compute(struct amdgpu_ring * ring)2598 static u64 gfx_v9_4_3_ring_get_wptr_compute(struct amdgpu_ring *ring)
2599 {
2600 u64 wptr;
2601
2602 /* XXX check if swapping is necessary on BE */
2603 if (ring->use_doorbell)
2604 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
2605 else
2606 BUG();
2607 return wptr;
2608 }
2609
gfx_v9_4_3_ring_set_wptr_compute(struct amdgpu_ring * ring)2610 static void gfx_v9_4_3_ring_set_wptr_compute(struct amdgpu_ring *ring)
2611 {
2612 struct amdgpu_device *adev = ring->adev;
2613
2614 /* XXX check if swapping is necessary on BE */
2615 if (ring->use_doorbell) {
2616 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
2617 WDOORBELL64(ring->doorbell_index, ring->wptr);
2618 } else {
2619 BUG(); /* only DOORBELL method supported on gfx9 now */
2620 }
2621 }
2622
gfx_v9_4_3_ring_emit_fence_kiq(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned int flags)2623 static void gfx_v9_4_3_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
2624 u64 seq, unsigned int flags)
2625 {
2626 struct amdgpu_device *adev = ring->adev;
2627
2628 /* we only allocate 32bit for each seq wb address */
2629 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
2630
2631 /* write fence seq to the "addr" */
2632 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2633 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
2634 WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
2635 amdgpu_ring_write(ring, lower_32_bits(addr));
2636 amdgpu_ring_write(ring, upper_32_bits(addr));
2637 amdgpu_ring_write(ring, lower_32_bits(seq));
2638
2639 if (flags & AMDGPU_FENCE_FLAG_INT) {
2640 /* set register to trigger INT */
2641 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2642 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
2643 WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
2644 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCPC_INT_STATUS));
2645 amdgpu_ring_write(ring, 0);
2646 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
2647 }
2648 }
2649
gfx_v9_4_3_ring_emit_rreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t reg_val_offs)2650 static void gfx_v9_4_3_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
2651 uint32_t reg_val_offs)
2652 {
2653 struct amdgpu_device *adev = ring->adev;
2654
2655 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
2656 amdgpu_ring_write(ring, 0 | /* src: register*/
2657 (5 << 8) | /* dst: memory */
2658 (1 << 20)); /* write confirm */
2659 amdgpu_ring_write(ring, reg);
2660 amdgpu_ring_write(ring, 0);
2661 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
2662 reg_val_offs * 4));
2663 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
2664 reg_val_offs * 4));
2665 }
2666
gfx_v9_4_3_ring_emit_wreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t val)2667 static void gfx_v9_4_3_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
2668 uint32_t val)
2669 {
2670 uint32_t cmd = 0;
2671
2672 switch (ring->funcs->type) {
2673 case AMDGPU_RING_TYPE_GFX:
2674 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
2675 break;
2676 case AMDGPU_RING_TYPE_KIQ:
2677 cmd = (1 << 16); /* no inc addr */
2678 break;
2679 default:
2680 cmd = WR_CONFIRM;
2681 break;
2682 }
2683 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2684 amdgpu_ring_write(ring, cmd);
2685 amdgpu_ring_write(ring, reg);
2686 amdgpu_ring_write(ring, 0);
2687 amdgpu_ring_write(ring, val);
2688 }
2689
gfx_v9_4_3_ring_emit_reg_wait(struct amdgpu_ring * ring,uint32_t reg,uint32_t val,uint32_t mask)2690 static void gfx_v9_4_3_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
2691 uint32_t val, uint32_t mask)
2692 {
2693 gfx_v9_4_3_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
2694 }
2695
gfx_v9_4_3_ring_emit_reg_write_reg_wait(struct amdgpu_ring * ring,uint32_t reg0,uint32_t reg1,uint32_t ref,uint32_t mask)2696 static void gfx_v9_4_3_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
2697 uint32_t reg0, uint32_t reg1,
2698 uint32_t ref, uint32_t mask)
2699 {
2700 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
2701 ref, mask);
2702 }
2703
gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(struct amdgpu_device * adev,int me,int pipe,enum amdgpu_interrupt_state state,int xcc_id)2704 static void gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(
2705 struct amdgpu_device *adev, int me, int pipe,
2706 enum amdgpu_interrupt_state state, int xcc_id)
2707 {
2708 u32 mec_int_cntl, mec_int_cntl_reg;
2709
2710 /*
2711 * amdgpu controls only the first MEC. That's why this function only
2712 * handles the setting of interrupts for this specific MEC. All other
2713 * pipes' interrupts are set by amdkfd.
2714 */
2715
2716 if (me == 1) {
2717 switch (pipe) {
2718 case 0:
2719 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL);
2720 break;
2721 case 1:
2722 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL);
2723 break;
2724 case 2:
2725 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL);
2726 break;
2727 case 3:
2728 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL);
2729 break;
2730 default:
2731 DRM_DEBUG("invalid pipe %d\n", pipe);
2732 return;
2733 }
2734 } else {
2735 DRM_DEBUG("invalid me %d\n", me);
2736 return;
2737 }
2738
2739 switch (state) {
2740 case AMDGPU_IRQ_STATE_DISABLE:
2741 mec_int_cntl = RREG32(mec_int_cntl_reg);
2742 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
2743 TIME_STAMP_INT_ENABLE, 0);
2744 WREG32(mec_int_cntl_reg, mec_int_cntl);
2745 break;
2746 case AMDGPU_IRQ_STATE_ENABLE:
2747 mec_int_cntl = RREG32(mec_int_cntl_reg);
2748 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
2749 TIME_STAMP_INT_ENABLE, 1);
2750 WREG32(mec_int_cntl_reg, mec_int_cntl);
2751 break;
2752 default:
2753 break;
2754 }
2755 }
2756
gfx_v9_4_3_set_priv_reg_fault_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)2757 static int gfx_v9_4_3_set_priv_reg_fault_state(struct amdgpu_device *adev,
2758 struct amdgpu_irq_src *source,
2759 unsigned type,
2760 enum amdgpu_interrupt_state state)
2761 {
2762 int i, num_xcc;
2763
2764 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
2765 switch (state) {
2766 case AMDGPU_IRQ_STATE_DISABLE:
2767 case AMDGPU_IRQ_STATE_ENABLE:
2768 for (i = 0; i < num_xcc; i++)
2769 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0,
2770 PRIV_REG_INT_ENABLE,
2771 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
2772 break;
2773 default:
2774 break;
2775 }
2776
2777 return 0;
2778 }
2779
gfx_v9_4_3_set_priv_inst_fault_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)2780 static int gfx_v9_4_3_set_priv_inst_fault_state(struct amdgpu_device *adev,
2781 struct amdgpu_irq_src *source,
2782 unsigned type,
2783 enum amdgpu_interrupt_state state)
2784 {
2785 int i, num_xcc;
2786
2787 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
2788 switch (state) {
2789 case AMDGPU_IRQ_STATE_DISABLE:
2790 case AMDGPU_IRQ_STATE_ENABLE:
2791 for (i = 0; i < num_xcc; i++)
2792 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0,
2793 PRIV_INSTR_INT_ENABLE,
2794 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
2795 break;
2796 default:
2797 break;
2798 }
2799
2800 return 0;
2801 }
2802
gfx_v9_4_3_set_eop_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned type,enum amdgpu_interrupt_state state)2803 static int gfx_v9_4_3_set_eop_interrupt_state(struct amdgpu_device *adev,
2804 struct amdgpu_irq_src *src,
2805 unsigned type,
2806 enum amdgpu_interrupt_state state)
2807 {
2808 int i, num_xcc;
2809
2810 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
2811 for (i = 0; i < num_xcc; i++) {
2812 switch (type) {
2813 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
2814 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(
2815 adev, 1, 0, state, i);
2816 break;
2817 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
2818 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(
2819 adev, 1, 1, state, i);
2820 break;
2821 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
2822 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(
2823 adev, 1, 2, state, i);
2824 break;
2825 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
2826 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(
2827 adev, 1, 3, state, i);
2828 break;
2829 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
2830 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(
2831 adev, 2, 0, state, i);
2832 break;
2833 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
2834 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(
2835 adev, 2, 1, state, i);
2836 break;
2837 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
2838 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(
2839 adev, 2, 2, state, i);
2840 break;
2841 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
2842 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(
2843 adev, 2, 3, state, i);
2844 break;
2845 default:
2846 break;
2847 }
2848 }
2849
2850 return 0;
2851 }
2852
gfx_v9_4_3_eop_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)2853 static int gfx_v9_4_3_eop_irq(struct amdgpu_device *adev,
2854 struct amdgpu_irq_src *source,
2855 struct amdgpu_iv_entry *entry)
2856 {
2857 int i, xcc_id;
2858 u8 me_id, pipe_id, queue_id;
2859 struct amdgpu_ring *ring;
2860
2861 DRM_DEBUG("IH: CP EOP\n");
2862 me_id = (entry->ring_id & 0x0c) >> 2;
2863 pipe_id = (entry->ring_id & 0x03) >> 0;
2864 queue_id = (entry->ring_id & 0x70) >> 4;
2865
2866 xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id);
2867
2868 if (xcc_id == -EINVAL)
2869 return -EINVAL;
2870
2871 switch (me_id) {
2872 case 0:
2873 case 1:
2874 case 2:
2875 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2876 ring = &adev->gfx.compute_ring
2877 [i +
2878 xcc_id * adev->gfx.num_compute_rings];
2879 /* Per-queue interrupt is supported for MEC starting from VI.
2880 * The interrupt can only be enabled/disabled per pipe instead of per queue.
2881 */
2882
2883 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
2884 amdgpu_fence_process(ring);
2885 }
2886 break;
2887 }
2888 return 0;
2889 }
2890
gfx_v9_4_3_fault(struct amdgpu_device * adev,struct amdgpu_iv_entry * entry)2891 static void gfx_v9_4_3_fault(struct amdgpu_device *adev,
2892 struct amdgpu_iv_entry *entry)
2893 {
2894 u8 me_id, pipe_id, queue_id;
2895 struct amdgpu_ring *ring;
2896 int i, xcc_id;
2897
2898 me_id = (entry->ring_id & 0x0c) >> 2;
2899 pipe_id = (entry->ring_id & 0x03) >> 0;
2900 queue_id = (entry->ring_id & 0x70) >> 4;
2901
2902 xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id);
2903
2904 if (xcc_id == -EINVAL)
2905 return;
2906
2907 switch (me_id) {
2908 case 0:
2909 case 1:
2910 case 2:
2911 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2912 ring = &adev->gfx.compute_ring
2913 [i +
2914 xcc_id * adev->gfx.num_compute_rings];
2915 if (ring->me == me_id && ring->pipe == pipe_id &&
2916 ring->queue == queue_id)
2917 drm_sched_fault(&ring->sched);
2918 }
2919 break;
2920 }
2921 }
2922
gfx_v9_4_3_priv_reg_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)2923 static int gfx_v9_4_3_priv_reg_irq(struct amdgpu_device *adev,
2924 struct amdgpu_irq_src *source,
2925 struct amdgpu_iv_entry *entry)
2926 {
2927 DRM_ERROR("Illegal register access in command stream\n");
2928 gfx_v9_4_3_fault(adev, entry);
2929 return 0;
2930 }
2931
gfx_v9_4_3_priv_inst_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)2932 static int gfx_v9_4_3_priv_inst_irq(struct amdgpu_device *adev,
2933 struct amdgpu_irq_src *source,
2934 struct amdgpu_iv_entry *entry)
2935 {
2936 DRM_ERROR("Illegal instruction in command stream\n");
2937 gfx_v9_4_3_fault(adev, entry);
2938 return 0;
2939 }
2940
gfx_v9_4_3_emit_mem_sync(struct amdgpu_ring * ring)2941 static void gfx_v9_4_3_emit_mem_sync(struct amdgpu_ring *ring)
2942 {
2943 const unsigned int cp_coher_cntl =
2944 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(1) |
2945 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(1) |
2946 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(1) |
2947 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(1) |
2948 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(1);
2949
2950 /* ACQUIRE_MEM -make one or more surfaces valid for use by the subsequent operations */
2951 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5));
2952 amdgpu_ring_write(ring, cp_coher_cntl); /* CP_COHER_CNTL */
2953 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */
2954 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */
2955 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
2956 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */
2957 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
2958 }
2959
gfx_v9_4_3_emit_wave_limit_cs(struct amdgpu_ring * ring,uint32_t pipe,bool enable)2960 static void gfx_v9_4_3_emit_wave_limit_cs(struct amdgpu_ring *ring,
2961 uint32_t pipe, bool enable)
2962 {
2963 struct amdgpu_device *adev = ring->adev;
2964 uint32_t val;
2965 uint32_t wcl_cs_reg;
2966
2967 /* regSPI_WCL_PIPE_PERCENT_CS[0-7]_DEFAULT values are same */
2968 val = enable ? 0x1 : 0x7f;
2969
2970 switch (pipe) {
2971 case 0:
2972 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS0);
2973 break;
2974 case 1:
2975 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS1);
2976 break;
2977 case 2:
2978 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS2);
2979 break;
2980 case 3:
2981 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS3);
2982 break;
2983 default:
2984 DRM_DEBUG("invalid pipe %d\n", pipe);
2985 return;
2986 }
2987
2988 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val);
2989
2990 }
gfx_v9_4_3_emit_wave_limit(struct amdgpu_ring * ring,bool enable)2991 static void gfx_v9_4_3_emit_wave_limit(struct amdgpu_ring *ring, bool enable)
2992 {
2993 struct amdgpu_device *adev = ring->adev;
2994 uint32_t val;
2995 int i;
2996
2997 /* regSPI_WCL_PIPE_PERCENT_GFX is 7 bit multiplier register to limit
2998 * number of gfx waves. Setting 5 bit will make sure gfx only gets
2999 * around 25% of gpu resources.
3000 */
3001 val = enable ? 0x1f : 0x07ffffff;
3002 amdgpu_ring_emit_wreg(ring,
3003 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_GFX),
3004 val);
3005
3006 /* Restrict waves for normal/low priority compute queues as well
3007 * to get best QoS for high priority compute jobs.
3008 *
3009 * amdgpu controls only 1st ME(0-3 CS pipes).
3010 */
3011 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) {
3012 if (i != ring->pipe)
3013 gfx_v9_4_3_emit_wave_limit_cs(ring, i, enable);
3014
3015 }
3016 }
3017
3018 enum amdgpu_gfx_cp_ras_mem_id {
3019 AMDGPU_GFX_CP_MEM1 = 1,
3020 AMDGPU_GFX_CP_MEM2,
3021 AMDGPU_GFX_CP_MEM3,
3022 AMDGPU_GFX_CP_MEM4,
3023 AMDGPU_GFX_CP_MEM5,
3024 };
3025
3026 enum amdgpu_gfx_gcea_ras_mem_id {
3027 AMDGPU_GFX_GCEA_IOWR_CMDMEM = 4,
3028 AMDGPU_GFX_GCEA_IORD_CMDMEM,
3029 AMDGPU_GFX_GCEA_GMIWR_CMDMEM,
3030 AMDGPU_GFX_GCEA_GMIRD_CMDMEM,
3031 AMDGPU_GFX_GCEA_DRAMWR_CMDMEM,
3032 AMDGPU_GFX_GCEA_DRAMRD_CMDMEM,
3033 AMDGPU_GFX_GCEA_MAM_DMEM0,
3034 AMDGPU_GFX_GCEA_MAM_DMEM1,
3035 AMDGPU_GFX_GCEA_MAM_DMEM2,
3036 AMDGPU_GFX_GCEA_MAM_DMEM3,
3037 AMDGPU_GFX_GCEA_MAM_AMEM0,
3038 AMDGPU_GFX_GCEA_MAM_AMEM1,
3039 AMDGPU_GFX_GCEA_MAM_AMEM2,
3040 AMDGPU_GFX_GCEA_MAM_AMEM3,
3041 AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER,
3042 AMDGPU_GFX_GCEA_WRET_TAGMEM,
3043 AMDGPU_GFX_GCEA_RRET_TAGMEM,
3044 AMDGPU_GFX_GCEA_IOWR_DATAMEM,
3045 AMDGPU_GFX_GCEA_GMIWR_DATAMEM,
3046 AMDGPU_GFX_GCEA_DRAM_DATAMEM,
3047 };
3048
3049 enum amdgpu_gfx_gc_cane_ras_mem_id {
3050 AMDGPU_GFX_GC_CANE_MEM0 = 0,
3051 };
3052
3053 enum amdgpu_gfx_gcutcl2_ras_mem_id {
3054 AMDGPU_GFX_GCUTCL2_MEM2P512X95 = 160,
3055 };
3056
3057 enum amdgpu_gfx_gds_ras_mem_id {
3058 AMDGPU_GFX_GDS_MEM0 = 0,
3059 };
3060
3061 enum amdgpu_gfx_lds_ras_mem_id {
3062 AMDGPU_GFX_LDS_BANK0 = 0,
3063 AMDGPU_GFX_LDS_BANK1,
3064 AMDGPU_GFX_LDS_BANK2,
3065 AMDGPU_GFX_LDS_BANK3,
3066 AMDGPU_GFX_LDS_BANK4,
3067 AMDGPU_GFX_LDS_BANK5,
3068 AMDGPU_GFX_LDS_BANK6,
3069 AMDGPU_GFX_LDS_BANK7,
3070 AMDGPU_GFX_LDS_BANK8,
3071 AMDGPU_GFX_LDS_BANK9,
3072 AMDGPU_GFX_LDS_BANK10,
3073 AMDGPU_GFX_LDS_BANK11,
3074 AMDGPU_GFX_LDS_BANK12,
3075 AMDGPU_GFX_LDS_BANK13,
3076 AMDGPU_GFX_LDS_BANK14,
3077 AMDGPU_GFX_LDS_BANK15,
3078 AMDGPU_GFX_LDS_BANK16,
3079 AMDGPU_GFX_LDS_BANK17,
3080 AMDGPU_GFX_LDS_BANK18,
3081 AMDGPU_GFX_LDS_BANK19,
3082 AMDGPU_GFX_LDS_BANK20,
3083 AMDGPU_GFX_LDS_BANK21,
3084 AMDGPU_GFX_LDS_BANK22,
3085 AMDGPU_GFX_LDS_BANK23,
3086 AMDGPU_GFX_LDS_BANK24,
3087 AMDGPU_GFX_LDS_BANK25,
3088 AMDGPU_GFX_LDS_BANK26,
3089 AMDGPU_GFX_LDS_BANK27,
3090 AMDGPU_GFX_LDS_BANK28,
3091 AMDGPU_GFX_LDS_BANK29,
3092 AMDGPU_GFX_LDS_BANK30,
3093 AMDGPU_GFX_LDS_BANK31,
3094 AMDGPU_GFX_LDS_SP_BUFFER_A,
3095 AMDGPU_GFX_LDS_SP_BUFFER_B,
3096 };
3097
3098 enum amdgpu_gfx_rlc_ras_mem_id {
3099 AMDGPU_GFX_RLC_GPMF32 = 1,
3100 AMDGPU_GFX_RLC_RLCVF32,
3101 AMDGPU_GFX_RLC_SCRATCH,
3102 AMDGPU_GFX_RLC_SRM_ARAM,
3103 AMDGPU_GFX_RLC_SRM_DRAM,
3104 AMDGPU_GFX_RLC_TCTAG,
3105 AMDGPU_GFX_RLC_SPM_SE,
3106 AMDGPU_GFX_RLC_SPM_GRBMT,
3107 };
3108
3109 enum amdgpu_gfx_sp_ras_mem_id {
3110 AMDGPU_GFX_SP_SIMDID0 = 0,
3111 };
3112
3113 enum amdgpu_gfx_spi_ras_mem_id {
3114 AMDGPU_GFX_SPI_MEM0 = 0,
3115 AMDGPU_GFX_SPI_MEM1,
3116 AMDGPU_GFX_SPI_MEM2,
3117 AMDGPU_GFX_SPI_MEM3,
3118 };
3119
3120 enum amdgpu_gfx_sqc_ras_mem_id {
3121 AMDGPU_GFX_SQC_INST_CACHE_A = 100,
3122 AMDGPU_GFX_SQC_INST_CACHE_B = 101,
3123 AMDGPU_GFX_SQC_INST_CACHE_TAG_A = 102,
3124 AMDGPU_GFX_SQC_INST_CACHE_TAG_B = 103,
3125 AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A = 104,
3126 AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B = 105,
3127 AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A = 106,
3128 AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B = 107,
3129 AMDGPU_GFX_SQC_DATA_CACHE_A = 200,
3130 AMDGPU_GFX_SQC_DATA_CACHE_B = 201,
3131 AMDGPU_GFX_SQC_DATA_CACHE_TAG_A = 202,
3132 AMDGPU_GFX_SQC_DATA_CACHE_TAG_B = 203,
3133 AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A = 204,
3134 AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B = 205,
3135 AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A = 206,
3136 AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B = 207,
3137 AMDGPU_GFX_SQC_DIRTY_BIT_A = 208,
3138 AMDGPU_GFX_SQC_DIRTY_BIT_B = 209,
3139 AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0 = 210,
3140 AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1 = 211,
3141 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A = 212,
3142 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B = 213,
3143 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE = 108,
3144 };
3145
3146 enum amdgpu_gfx_sq_ras_mem_id {
3147 AMDGPU_GFX_SQ_SGPR_MEM0 = 0,
3148 AMDGPU_GFX_SQ_SGPR_MEM1,
3149 AMDGPU_GFX_SQ_SGPR_MEM2,
3150 AMDGPU_GFX_SQ_SGPR_MEM3,
3151 };
3152
3153 enum amdgpu_gfx_ta_ras_mem_id {
3154 AMDGPU_GFX_TA_FS_AFIFO_RAM_LO = 1,
3155 AMDGPU_GFX_TA_FS_AFIFO_RAM_HI,
3156 AMDGPU_GFX_TA_FS_CFIFO_RAM,
3157 AMDGPU_GFX_TA_FSX_LFIFO,
3158 AMDGPU_GFX_TA_FS_DFIFO_RAM,
3159 };
3160
3161 enum amdgpu_gfx_tcc_ras_mem_id {
3162 AMDGPU_GFX_TCC_MEM1 = 1,
3163 };
3164
3165 enum amdgpu_gfx_tca_ras_mem_id {
3166 AMDGPU_GFX_TCA_MEM1 = 1,
3167 };
3168
3169 enum amdgpu_gfx_tci_ras_mem_id {
3170 AMDGPU_GFX_TCIW_MEM = 1,
3171 };
3172
3173 enum amdgpu_gfx_tcp_ras_mem_id {
3174 AMDGPU_GFX_TCP_LFIFO0 = 1,
3175 AMDGPU_GFX_TCP_SET0BANK0_RAM,
3176 AMDGPU_GFX_TCP_SET0BANK1_RAM,
3177 AMDGPU_GFX_TCP_SET0BANK2_RAM,
3178 AMDGPU_GFX_TCP_SET0BANK3_RAM,
3179 AMDGPU_GFX_TCP_SET1BANK0_RAM,
3180 AMDGPU_GFX_TCP_SET1BANK1_RAM,
3181 AMDGPU_GFX_TCP_SET1BANK2_RAM,
3182 AMDGPU_GFX_TCP_SET1BANK3_RAM,
3183 AMDGPU_GFX_TCP_SET2BANK0_RAM,
3184 AMDGPU_GFX_TCP_SET2BANK1_RAM,
3185 AMDGPU_GFX_TCP_SET2BANK2_RAM,
3186 AMDGPU_GFX_TCP_SET2BANK3_RAM,
3187 AMDGPU_GFX_TCP_SET3BANK0_RAM,
3188 AMDGPU_GFX_TCP_SET3BANK1_RAM,
3189 AMDGPU_GFX_TCP_SET3BANK2_RAM,
3190 AMDGPU_GFX_TCP_SET3BANK3_RAM,
3191 AMDGPU_GFX_TCP_VM_FIFO,
3192 AMDGPU_GFX_TCP_DB_TAGRAM0,
3193 AMDGPU_GFX_TCP_DB_TAGRAM1,
3194 AMDGPU_GFX_TCP_DB_TAGRAM2,
3195 AMDGPU_GFX_TCP_DB_TAGRAM3,
3196 AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0,
3197 AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1,
3198 AMDGPU_GFX_TCP_CMD_FIFO,
3199 };
3200
3201 enum amdgpu_gfx_td_ras_mem_id {
3202 AMDGPU_GFX_TD_UTD_CS_FIFO_MEM = 1,
3203 AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM,
3204 AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM,
3205 };
3206
3207 enum amdgpu_gfx_tcx_ras_mem_id {
3208 AMDGPU_GFX_TCX_FIFOD0 = 0,
3209 AMDGPU_GFX_TCX_FIFOD1,
3210 AMDGPU_GFX_TCX_FIFOD2,
3211 AMDGPU_GFX_TCX_FIFOD3,
3212 AMDGPU_GFX_TCX_FIFOD4,
3213 AMDGPU_GFX_TCX_FIFOD5,
3214 AMDGPU_GFX_TCX_FIFOD6,
3215 AMDGPU_GFX_TCX_FIFOD7,
3216 AMDGPU_GFX_TCX_FIFOB0,
3217 AMDGPU_GFX_TCX_FIFOB1,
3218 AMDGPU_GFX_TCX_FIFOB2,
3219 AMDGPU_GFX_TCX_FIFOB3,
3220 AMDGPU_GFX_TCX_FIFOB4,
3221 AMDGPU_GFX_TCX_FIFOB5,
3222 AMDGPU_GFX_TCX_FIFOB6,
3223 AMDGPU_GFX_TCX_FIFOB7,
3224 AMDGPU_GFX_TCX_FIFOA0,
3225 AMDGPU_GFX_TCX_FIFOA1,
3226 AMDGPU_GFX_TCX_FIFOA2,
3227 AMDGPU_GFX_TCX_FIFOA3,
3228 AMDGPU_GFX_TCX_FIFOA4,
3229 AMDGPU_GFX_TCX_FIFOA5,
3230 AMDGPU_GFX_TCX_FIFOA6,
3231 AMDGPU_GFX_TCX_FIFOA7,
3232 AMDGPU_GFX_TCX_CFIFO0,
3233 AMDGPU_GFX_TCX_CFIFO1,
3234 AMDGPU_GFX_TCX_CFIFO2,
3235 AMDGPU_GFX_TCX_CFIFO3,
3236 AMDGPU_GFX_TCX_CFIFO4,
3237 AMDGPU_GFX_TCX_CFIFO5,
3238 AMDGPU_GFX_TCX_CFIFO6,
3239 AMDGPU_GFX_TCX_CFIFO7,
3240 AMDGPU_GFX_TCX_FIFO_ACKB0,
3241 AMDGPU_GFX_TCX_FIFO_ACKB1,
3242 AMDGPU_GFX_TCX_FIFO_ACKB2,
3243 AMDGPU_GFX_TCX_FIFO_ACKB3,
3244 AMDGPU_GFX_TCX_FIFO_ACKB4,
3245 AMDGPU_GFX_TCX_FIFO_ACKB5,
3246 AMDGPU_GFX_TCX_FIFO_ACKB6,
3247 AMDGPU_GFX_TCX_FIFO_ACKB7,
3248 AMDGPU_GFX_TCX_FIFO_ACKD0,
3249 AMDGPU_GFX_TCX_FIFO_ACKD1,
3250 AMDGPU_GFX_TCX_FIFO_ACKD2,
3251 AMDGPU_GFX_TCX_FIFO_ACKD3,
3252 AMDGPU_GFX_TCX_FIFO_ACKD4,
3253 AMDGPU_GFX_TCX_FIFO_ACKD5,
3254 AMDGPU_GFX_TCX_FIFO_ACKD6,
3255 AMDGPU_GFX_TCX_FIFO_ACKD7,
3256 AMDGPU_GFX_TCX_DST_FIFOA0,
3257 AMDGPU_GFX_TCX_DST_FIFOA1,
3258 AMDGPU_GFX_TCX_DST_FIFOA2,
3259 AMDGPU_GFX_TCX_DST_FIFOA3,
3260 AMDGPU_GFX_TCX_DST_FIFOA4,
3261 AMDGPU_GFX_TCX_DST_FIFOA5,
3262 AMDGPU_GFX_TCX_DST_FIFOA6,
3263 AMDGPU_GFX_TCX_DST_FIFOA7,
3264 AMDGPU_GFX_TCX_DST_FIFOB0,
3265 AMDGPU_GFX_TCX_DST_FIFOB1,
3266 AMDGPU_GFX_TCX_DST_FIFOB2,
3267 AMDGPU_GFX_TCX_DST_FIFOB3,
3268 AMDGPU_GFX_TCX_DST_FIFOB4,
3269 AMDGPU_GFX_TCX_DST_FIFOB5,
3270 AMDGPU_GFX_TCX_DST_FIFOB6,
3271 AMDGPU_GFX_TCX_DST_FIFOB7,
3272 AMDGPU_GFX_TCX_DST_FIFOD0,
3273 AMDGPU_GFX_TCX_DST_FIFOD1,
3274 AMDGPU_GFX_TCX_DST_FIFOD2,
3275 AMDGPU_GFX_TCX_DST_FIFOD3,
3276 AMDGPU_GFX_TCX_DST_FIFOD4,
3277 AMDGPU_GFX_TCX_DST_FIFOD5,
3278 AMDGPU_GFX_TCX_DST_FIFOD6,
3279 AMDGPU_GFX_TCX_DST_FIFOD7,
3280 AMDGPU_GFX_TCX_DST_FIFO_ACKB0,
3281 AMDGPU_GFX_TCX_DST_FIFO_ACKB1,
3282 AMDGPU_GFX_TCX_DST_FIFO_ACKB2,
3283 AMDGPU_GFX_TCX_DST_FIFO_ACKB3,
3284 AMDGPU_GFX_TCX_DST_FIFO_ACKB4,
3285 AMDGPU_GFX_TCX_DST_FIFO_ACKB5,
3286 AMDGPU_GFX_TCX_DST_FIFO_ACKB6,
3287 AMDGPU_GFX_TCX_DST_FIFO_ACKB7,
3288 AMDGPU_GFX_TCX_DST_FIFO_ACKD0,
3289 AMDGPU_GFX_TCX_DST_FIFO_ACKD1,
3290 AMDGPU_GFX_TCX_DST_FIFO_ACKD2,
3291 AMDGPU_GFX_TCX_DST_FIFO_ACKD3,
3292 AMDGPU_GFX_TCX_DST_FIFO_ACKD4,
3293 AMDGPU_GFX_TCX_DST_FIFO_ACKD5,
3294 AMDGPU_GFX_TCX_DST_FIFO_ACKD6,
3295 AMDGPU_GFX_TCX_DST_FIFO_ACKD7,
3296 };
3297
3298 enum amdgpu_gfx_atc_l2_ras_mem_id {
3299 AMDGPU_GFX_ATC_L2_MEM0 = 0,
3300 };
3301
3302 enum amdgpu_gfx_utcl2_ras_mem_id {
3303 AMDGPU_GFX_UTCL2_MEM0 = 0,
3304 };
3305
3306 enum amdgpu_gfx_vml2_ras_mem_id {
3307 AMDGPU_GFX_VML2_MEM0 = 0,
3308 };
3309
3310 enum amdgpu_gfx_vml2_walker_ras_mem_id {
3311 AMDGPU_GFX_VML2_WALKER_MEM0 = 0,
3312 };
3313
3314 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_cp_mem_list[] = {
3315 {AMDGPU_GFX_CP_MEM1, "CP_MEM1"},
3316 {AMDGPU_GFX_CP_MEM2, "CP_MEM2"},
3317 {AMDGPU_GFX_CP_MEM3, "CP_MEM3"},
3318 {AMDGPU_GFX_CP_MEM4, "CP_MEM4"},
3319 {AMDGPU_GFX_CP_MEM5, "CP_MEM5"},
3320 };
3321
3322 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcea_mem_list[] = {
3323 {AMDGPU_GFX_GCEA_IOWR_CMDMEM, "GCEA_IOWR_CMDMEM"},
3324 {AMDGPU_GFX_GCEA_IORD_CMDMEM, "GCEA_IORD_CMDMEM"},
3325 {AMDGPU_GFX_GCEA_GMIWR_CMDMEM, "GCEA_GMIWR_CMDMEM"},
3326 {AMDGPU_GFX_GCEA_GMIRD_CMDMEM, "GCEA_GMIRD_CMDMEM"},
3327 {AMDGPU_GFX_GCEA_DRAMWR_CMDMEM, "GCEA_DRAMWR_CMDMEM"},
3328 {AMDGPU_GFX_GCEA_DRAMRD_CMDMEM, "GCEA_DRAMRD_CMDMEM"},
3329 {AMDGPU_GFX_GCEA_MAM_DMEM0, "GCEA_MAM_DMEM0"},
3330 {AMDGPU_GFX_GCEA_MAM_DMEM1, "GCEA_MAM_DMEM1"},
3331 {AMDGPU_GFX_GCEA_MAM_DMEM2, "GCEA_MAM_DMEM2"},
3332 {AMDGPU_GFX_GCEA_MAM_DMEM3, "GCEA_MAM_DMEM3"},
3333 {AMDGPU_GFX_GCEA_MAM_AMEM0, "GCEA_MAM_AMEM0"},
3334 {AMDGPU_GFX_GCEA_MAM_AMEM1, "GCEA_MAM_AMEM1"},
3335 {AMDGPU_GFX_GCEA_MAM_AMEM2, "GCEA_MAM_AMEM2"},
3336 {AMDGPU_GFX_GCEA_MAM_AMEM3, "GCEA_MAM_AMEM3"},
3337 {AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER, "GCEA_MAM_AFLUSH_BUFFER"},
3338 {AMDGPU_GFX_GCEA_WRET_TAGMEM, "GCEA_WRET_TAGMEM"},
3339 {AMDGPU_GFX_GCEA_RRET_TAGMEM, "GCEA_RRET_TAGMEM"},
3340 {AMDGPU_GFX_GCEA_IOWR_DATAMEM, "GCEA_IOWR_DATAMEM"},
3341 {AMDGPU_GFX_GCEA_GMIWR_DATAMEM, "GCEA_GMIWR_DATAMEM"},
3342 {AMDGPU_GFX_GCEA_DRAM_DATAMEM, "GCEA_DRAM_DATAMEM"},
3343 };
3344
3345 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gc_cane_mem_list[] = {
3346 {AMDGPU_GFX_GC_CANE_MEM0, "GC_CANE_MEM0"},
3347 };
3348
3349 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcutcl2_mem_list[] = {
3350 {AMDGPU_GFX_GCUTCL2_MEM2P512X95, "GCUTCL2_MEM2P512X95"},
3351 };
3352
3353 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gds_mem_list[] = {
3354 {AMDGPU_GFX_GDS_MEM0, "GDS_MEM"},
3355 };
3356
3357 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_lds_mem_list[] = {
3358 {AMDGPU_GFX_LDS_BANK0, "LDS_BANK0"},
3359 {AMDGPU_GFX_LDS_BANK1, "LDS_BANK1"},
3360 {AMDGPU_GFX_LDS_BANK2, "LDS_BANK2"},
3361 {AMDGPU_GFX_LDS_BANK3, "LDS_BANK3"},
3362 {AMDGPU_GFX_LDS_BANK4, "LDS_BANK4"},
3363 {AMDGPU_GFX_LDS_BANK5, "LDS_BANK5"},
3364 {AMDGPU_GFX_LDS_BANK6, "LDS_BANK6"},
3365 {AMDGPU_GFX_LDS_BANK7, "LDS_BANK7"},
3366 {AMDGPU_GFX_LDS_BANK8, "LDS_BANK8"},
3367 {AMDGPU_GFX_LDS_BANK9, "LDS_BANK9"},
3368 {AMDGPU_GFX_LDS_BANK10, "LDS_BANK10"},
3369 {AMDGPU_GFX_LDS_BANK11, "LDS_BANK11"},
3370 {AMDGPU_GFX_LDS_BANK12, "LDS_BANK12"},
3371 {AMDGPU_GFX_LDS_BANK13, "LDS_BANK13"},
3372 {AMDGPU_GFX_LDS_BANK14, "LDS_BANK14"},
3373 {AMDGPU_GFX_LDS_BANK15, "LDS_BANK15"},
3374 {AMDGPU_GFX_LDS_BANK16, "LDS_BANK16"},
3375 {AMDGPU_GFX_LDS_BANK17, "LDS_BANK17"},
3376 {AMDGPU_GFX_LDS_BANK18, "LDS_BANK18"},
3377 {AMDGPU_GFX_LDS_BANK19, "LDS_BANK19"},
3378 {AMDGPU_GFX_LDS_BANK20, "LDS_BANK20"},
3379 {AMDGPU_GFX_LDS_BANK21, "LDS_BANK21"},
3380 {AMDGPU_GFX_LDS_BANK22, "LDS_BANK22"},
3381 {AMDGPU_GFX_LDS_BANK23, "LDS_BANK23"},
3382 {AMDGPU_GFX_LDS_BANK24, "LDS_BANK24"},
3383 {AMDGPU_GFX_LDS_BANK25, "LDS_BANK25"},
3384 {AMDGPU_GFX_LDS_BANK26, "LDS_BANK26"},
3385 {AMDGPU_GFX_LDS_BANK27, "LDS_BANK27"},
3386 {AMDGPU_GFX_LDS_BANK28, "LDS_BANK28"},
3387 {AMDGPU_GFX_LDS_BANK29, "LDS_BANK29"},
3388 {AMDGPU_GFX_LDS_BANK30, "LDS_BANK30"},
3389 {AMDGPU_GFX_LDS_BANK31, "LDS_BANK31"},
3390 {AMDGPU_GFX_LDS_SP_BUFFER_A, "LDS_SP_BUFFER_A"},
3391 {AMDGPU_GFX_LDS_SP_BUFFER_B, "LDS_SP_BUFFER_B"},
3392 };
3393
3394 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_rlc_mem_list[] = {
3395 {AMDGPU_GFX_RLC_GPMF32, "RLC_GPMF32"},
3396 {AMDGPU_GFX_RLC_RLCVF32, "RLC_RLCVF32"},
3397 {AMDGPU_GFX_RLC_SCRATCH, "RLC_SCRATCH"},
3398 {AMDGPU_GFX_RLC_SRM_ARAM, "RLC_SRM_ARAM"},
3399 {AMDGPU_GFX_RLC_SRM_DRAM, "RLC_SRM_DRAM"},
3400 {AMDGPU_GFX_RLC_TCTAG, "RLC_TCTAG"},
3401 {AMDGPU_GFX_RLC_SPM_SE, "RLC_SPM_SE"},
3402 {AMDGPU_GFX_RLC_SPM_GRBMT, "RLC_SPM_GRBMT"},
3403 };
3404
3405 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sp_mem_list[] = {
3406 {AMDGPU_GFX_SP_SIMDID0, "SP_SIMDID0"},
3407 };
3408
3409 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_spi_mem_list[] = {
3410 {AMDGPU_GFX_SPI_MEM0, "SPI_MEM0"},
3411 {AMDGPU_GFX_SPI_MEM1, "SPI_MEM1"},
3412 {AMDGPU_GFX_SPI_MEM2, "SPI_MEM2"},
3413 {AMDGPU_GFX_SPI_MEM3, "SPI_MEM3"},
3414 };
3415
3416 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sqc_mem_list[] = {
3417 {AMDGPU_GFX_SQC_INST_CACHE_A, "SQC_INST_CACHE_A"},
3418 {AMDGPU_GFX_SQC_INST_CACHE_B, "SQC_INST_CACHE_B"},
3419 {AMDGPU_GFX_SQC_INST_CACHE_TAG_A, "SQC_INST_CACHE_TAG_A"},
3420 {AMDGPU_GFX_SQC_INST_CACHE_TAG_B, "SQC_INST_CACHE_TAG_B"},
3421 {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A, "SQC_INST_CACHE_MISS_FIFO_A"},
3422 {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B, "SQC_INST_CACHE_MISS_FIFO_B"},
3423 {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A, "SQC_INST_CACHE_GATCL1_MISS_FIFO_A"},
3424 {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B, "SQC_INST_CACHE_GATCL1_MISS_FIFO_B"},
3425 {AMDGPU_GFX_SQC_DATA_CACHE_A, "SQC_DATA_CACHE_A"},
3426 {AMDGPU_GFX_SQC_DATA_CACHE_B, "SQC_DATA_CACHE_B"},
3427 {AMDGPU_GFX_SQC_DATA_CACHE_TAG_A, "SQC_DATA_CACHE_TAG_A"},
3428 {AMDGPU_GFX_SQC_DATA_CACHE_TAG_B, "SQC_DATA_CACHE_TAG_B"},
3429 {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A, "SQC_DATA_CACHE_MISS_FIFO_A"},
3430 {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B, "SQC_DATA_CACHE_MISS_FIFO_B"},
3431 {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A, "SQC_DATA_CACHE_HIT_FIFO_A"},
3432 {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B, "SQC_DATA_CACHE_HIT_FIFO_B"},
3433 {AMDGPU_GFX_SQC_DIRTY_BIT_A, "SQC_DIRTY_BIT_A"},
3434 {AMDGPU_GFX_SQC_DIRTY_BIT_B, "SQC_DIRTY_BIT_B"},
3435 {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0, "SQC_WRITE_DATA_BUFFER_CU0"},
3436 {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1, "SQC_WRITE_DATA_BUFFER_CU1"},
3437 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A"},
3438 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B"},
3439 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE, "SQC_UTCL1_MISS_LFIFO_INST_CACHE"},
3440 };
3441
3442 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sq_mem_list[] = {
3443 {AMDGPU_GFX_SQ_SGPR_MEM0, "SQ_SGPR_MEM0"},
3444 {AMDGPU_GFX_SQ_SGPR_MEM1, "SQ_SGPR_MEM1"},
3445 {AMDGPU_GFX_SQ_SGPR_MEM2, "SQ_SGPR_MEM2"},
3446 {AMDGPU_GFX_SQ_SGPR_MEM3, "SQ_SGPR_MEM3"},
3447 };
3448
3449 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_ta_mem_list[] = {
3450 {AMDGPU_GFX_TA_FS_AFIFO_RAM_LO, "TA_FS_AFIFO_RAM_LO"},
3451 {AMDGPU_GFX_TA_FS_AFIFO_RAM_HI, "TA_FS_AFIFO_RAM_HI"},
3452 {AMDGPU_GFX_TA_FS_CFIFO_RAM, "TA_FS_CFIFO_RAM"},
3453 {AMDGPU_GFX_TA_FSX_LFIFO, "TA_FSX_LFIFO"},
3454 {AMDGPU_GFX_TA_FS_DFIFO_RAM, "TA_FS_DFIFO_RAM"},
3455 };
3456
3457 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcc_mem_list[] = {
3458 {AMDGPU_GFX_TCC_MEM1, "TCC_MEM1"},
3459 };
3460
3461 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tca_mem_list[] = {
3462 {AMDGPU_GFX_TCA_MEM1, "TCA_MEM1"},
3463 };
3464
3465 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tci_mem_list[] = {
3466 {AMDGPU_GFX_TCIW_MEM, "TCIW_MEM"},
3467 };
3468
3469 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcp_mem_list[] = {
3470 {AMDGPU_GFX_TCP_LFIFO0, "TCP_LFIFO0"},
3471 {AMDGPU_GFX_TCP_SET0BANK0_RAM, "TCP_SET0BANK0_RAM"},
3472 {AMDGPU_GFX_TCP_SET0BANK1_RAM, "TCP_SET0BANK1_RAM"},
3473 {AMDGPU_GFX_TCP_SET0BANK2_RAM, "TCP_SET0BANK2_RAM"},
3474 {AMDGPU_GFX_TCP_SET0BANK3_RAM, "TCP_SET0BANK3_RAM"},
3475 {AMDGPU_GFX_TCP_SET1BANK0_RAM, "TCP_SET1BANK0_RAM"},
3476 {AMDGPU_GFX_TCP_SET1BANK1_RAM, "TCP_SET1BANK1_RAM"},
3477 {AMDGPU_GFX_TCP_SET1BANK2_RAM, "TCP_SET1BANK2_RAM"},
3478 {AMDGPU_GFX_TCP_SET1BANK3_RAM, "TCP_SET1BANK3_RAM"},
3479 {AMDGPU_GFX_TCP_SET2BANK0_RAM, "TCP_SET2BANK0_RAM"},
3480 {AMDGPU_GFX_TCP_SET2BANK1_RAM, "TCP_SET2BANK1_RAM"},
3481 {AMDGPU_GFX_TCP_SET2BANK2_RAM, "TCP_SET2BANK2_RAM"},
3482 {AMDGPU_GFX_TCP_SET2BANK3_RAM, "TCP_SET2BANK3_RAM"},
3483 {AMDGPU_GFX_TCP_SET3BANK0_RAM, "TCP_SET3BANK0_RAM"},
3484 {AMDGPU_GFX_TCP_SET3BANK1_RAM, "TCP_SET3BANK1_RAM"},
3485 {AMDGPU_GFX_TCP_SET3BANK2_RAM, "TCP_SET3BANK2_RAM"},
3486 {AMDGPU_GFX_TCP_SET3BANK3_RAM, "TCP_SET3BANK3_RAM"},
3487 {AMDGPU_GFX_TCP_VM_FIFO, "TCP_VM_FIFO"},
3488 {AMDGPU_GFX_TCP_DB_TAGRAM0, "TCP_DB_TAGRAM0"},
3489 {AMDGPU_GFX_TCP_DB_TAGRAM1, "TCP_DB_TAGRAM1"},
3490 {AMDGPU_GFX_TCP_DB_TAGRAM2, "TCP_DB_TAGRAM2"},
3491 {AMDGPU_GFX_TCP_DB_TAGRAM3, "TCP_DB_TAGRAM3"},
3492 {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0, "TCP_UTCL1_LFIFO_PROBE0"},
3493 {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1, "TCP_UTCL1_LFIFO_PROBE1"},
3494 {AMDGPU_GFX_TCP_CMD_FIFO, "TCP_CMD_FIFO"},
3495 };
3496
3497 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_td_mem_list[] = {
3498 {AMDGPU_GFX_TD_UTD_CS_FIFO_MEM, "TD_UTD_CS_FIFO_MEM"},
3499 {AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM, "TD_UTD_SS_FIFO_LO_MEM"},
3500 {AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM, "TD_UTD_SS_FIFO_HI_MEM"},
3501 };
3502
3503 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcx_mem_list[] = {
3504 {AMDGPU_GFX_TCX_FIFOD0, "TCX_FIFOD0"},
3505 {AMDGPU_GFX_TCX_FIFOD1, "TCX_FIFOD1"},
3506 {AMDGPU_GFX_TCX_FIFOD2, "TCX_FIFOD2"},
3507 {AMDGPU_GFX_TCX_FIFOD3, "TCX_FIFOD3"},
3508 {AMDGPU_GFX_TCX_FIFOD4, "TCX_FIFOD4"},
3509 {AMDGPU_GFX_TCX_FIFOD5, "TCX_FIFOD5"},
3510 {AMDGPU_GFX_TCX_FIFOD6, "TCX_FIFOD6"},
3511 {AMDGPU_GFX_TCX_FIFOD7, "TCX_FIFOD7"},
3512 {AMDGPU_GFX_TCX_FIFOB0, "TCX_FIFOB0"},
3513 {AMDGPU_GFX_TCX_FIFOB1, "TCX_FIFOB1"},
3514 {AMDGPU_GFX_TCX_FIFOB2, "TCX_FIFOB2"},
3515 {AMDGPU_GFX_TCX_FIFOB3, "TCX_FIFOB3"},
3516 {AMDGPU_GFX_TCX_FIFOB4, "TCX_FIFOB4"},
3517 {AMDGPU_GFX_TCX_FIFOB5, "TCX_FIFOB5"},
3518 {AMDGPU_GFX_TCX_FIFOB6, "TCX_FIFOB6"},
3519 {AMDGPU_GFX_TCX_FIFOB7, "TCX_FIFOB7"},
3520 {AMDGPU_GFX_TCX_FIFOA0, "TCX_FIFOA0"},
3521 {AMDGPU_GFX_TCX_FIFOA1, "TCX_FIFOA1"},
3522 {AMDGPU_GFX_TCX_FIFOA2, "TCX_FIFOA2"},
3523 {AMDGPU_GFX_TCX_FIFOA3, "TCX_FIFOA3"},
3524 {AMDGPU_GFX_TCX_FIFOA4, "TCX_FIFOA4"},
3525 {AMDGPU_GFX_TCX_FIFOA5, "TCX_FIFOA5"},
3526 {AMDGPU_GFX_TCX_FIFOA6, "TCX_FIFOA6"},
3527 {AMDGPU_GFX_TCX_FIFOA7, "TCX_FIFOA7"},
3528 {AMDGPU_GFX_TCX_CFIFO0, "TCX_CFIFO0"},
3529 {AMDGPU_GFX_TCX_CFIFO1, "TCX_CFIFO1"},
3530 {AMDGPU_GFX_TCX_CFIFO2, "TCX_CFIFO2"},
3531 {AMDGPU_GFX_TCX_CFIFO3, "TCX_CFIFO3"},
3532 {AMDGPU_GFX_TCX_CFIFO4, "TCX_CFIFO4"},
3533 {AMDGPU_GFX_TCX_CFIFO5, "TCX_CFIFO5"},
3534 {AMDGPU_GFX_TCX_CFIFO6, "TCX_CFIFO6"},
3535 {AMDGPU_GFX_TCX_CFIFO7, "TCX_CFIFO7"},
3536 {AMDGPU_GFX_TCX_FIFO_ACKB0, "TCX_FIFO_ACKB0"},
3537 {AMDGPU_GFX_TCX_FIFO_ACKB1, "TCX_FIFO_ACKB1"},
3538 {AMDGPU_GFX_TCX_FIFO_ACKB2, "TCX_FIFO_ACKB2"},
3539 {AMDGPU_GFX_TCX_FIFO_ACKB3, "TCX_FIFO_ACKB3"},
3540 {AMDGPU_GFX_TCX_FIFO_ACKB4, "TCX_FIFO_ACKB4"},
3541 {AMDGPU_GFX_TCX_FIFO_ACKB5, "TCX_FIFO_ACKB5"},
3542 {AMDGPU_GFX_TCX_FIFO_ACKB6, "TCX_FIFO_ACKB6"},
3543 {AMDGPU_GFX_TCX_FIFO_ACKB7, "TCX_FIFO_ACKB7"},
3544 {AMDGPU_GFX_TCX_FIFO_ACKD0, "TCX_FIFO_ACKD0"},
3545 {AMDGPU_GFX_TCX_FIFO_ACKD1, "TCX_FIFO_ACKD1"},
3546 {AMDGPU_GFX_TCX_FIFO_ACKD2, "TCX_FIFO_ACKD2"},
3547 {AMDGPU_GFX_TCX_FIFO_ACKD3, "TCX_FIFO_ACKD3"},
3548 {AMDGPU_GFX_TCX_FIFO_ACKD4, "TCX_FIFO_ACKD4"},
3549 {AMDGPU_GFX_TCX_FIFO_ACKD5, "TCX_FIFO_ACKD5"},
3550 {AMDGPU_GFX_TCX_FIFO_ACKD6, "TCX_FIFO_ACKD6"},
3551 {AMDGPU_GFX_TCX_FIFO_ACKD7, "TCX_FIFO_ACKD7"},
3552 {AMDGPU_GFX_TCX_DST_FIFOA0, "TCX_DST_FIFOA0"},
3553 {AMDGPU_GFX_TCX_DST_FIFOA1, "TCX_DST_FIFOA1"},
3554 {AMDGPU_GFX_TCX_DST_FIFOA2, "TCX_DST_FIFOA2"},
3555 {AMDGPU_GFX_TCX_DST_FIFOA3, "TCX_DST_FIFOA3"},
3556 {AMDGPU_GFX_TCX_DST_FIFOA4, "TCX_DST_FIFOA4"},
3557 {AMDGPU_GFX_TCX_DST_FIFOA5, "TCX_DST_FIFOA5"},
3558 {AMDGPU_GFX_TCX_DST_FIFOA6, "TCX_DST_FIFOA6"},
3559 {AMDGPU_GFX_TCX_DST_FIFOA7, "TCX_DST_FIFOA7"},
3560 {AMDGPU_GFX_TCX_DST_FIFOB0, "TCX_DST_FIFOB0"},
3561 {AMDGPU_GFX_TCX_DST_FIFOB1, "TCX_DST_FIFOB1"},
3562 {AMDGPU_GFX_TCX_DST_FIFOB2, "TCX_DST_FIFOB2"},
3563 {AMDGPU_GFX_TCX_DST_FIFOB3, "TCX_DST_FIFOB3"},
3564 {AMDGPU_GFX_TCX_DST_FIFOB4, "TCX_DST_FIFOB4"},
3565 {AMDGPU_GFX_TCX_DST_FIFOB5, "TCX_DST_FIFOB5"},
3566 {AMDGPU_GFX_TCX_DST_FIFOB6, "TCX_DST_FIFOB6"},
3567 {AMDGPU_GFX_TCX_DST_FIFOB7, "TCX_DST_FIFOB7"},
3568 {AMDGPU_GFX_TCX_DST_FIFOD0, "TCX_DST_FIFOD0"},
3569 {AMDGPU_GFX_TCX_DST_FIFOD1, "TCX_DST_FIFOD1"},
3570 {AMDGPU_GFX_TCX_DST_FIFOD2, "TCX_DST_FIFOD2"},
3571 {AMDGPU_GFX_TCX_DST_FIFOD3, "TCX_DST_FIFOD3"},
3572 {AMDGPU_GFX_TCX_DST_FIFOD4, "TCX_DST_FIFOD4"},
3573 {AMDGPU_GFX_TCX_DST_FIFOD5, "TCX_DST_FIFOD5"},
3574 {AMDGPU_GFX_TCX_DST_FIFOD6, "TCX_DST_FIFOD6"},
3575 {AMDGPU_GFX_TCX_DST_FIFOD7, "TCX_DST_FIFOD7"},
3576 {AMDGPU_GFX_TCX_DST_FIFO_ACKB0, "TCX_DST_FIFO_ACKB0"},
3577 {AMDGPU_GFX_TCX_DST_FIFO_ACKB1, "TCX_DST_FIFO_ACKB1"},
3578 {AMDGPU_GFX_TCX_DST_FIFO_ACKB2, "TCX_DST_FIFO_ACKB2"},
3579 {AMDGPU_GFX_TCX_DST_FIFO_ACKB3, "TCX_DST_FIFO_ACKB3"},
3580 {AMDGPU_GFX_TCX_DST_FIFO_ACKB4, "TCX_DST_FIFO_ACKB4"},
3581 {AMDGPU_GFX_TCX_DST_FIFO_ACKB5, "TCX_DST_FIFO_ACKB5"},
3582 {AMDGPU_GFX_TCX_DST_FIFO_ACKB6, "TCX_DST_FIFO_ACKB6"},
3583 {AMDGPU_GFX_TCX_DST_FIFO_ACKB7, "TCX_DST_FIFO_ACKB7"},
3584 {AMDGPU_GFX_TCX_DST_FIFO_ACKD0, "TCX_DST_FIFO_ACKD0"},
3585 {AMDGPU_GFX_TCX_DST_FIFO_ACKD1, "TCX_DST_FIFO_ACKD1"},
3586 {AMDGPU_GFX_TCX_DST_FIFO_ACKD2, "TCX_DST_FIFO_ACKD2"},
3587 {AMDGPU_GFX_TCX_DST_FIFO_ACKD3, "TCX_DST_FIFO_ACKD3"},
3588 {AMDGPU_GFX_TCX_DST_FIFO_ACKD4, "TCX_DST_FIFO_ACKD4"},
3589 {AMDGPU_GFX_TCX_DST_FIFO_ACKD5, "TCX_DST_FIFO_ACKD5"},
3590 {AMDGPU_GFX_TCX_DST_FIFO_ACKD6, "TCX_DST_FIFO_ACKD6"},
3591 {AMDGPU_GFX_TCX_DST_FIFO_ACKD7, "TCX_DST_FIFO_ACKD7"},
3592 };
3593
3594 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_atc_l2_mem_list[] = {
3595 {AMDGPU_GFX_ATC_L2_MEM, "ATC_L2_MEM"},
3596 };
3597
3598 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_utcl2_mem_list[] = {
3599 {AMDGPU_GFX_UTCL2_MEM, "UTCL2_MEM"},
3600 };
3601
3602 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_mem_list[] = {
3603 {AMDGPU_GFX_VML2_MEM, "VML2_MEM"},
3604 };
3605
3606 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_walker_mem_list[] = {
3607 {AMDGPU_GFX_VML2_WALKER_MEM, "VML2_WALKER_MEM"},
3608 };
3609
3610 static const struct amdgpu_gfx_ras_mem_id_entry gfx_v9_4_3_ras_mem_list_array[AMDGPU_GFX_MEM_TYPE_NUM] = {
3611 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_cp_mem_list)
3612 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcea_mem_list)
3613 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gc_cane_mem_list)
3614 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcutcl2_mem_list)
3615 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gds_mem_list)
3616 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_lds_mem_list)
3617 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_rlc_mem_list)
3618 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sp_mem_list)
3619 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_spi_mem_list)
3620 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sqc_mem_list)
3621 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sq_mem_list)
3622 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_ta_mem_list)
3623 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcc_mem_list)
3624 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tca_mem_list)
3625 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tci_mem_list)
3626 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcp_mem_list)
3627 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_td_mem_list)
3628 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcx_mem_list)
3629 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_atc_l2_mem_list)
3630 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_utcl2_mem_list)
3631 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_mem_list)
3632 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_walker_mem_list)
3633 };
3634
3635 static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ce_reg_list[] = {
3636 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_CE_ERR_STATUS_LOW, regRLC_CE_ERR_STATUS_HIGH),
3637 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"},
3638 AMDGPU_GFX_RLC_MEM, 1},
3639 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_CE_ERR_STATUS_LO, regCPC_CE_ERR_STATUS_HI),
3640 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"},
3641 AMDGPU_GFX_CP_MEM, 1},
3642 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_CE_ERR_STATUS_LO, regCPF_CE_ERR_STATUS_HI),
3643 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"},
3644 AMDGPU_GFX_CP_MEM, 1},
3645 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_CE_ERR_STATUS_LO, regCPG_CE_ERR_STATUS_HI),
3646 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"},
3647 AMDGPU_GFX_CP_MEM, 1},
3648 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_CE_ERR_STATUS_LO, regGDS_CE_ERR_STATUS_HI),
3649 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"},
3650 AMDGPU_GFX_GDS_MEM, 1},
3651 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_CE_ERR_STATUS_LO, regGC_CANE_CE_ERR_STATUS_HI),
3652 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"},
3653 AMDGPU_GFX_GC_CANE_MEM, 1},
3654 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_CE_ERR_STATUS_LO, regSPI_CE_ERR_STATUS_HI),
3655 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"},
3656 AMDGPU_GFX_SPI_MEM, 8},
3657 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_CE_ERR_STATUS_LO, regSP0_CE_ERR_STATUS_HI),
3658 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"},
3659 AMDGPU_GFX_SP_MEM, 1},
3660 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_CE_ERR_STATUS_LO, regSP1_CE_ERR_STATUS_HI),
3661 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"},
3662 AMDGPU_GFX_SP_MEM, 1},
3663 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_CE_ERR_STATUS_LO, regSQ_CE_ERR_STATUS_HI),
3664 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"},
3665 AMDGPU_GFX_SQ_MEM, 8},
3666 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_CE_EDC_LO, regSQC_CE_EDC_HI),
3667 5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"},
3668 AMDGPU_GFX_SQC_MEM, 8},
3669 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_CE_ERR_STATUS_LO, regTCX_CE_ERR_STATUS_HI),
3670 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"},
3671 AMDGPU_GFX_TCX_MEM, 1},
3672 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_CE_ERR_STATUS_LO, regTCC_CE_ERR_STATUS_HI),
3673 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"},
3674 AMDGPU_GFX_TCC_MEM, 1},
3675 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_CE_EDC_LO, regTA_CE_EDC_HI),
3676 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"},
3677 AMDGPU_GFX_TA_MEM, 8},
3678 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_CE_EDC_LO_REG, regTCI_CE_EDC_HI_REG),
3679 31, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"},
3680 AMDGPU_GFX_TCI_MEM, 1},
3681 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_CE_EDC_LO_REG, regTCP_CE_EDC_HI_REG),
3682 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"},
3683 AMDGPU_GFX_TCP_MEM, 8},
3684 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_CE_EDC_LO, regTD_CE_EDC_HI),
3685 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"},
3686 AMDGPU_GFX_TD_MEM, 8},
3687 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_CE_ERR_STATUS_LO, regGCEA_CE_ERR_STATUS_HI),
3688 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"},
3689 AMDGPU_GFX_GCEA_MEM, 1},
3690 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_CE_ERR_STATUS_LO, regLDS_CE_ERR_STATUS_HI),
3691 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"},
3692 AMDGPU_GFX_LDS_MEM, 1},
3693 };
3694
3695 static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ue_reg_list[] = {
3696 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_UE_ERR_STATUS_LOW, regRLC_UE_ERR_STATUS_HIGH),
3697 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"},
3698 AMDGPU_GFX_RLC_MEM, 1},
3699 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_UE_ERR_STATUS_LO, regCPC_UE_ERR_STATUS_HI),
3700 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"},
3701 AMDGPU_GFX_CP_MEM, 1},
3702 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_UE_ERR_STATUS_LO, regCPF_UE_ERR_STATUS_HI),
3703 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"},
3704 AMDGPU_GFX_CP_MEM, 1},
3705 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_UE_ERR_STATUS_LO, regCPG_UE_ERR_STATUS_HI),
3706 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"},
3707 AMDGPU_GFX_CP_MEM, 1},
3708 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_UE_ERR_STATUS_LO, regGDS_UE_ERR_STATUS_HI),
3709 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"},
3710 AMDGPU_GFX_GDS_MEM, 1},
3711 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_UE_ERR_STATUS_LO, regGC_CANE_UE_ERR_STATUS_HI),
3712 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"},
3713 AMDGPU_GFX_GC_CANE_MEM, 1},
3714 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_UE_ERR_STATUS_LO, regSPI_UE_ERR_STATUS_HI),
3715 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"},
3716 AMDGPU_GFX_SPI_MEM, 8},
3717 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_UE_ERR_STATUS_LO, regSP0_UE_ERR_STATUS_HI),
3718 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"},
3719 AMDGPU_GFX_SP_MEM, 1},
3720 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_UE_ERR_STATUS_LO, regSP1_UE_ERR_STATUS_HI),
3721 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"},
3722 AMDGPU_GFX_SP_MEM, 1},
3723 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_UE_ERR_STATUS_LO, regSQ_UE_ERR_STATUS_HI),
3724 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"},
3725 AMDGPU_GFX_SQ_MEM, 8},
3726 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_UE_EDC_LO, regSQC_UE_EDC_HI),
3727 5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"},
3728 AMDGPU_GFX_SQC_MEM, 8},
3729 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_UE_ERR_STATUS_LO, regTCX_UE_ERR_STATUS_HI),
3730 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"},
3731 AMDGPU_GFX_TCX_MEM, 1},
3732 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_UE_ERR_STATUS_LO, regTCC_UE_ERR_STATUS_HI),
3733 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"},
3734 AMDGPU_GFX_TCC_MEM, 1},
3735 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_UE_EDC_LO, regTA_UE_EDC_HI),
3736 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"},
3737 AMDGPU_GFX_TA_MEM, 8},
3738 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_UE_EDC_LO_REG, regTCI_UE_EDC_HI_REG),
3739 31, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"},
3740 AMDGPU_GFX_TCI_MEM, 1},
3741 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_UE_EDC_LO_REG, regTCP_UE_EDC_HI_REG),
3742 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"},
3743 AMDGPU_GFX_TCP_MEM, 8},
3744 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_UE_EDC_LO, regTD_UE_EDC_HI),
3745 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"},
3746 AMDGPU_GFX_TD_MEM, 8},
3747 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCA_UE_ERR_STATUS_LO, regTCA_UE_ERR_STATUS_HI),
3748 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCA"},
3749 AMDGPU_GFX_TCA_MEM, 1},
3750 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_UE_ERR_STATUS_LO, regGCEA_UE_ERR_STATUS_HI),
3751 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"},
3752 AMDGPU_GFX_GCEA_MEM, 1},
3753 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_UE_ERR_STATUS_LO, regLDS_UE_ERR_STATUS_HI),
3754 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"},
3755 AMDGPU_GFX_LDS_MEM, 1},
3756 };
3757
3758 static const struct soc15_reg_entry gfx_v9_4_3_ea_err_status_regs = {
3759 SOC15_REG_ENTRY(GC, 0, regGCEA_ERR_STATUS), 0, 1, 16
3760 };
3761
gfx_v9_4_3_inst_query_ras_err_count(struct amdgpu_device * adev,void * ras_error_status,int xcc_id)3762 static void gfx_v9_4_3_inst_query_ras_err_count(struct amdgpu_device *adev,
3763 void *ras_error_status, int xcc_id)
3764 {
3765 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
3766 unsigned long ce_count = 0, ue_count = 0;
3767 uint32_t i, j, k;
3768
3769 mutex_lock(&adev->grbm_idx_mutex);
3770
3771 for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) {
3772 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) {
3773 for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) {
3774 /* no need to select if instance number is 1 */
3775 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 ||
3776 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1)
3777 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id);
3778
3779 amdgpu_ras_inst_query_ras_error_count(adev,
3780 &(gfx_v9_4_3_ce_reg_list[i].reg_entry),
3781 1,
3782 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].mem_id_ent,
3783 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].size,
3784 GET_INST(GC, xcc_id),
3785 AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE,
3786 &ce_count);
3787
3788 amdgpu_ras_inst_query_ras_error_count(adev,
3789 &(gfx_v9_4_3_ue_reg_list[i].reg_entry),
3790 1,
3791 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].mem_id_ent,
3792 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].size,
3793 GET_INST(GC, xcc_id),
3794 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
3795 &ue_count);
3796 }
3797 }
3798 }
3799
3800 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff,
3801 xcc_id);
3802 mutex_unlock(&adev->grbm_idx_mutex);
3803
3804 /* the caller should make sure initialize value of
3805 * err_data->ue_count and err_data->ce_count
3806 */
3807 err_data->ce_count += ce_count;
3808 err_data->ue_count += ue_count;
3809 }
3810
gfx_v9_4_3_inst_reset_ras_err_count(struct amdgpu_device * adev,void * ras_error_status,int xcc_id)3811 static void gfx_v9_4_3_inst_reset_ras_err_count(struct amdgpu_device *adev,
3812 void *ras_error_status, int xcc_id)
3813 {
3814 uint32_t i, j, k;
3815
3816 mutex_lock(&adev->grbm_idx_mutex);
3817
3818 for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) {
3819 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) {
3820 for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) {
3821 /* no need to select if instance number is 1 */
3822 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 ||
3823 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1)
3824 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id);
3825
3826 amdgpu_ras_inst_reset_ras_error_count(adev,
3827 &(gfx_v9_4_3_ce_reg_list[i].reg_entry),
3828 1,
3829 GET_INST(GC, xcc_id));
3830
3831 amdgpu_ras_inst_reset_ras_error_count(adev,
3832 &(gfx_v9_4_3_ue_reg_list[i].reg_entry),
3833 1,
3834 GET_INST(GC, xcc_id));
3835 }
3836 }
3837 }
3838
3839 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff,
3840 xcc_id);
3841 mutex_unlock(&adev->grbm_idx_mutex);
3842 }
3843
gfx_v9_4_3_inst_query_ea_err_status(struct amdgpu_device * adev,int xcc_id)3844 static void gfx_v9_4_3_inst_query_ea_err_status(struct amdgpu_device *adev,
3845 int xcc_id)
3846 {
3847 uint32_t i, j;
3848 uint32_t reg_value;
3849
3850 mutex_lock(&adev->grbm_idx_mutex);
3851
3852 for (i = 0; i < gfx_v9_4_3_ea_err_status_regs.se_num; i++) {
3853 for (j = 0; j < gfx_v9_4_3_ea_err_status_regs.instance; j++) {
3854 gfx_v9_4_3_xcc_select_se_sh(adev, i, 0, j, xcc_id);
3855 reg_value = RREG32_SOC15(GC, GET_INST(GC, xcc_id),
3856 regGCEA_ERR_STATUS);
3857 if (REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_RDRSP_STATUS) ||
3858 REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_WRRSP_STATUS) ||
3859 REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_RDRSP_DATAPARITY_ERROR)) {
3860 dev_warn(adev->dev,
3861 "GCEA err detected at instance: %d, status: 0x%x!\n",
3862 j, reg_value);
3863 }
3864 /* clear after read */
3865 reg_value = REG_SET_FIELD(reg_value, GCEA_ERR_STATUS,
3866 CLEAR_ERROR_STATUS, 0x1);
3867 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGCEA_ERR_STATUS,
3868 reg_value);
3869 }
3870 }
3871
3872 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff,
3873 xcc_id);
3874 mutex_unlock(&adev->grbm_idx_mutex);
3875 }
3876
gfx_v9_4_3_inst_query_utc_err_status(struct amdgpu_device * adev,int xcc_id)3877 static void gfx_v9_4_3_inst_query_utc_err_status(struct amdgpu_device *adev,
3878 int xcc_id)
3879 {
3880 uint32_t data;
3881
3882 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regUTCL2_MEM_ECC_STATUS);
3883 if (data) {
3884 dev_warn(adev->dev, "GFX UTCL2 Mem Ecc Status: 0x%x!\n", data);
3885 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regUTCL2_MEM_ECC_STATUS, 0x3);
3886 }
3887
3888 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regVML2_MEM_ECC_STATUS);
3889 if (data) {
3890 dev_warn(adev->dev, "GFX VML2 Mem Ecc Status: 0x%x!\n", data);
3891 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regVML2_MEM_ECC_STATUS, 0x3);
3892 }
3893
3894 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id),
3895 regVML2_WALKER_MEM_ECC_STATUS);
3896 if (data) {
3897 dev_warn(adev->dev, "GFX VML2 Walker Mem Ecc Status: 0x%x!\n", data);
3898 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regVML2_WALKER_MEM_ECC_STATUS,
3899 0x3);
3900 }
3901 }
3902
gfx_v9_4_3_log_cu_timeout_status(struct amdgpu_device * adev,uint32_t status,int xcc_id)3903 static void gfx_v9_4_3_log_cu_timeout_status(struct amdgpu_device *adev,
3904 uint32_t status, int xcc_id)
3905 {
3906 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
3907 uint32_t i, simd, wave;
3908 uint32_t wave_status;
3909 uint32_t wave_pc_lo, wave_pc_hi;
3910 uint32_t wave_exec_lo, wave_exec_hi;
3911 uint32_t wave_inst_dw0, wave_inst_dw1;
3912 uint32_t wave_ib_sts;
3913
3914 for (i = 0; i < 32; i++) {
3915 if (!((i << 1) & status))
3916 continue;
3917
3918 simd = i / cu_info->max_waves_per_simd;
3919 wave = i % cu_info->max_waves_per_simd;
3920
3921 wave_status = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_STATUS);
3922 wave_pc_lo = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_LO);
3923 wave_pc_hi = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_HI);
3924 wave_exec_lo =
3925 wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_LO);
3926 wave_exec_hi =
3927 wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_HI);
3928 wave_inst_dw0 =
3929 wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW0);
3930 wave_inst_dw1 =
3931 wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW1);
3932 wave_ib_sts = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_STS);
3933
3934 dev_info(
3935 adev->dev,
3936 "\t SIMD %d, Wave %d: status 0x%x, pc 0x%llx, exec 0x%llx, inst 0x%llx, ib_sts 0x%x\n",
3937 simd, wave, wave_status,
3938 ((uint64_t)wave_pc_hi << 32 | wave_pc_lo),
3939 ((uint64_t)wave_exec_hi << 32 | wave_exec_lo),
3940 ((uint64_t)wave_inst_dw1 << 32 | wave_inst_dw0),
3941 wave_ib_sts);
3942 }
3943 }
3944
gfx_v9_4_3_inst_query_sq_timeout_status(struct amdgpu_device * adev,int xcc_id)3945 static void gfx_v9_4_3_inst_query_sq_timeout_status(struct amdgpu_device *adev,
3946 int xcc_id)
3947 {
3948 uint32_t se_idx, sh_idx, cu_idx;
3949 uint32_t status;
3950
3951 mutex_lock(&adev->grbm_idx_mutex);
3952 for (se_idx = 0; se_idx < adev->gfx.config.max_shader_engines; se_idx++) {
3953 for (sh_idx = 0; sh_idx < adev->gfx.config.max_sh_per_se; sh_idx++) {
3954 for (cu_idx = 0; cu_idx < adev->gfx.config.max_cu_per_sh; cu_idx++) {
3955 gfx_v9_4_3_xcc_select_se_sh(adev, se_idx, sh_idx,
3956 cu_idx, xcc_id);
3957 status = RREG32_SOC15(GC, GET_INST(GC, xcc_id),
3958 regSQ_TIMEOUT_STATUS);
3959 if (status != 0) {
3960 dev_info(
3961 adev->dev,
3962 "GFX Watchdog Timeout: SE %d, SH %d, CU %d\n",
3963 se_idx, sh_idx, cu_idx);
3964 gfx_v9_4_3_log_cu_timeout_status(
3965 adev, status, xcc_id);
3966 }
3967 /* clear old status */
3968 WREG32_SOC15(GC, GET_INST(GC, xcc_id),
3969 regSQ_TIMEOUT_STATUS, 0);
3970 }
3971 }
3972 }
3973 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff,
3974 xcc_id);
3975 mutex_unlock(&adev->grbm_idx_mutex);
3976 }
3977
gfx_v9_4_3_inst_query_ras_err_status(struct amdgpu_device * adev,void * ras_error_status,int xcc_id)3978 static void gfx_v9_4_3_inst_query_ras_err_status(struct amdgpu_device *adev,
3979 void *ras_error_status, int xcc_id)
3980 {
3981 gfx_v9_4_3_inst_query_ea_err_status(adev, xcc_id);
3982 gfx_v9_4_3_inst_query_utc_err_status(adev, xcc_id);
3983 gfx_v9_4_3_inst_query_sq_timeout_status(adev, xcc_id);
3984 }
3985
gfx_v9_4_3_inst_reset_utc_err_status(struct amdgpu_device * adev,int xcc_id)3986 static void gfx_v9_4_3_inst_reset_utc_err_status(struct amdgpu_device *adev,
3987 int xcc_id)
3988 {
3989 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regUTCL2_MEM_ECC_STATUS, 0x3);
3990 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regVML2_MEM_ECC_STATUS, 0x3);
3991 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regVML2_WALKER_MEM_ECC_STATUS, 0x3);
3992 }
3993
gfx_v9_4_3_inst_reset_ea_err_status(struct amdgpu_device * adev,int xcc_id)3994 static void gfx_v9_4_3_inst_reset_ea_err_status(struct amdgpu_device *adev,
3995 int xcc_id)
3996 {
3997 uint32_t i, j;
3998 uint32_t value;
3999
4000 mutex_lock(&adev->grbm_idx_mutex);
4001 for (i = 0; i < gfx_v9_4_3_ea_err_status_regs.se_num; i++) {
4002 for (j = 0; j < gfx_v9_4_3_ea_err_status_regs.instance; j++) {
4003 gfx_v9_4_3_xcc_select_se_sh(adev, i, 0, j, xcc_id);
4004 value = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regGCEA_ERR_STATUS);
4005 value = REG_SET_FIELD(value, GCEA_ERR_STATUS,
4006 CLEAR_ERROR_STATUS, 0x1);
4007 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGCEA_ERR_STATUS, value);
4008 }
4009 }
4010 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff,
4011 xcc_id);
4012 mutex_unlock(&adev->grbm_idx_mutex);
4013 }
4014
gfx_v9_4_3_inst_reset_sq_timeout_status(struct amdgpu_device * adev,int xcc_id)4015 static void gfx_v9_4_3_inst_reset_sq_timeout_status(struct amdgpu_device *adev,
4016 int xcc_id)
4017 {
4018 uint32_t se_idx, sh_idx, cu_idx;
4019
4020 mutex_lock(&adev->grbm_idx_mutex);
4021 for (se_idx = 0; se_idx < adev->gfx.config.max_shader_engines; se_idx++) {
4022 for (sh_idx = 0; sh_idx < adev->gfx.config.max_sh_per_se; sh_idx++) {
4023 for (cu_idx = 0; cu_idx < adev->gfx.config.max_cu_per_sh; cu_idx++) {
4024 gfx_v9_4_3_xcc_select_se_sh(adev, se_idx, sh_idx,
4025 cu_idx, xcc_id);
4026 WREG32_SOC15(GC, GET_INST(GC, xcc_id),
4027 regSQ_TIMEOUT_STATUS, 0);
4028 }
4029 }
4030 }
4031 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff,
4032 xcc_id);
4033 mutex_unlock(&adev->grbm_idx_mutex);
4034 }
4035
gfx_v9_4_3_inst_reset_ras_err_status(struct amdgpu_device * adev,void * ras_error_status,int xcc_id)4036 static void gfx_v9_4_3_inst_reset_ras_err_status(struct amdgpu_device *adev,
4037 void *ras_error_status, int xcc_id)
4038 {
4039 gfx_v9_4_3_inst_reset_utc_err_status(adev, xcc_id);
4040 gfx_v9_4_3_inst_reset_ea_err_status(adev, xcc_id);
4041 gfx_v9_4_3_inst_reset_sq_timeout_status(adev, xcc_id);
4042 }
4043
gfx_v9_4_3_inst_enable_watchdog_timer(struct amdgpu_device * adev,void * ras_error_status,int xcc_id)4044 static void gfx_v9_4_3_inst_enable_watchdog_timer(struct amdgpu_device *adev,
4045 void *ras_error_status, int xcc_id)
4046 {
4047 uint32_t i;
4048 uint32_t data;
4049
4050 data = RREG32_SOC15(GC, GET_INST(GC, 0), regSQ_TIMEOUT_CONFIG);
4051 data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, TIMEOUT_FATAL_DISABLE,
4052 amdgpu_watchdog_timer.timeout_fatal_disable ? 1 : 0);
4053
4054 if (amdgpu_watchdog_timer.timeout_fatal_disable &&
4055 (amdgpu_watchdog_timer.period < 1 ||
4056 amdgpu_watchdog_timer.period > 0x23)) {
4057 dev_warn(adev->dev, "Watchdog period range is 1 to 0x23\n");
4058 amdgpu_watchdog_timer.period = 0x23;
4059 }
4060 data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, PERIOD_SEL,
4061 amdgpu_watchdog_timer.period);
4062
4063 mutex_lock(&adev->grbm_idx_mutex);
4064 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4065 gfx_v9_4_3_xcc_select_se_sh(adev, i, 0xffffffff, 0xffffffff, xcc_id);
4066 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_TIMEOUT_CONFIG, data);
4067 }
4068 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff,
4069 xcc_id);
4070 mutex_unlock(&adev->grbm_idx_mutex);
4071 }
4072
gfx_v9_4_3_query_ras_error_count(struct amdgpu_device * adev,void * ras_error_status)4073 static void gfx_v9_4_3_query_ras_error_count(struct amdgpu_device *adev,
4074 void *ras_error_status)
4075 {
4076 amdgpu_gfx_ras_error_func(adev, ras_error_status,
4077 gfx_v9_4_3_inst_query_ras_err_count);
4078 }
4079
gfx_v9_4_3_reset_ras_error_count(struct amdgpu_device * adev)4080 static void gfx_v9_4_3_reset_ras_error_count(struct amdgpu_device *adev)
4081 {
4082 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_reset_ras_err_count);
4083 }
4084
gfx_v9_4_3_query_ras_error_status(struct amdgpu_device * adev)4085 static void gfx_v9_4_3_query_ras_error_status(struct amdgpu_device *adev)
4086 {
4087 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_query_ras_err_status);
4088 }
4089
gfx_v9_4_3_reset_ras_error_status(struct amdgpu_device * adev)4090 static void gfx_v9_4_3_reset_ras_error_status(struct amdgpu_device *adev)
4091 {
4092 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_reset_ras_err_status);
4093 }
4094
gfx_v9_4_3_enable_watchdog_timer(struct amdgpu_device * adev)4095 static void gfx_v9_4_3_enable_watchdog_timer(struct amdgpu_device *adev)
4096 {
4097 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_enable_watchdog_timer);
4098 }
4099
4100 static const struct amd_ip_funcs gfx_v9_4_3_ip_funcs = {
4101 .name = "gfx_v9_4_3",
4102 .early_init = gfx_v9_4_3_early_init,
4103 .late_init = gfx_v9_4_3_late_init,
4104 .sw_init = gfx_v9_4_3_sw_init,
4105 .sw_fini = gfx_v9_4_3_sw_fini,
4106 .hw_init = gfx_v9_4_3_hw_init,
4107 .hw_fini = gfx_v9_4_3_hw_fini,
4108 .suspend = gfx_v9_4_3_suspend,
4109 .resume = gfx_v9_4_3_resume,
4110 .is_idle = gfx_v9_4_3_is_idle,
4111 .wait_for_idle = gfx_v9_4_3_wait_for_idle,
4112 .soft_reset = gfx_v9_4_3_soft_reset,
4113 .set_clockgating_state = gfx_v9_4_3_set_clockgating_state,
4114 .set_powergating_state = gfx_v9_4_3_set_powergating_state,
4115 .get_clockgating_state = gfx_v9_4_3_get_clockgating_state,
4116 };
4117
4118 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_compute = {
4119 .type = AMDGPU_RING_TYPE_COMPUTE,
4120 .align_mask = 0xff,
4121 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4122 .support_64bit_ptrs = true,
4123 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute,
4124 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute,
4125 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute,
4126 .emit_frame_size =
4127 20 + /* gfx_v9_4_3_ring_emit_gds_switch */
4128 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */
4129 5 + /* hdp invalidate */
4130 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */
4131 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
4132 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
4133 2 + /* gfx_v9_4_3_ring_emit_vm_flush */
4134 8 + 8 + 8 + /* gfx_v9_4_3_ring_emit_fence x3 for user fence, vm fence */
4135 7 + /* gfx_v9_4_3_emit_mem_sync */
4136 5 + /* gfx_v9_4_3_emit_wave_limit for updating regSPI_WCL_PIPE_PERCENT_GFX register */
4137 15, /* for updating 3 regSPI_WCL_PIPE_PERCENT_CS registers */
4138 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */
4139 .emit_ib = gfx_v9_4_3_ring_emit_ib_compute,
4140 .emit_fence = gfx_v9_4_3_ring_emit_fence,
4141 .emit_pipeline_sync = gfx_v9_4_3_ring_emit_pipeline_sync,
4142 .emit_vm_flush = gfx_v9_4_3_ring_emit_vm_flush,
4143 .emit_gds_switch = gfx_v9_4_3_ring_emit_gds_switch,
4144 .emit_hdp_flush = gfx_v9_4_3_ring_emit_hdp_flush,
4145 .test_ring = gfx_v9_4_3_ring_test_ring,
4146 .test_ib = gfx_v9_4_3_ring_test_ib,
4147 .insert_nop = amdgpu_ring_insert_nop,
4148 .pad_ib = amdgpu_ring_generic_pad_ib,
4149 .emit_wreg = gfx_v9_4_3_ring_emit_wreg,
4150 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait,
4151 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait,
4152 .emit_mem_sync = gfx_v9_4_3_emit_mem_sync,
4153 .emit_wave_limit = gfx_v9_4_3_emit_wave_limit,
4154 };
4155
4156 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_kiq = {
4157 .type = AMDGPU_RING_TYPE_KIQ,
4158 .align_mask = 0xff,
4159 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4160 .support_64bit_ptrs = true,
4161 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute,
4162 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute,
4163 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute,
4164 .emit_frame_size =
4165 20 + /* gfx_v9_4_3_ring_emit_gds_switch */
4166 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */
4167 5 + /* hdp invalidate */
4168 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */
4169 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
4170 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
4171 2 + /* gfx_v9_4_3_ring_emit_vm_flush */
4172 8 + 8 + 8, /* gfx_v9_4_3_ring_emit_fence_kiq x3 for user fence, vm fence */
4173 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */
4174 .emit_fence = gfx_v9_4_3_ring_emit_fence_kiq,
4175 .test_ring = gfx_v9_4_3_ring_test_ring,
4176 .insert_nop = amdgpu_ring_insert_nop,
4177 .pad_ib = amdgpu_ring_generic_pad_ib,
4178 .emit_rreg = gfx_v9_4_3_ring_emit_rreg,
4179 .emit_wreg = gfx_v9_4_3_ring_emit_wreg,
4180 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait,
4181 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait,
4182 };
4183
gfx_v9_4_3_set_ring_funcs(struct amdgpu_device * adev)4184 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev)
4185 {
4186 int i, j, num_xcc;
4187
4188 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
4189 for (i = 0; i < num_xcc; i++) {
4190 adev->gfx.kiq[i].ring.funcs = &gfx_v9_4_3_ring_funcs_kiq;
4191
4192 for (j = 0; j < adev->gfx.num_compute_rings; j++)
4193 adev->gfx.compute_ring[j + i * adev->gfx.num_compute_rings].funcs
4194 = &gfx_v9_4_3_ring_funcs_compute;
4195 }
4196 }
4197
4198 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_eop_irq_funcs = {
4199 .set = gfx_v9_4_3_set_eop_interrupt_state,
4200 .process = gfx_v9_4_3_eop_irq,
4201 };
4202
4203 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_reg_irq_funcs = {
4204 .set = gfx_v9_4_3_set_priv_reg_fault_state,
4205 .process = gfx_v9_4_3_priv_reg_irq,
4206 };
4207
4208 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_inst_irq_funcs = {
4209 .set = gfx_v9_4_3_set_priv_inst_fault_state,
4210 .process = gfx_v9_4_3_priv_inst_irq,
4211 };
4212
gfx_v9_4_3_set_irq_funcs(struct amdgpu_device * adev)4213 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev)
4214 {
4215 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
4216 adev->gfx.eop_irq.funcs = &gfx_v9_4_3_eop_irq_funcs;
4217
4218 adev->gfx.priv_reg_irq.num_types = 1;
4219 adev->gfx.priv_reg_irq.funcs = &gfx_v9_4_3_priv_reg_irq_funcs;
4220
4221 adev->gfx.priv_inst_irq.num_types = 1;
4222 adev->gfx.priv_inst_irq.funcs = &gfx_v9_4_3_priv_inst_irq_funcs;
4223 }
4224
gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device * adev)4225 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev)
4226 {
4227 adev->gfx.rlc.funcs = &gfx_v9_4_3_rlc_funcs;
4228 }
4229
4230
gfx_v9_4_3_set_gds_init(struct amdgpu_device * adev)4231 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev)
4232 {
4233 /* init asci gds info */
4234 switch (adev->ip_versions[GC_HWIP][0]) {
4235 case IP_VERSION(9, 4, 3):
4236 /* 9.4.3 removed all the GDS internal memory,
4237 * only support GWS opcode in kernel, like barrier
4238 * semaphore.etc */
4239 adev->gds.gds_size = 0;
4240 break;
4241 default:
4242 adev->gds.gds_size = 0x10000;
4243 break;
4244 }
4245
4246 switch (adev->ip_versions[GC_HWIP][0]) {
4247 case IP_VERSION(9, 4, 3):
4248 /* deprecated for 9.4.3, no usage at all */
4249 adev->gds.gds_compute_max_wave_id = 0;
4250 break;
4251 default:
4252 /* this really depends on the chip */
4253 adev->gds.gds_compute_max_wave_id = 0x7ff;
4254 break;
4255 }
4256
4257 adev->gds.gws_size = 64;
4258 adev->gds.oa_size = 16;
4259 }
4260
gfx_v9_4_3_set_user_cu_inactive_bitmap(struct amdgpu_device * adev,u32 bitmap,int xcc_id)4261 static void gfx_v9_4_3_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
4262 u32 bitmap, int xcc_id)
4263 {
4264 u32 data;
4265
4266 if (!bitmap)
4267 return;
4268
4269 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4270 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4271
4272 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG, data);
4273 }
4274
gfx_v9_4_3_get_cu_active_bitmap(struct amdgpu_device * adev,int xcc_id)4275 static u32 gfx_v9_4_3_get_cu_active_bitmap(struct amdgpu_device *adev, int xcc_id)
4276 {
4277 u32 data, mask;
4278
4279 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCC_GC_SHADER_ARRAY_CONFIG);
4280 data |= RREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG);
4281
4282 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4283 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4284
4285 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
4286
4287 return (~data) & mask;
4288 }
4289
gfx_v9_4_3_get_cu_info(struct amdgpu_device * adev,struct amdgpu_cu_info * cu_info)4290 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev,
4291 struct amdgpu_cu_info *cu_info)
4292 {
4293 int i, j, k, counter, xcc_id, active_cu_number = 0;
4294 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
4295 unsigned disable_masks[4 * 4];
4296
4297 if (!adev || !cu_info)
4298 return -EINVAL;
4299
4300 /*
4301 * 16 comes from bitmap array size 4*4, and it can cover all gfx9 ASICs
4302 */
4303 if (adev->gfx.config.max_shader_engines *
4304 adev->gfx.config.max_sh_per_se > 16)
4305 return -EINVAL;
4306
4307 amdgpu_gfx_parse_disable_cu(disable_masks,
4308 adev->gfx.config.max_shader_engines,
4309 adev->gfx.config.max_sh_per_se);
4310
4311 mutex_lock(&adev->grbm_idx_mutex);
4312 for (xcc_id = 0; xcc_id < NUM_XCC(adev->gfx.xcc_mask); xcc_id++) {
4313 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4314 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4315 mask = 1;
4316 ao_bitmap = 0;
4317 counter = 0;
4318 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, xcc_id);
4319 gfx_v9_4_3_set_user_cu_inactive_bitmap(
4320 adev,
4321 disable_masks[i * adev->gfx.config.max_sh_per_se + j],
4322 xcc_id);
4323 bitmap = gfx_v9_4_3_get_cu_active_bitmap(adev, xcc_id);
4324
4325 cu_info->bitmap[xcc_id][i][j] = bitmap;
4326
4327 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
4328 if (bitmap & mask) {
4329 if (counter < adev->gfx.config.max_cu_per_sh)
4330 ao_bitmap |= mask;
4331 counter++;
4332 }
4333 mask <<= 1;
4334 }
4335 active_cu_number += counter;
4336 if (i < 2 && j < 2)
4337 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
4338 cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
4339 }
4340 }
4341 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff,
4342 xcc_id);
4343 }
4344 mutex_unlock(&adev->grbm_idx_mutex);
4345
4346 cu_info->number = active_cu_number;
4347 cu_info->ao_cu_mask = ao_cu_mask;
4348 cu_info->simd_per_cu = NUM_SIMD_PER_CU;
4349
4350 return 0;
4351 }
4352
4353 const struct amdgpu_ip_block_version gfx_v9_4_3_ip_block = {
4354 .type = AMD_IP_BLOCK_TYPE_GFX,
4355 .major = 9,
4356 .minor = 4,
4357 .rev = 0,
4358 .funcs = &gfx_v9_4_3_ip_funcs,
4359 };
4360
gfx_v9_4_3_xcp_resume(void * handle,uint32_t inst_mask)4361 static int gfx_v9_4_3_xcp_resume(void *handle, uint32_t inst_mask)
4362 {
4363 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4364 uint32_t tmp_mask;
4365 int i, r;
4366
4367 /* TODO : Initialize golden regs */
4368 /* gfx_v9_4_3_init_golden_registers(adev); */
4369
4370 tmp_mask = inst_mask;
4371 for_each_inst(i, tmp_mask)
4372 gfx_v9_4_3_xcc_constants_init(adev, i);
4373
4374 if (!amdgpu_sriov_vf(adev)) {
4375 tmp_mask = inst_mask;
4376 for_each_inst(i, tmp_mask) {
4377 r = gfx_v9_4_3_xcc_rlc_resume(adev, i);
4378 if (r)
4379 return r;
4380 }
4381 }
4382
4383 tmp_mask = inst_mask;
4384 for_each_inst(i, tmp_mask) {
4385 r = gfx_v9_4_3_xcc_cp_resume(adev, i);
4386 if (r)
4387 return r;
4388 }
4389
4390 return 0;
4391 }
4392
gfx_v9_4_3_xcp_suspend(void * handle,uint32_t inst_mask)4393 static int gfx_v9_4_3_xcp_suspend(void *handle, uint32_t inst_mask)
4394 {
4395 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4396 int i;
4397
4398 for_each_inst(i, inst_mask)
4399 gfx_v9_4_3_xcc_fini(adev, i);
4400
4401 return 0;
4402 }
4403
4404 struct amdgpu_xcp_ip_funcs gfx_v9_4_3_xcp_funcs = {
4405 .suspend = &gfx_v9_4_3_xcp_suspend,
4406 .resume = &gfx_v9_4_3_xcp_resume
4407 };
4408
4409 struct amdgpu_ras_block_hw_ops gfx_v9_4_3_ras_ops = {
4410 .query_ras_error_count = &gfx_v9_4_3_query_ras_error_count,
4411 .reset_ras_error_count = &gfx_v9_4_3_reset_ras_error_count,
4412 .query_ras_error_status = &gfx_v9_4_3_query_ras_error_status,
4413 .reset_ras_error_status = &gfx_v9_4_3_reset_ras_error_status,
4414 };
4415
4416 struct amdgpu_gfx_ras gfx_v9_4_3_ras = {
4417 .ras_block = {
4418 .hw_ops = &gfx_v9_4_3_ras_ops,
4419 },
4420 .enable_watchdog_timer = &gfx_v9_4_3_enable_watchdog_timer,
4421 };
4422
