Searched refs:WRITE_DATA_DST_SEL (Results 1 – 17 of 17) sorted by relevance
152 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
110 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
89 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
142 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
260 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
892 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v8_0_ring_test_ib()5163 WRITE_DATA_DST_SEL(0))); in gfx_v8_0_ring_emit_gds_switch()5171 WRITE_DATA_DST_SEL(0))); in gfx_v8_0_ring_emit_gds_switch()5179 WRITE_DATA_DST_SEL(0))); in gfx_v8_0_ring_emit_gds_switch()5187 WRITE_DATA_DST_SEL(0))); in gfx_v8_0_ring_emit_gds_switch()6275 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v8_0_ring_emit_fence_kiq()6284 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v8_0_ring_emit_fence_kiq()7191 WRITE_DATA_DST_SEL(8) | in gfx_v8_0_ring_emit_ce_meta()7224 WRITE_DATA_DST_SEL(8) | in gfx_v8_0_ring_emit_de_meta()
3215 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_wreg()4045 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_gds_switch()4053 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_gds_switch()4061 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_gds_switch()4069 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_gds_switch()
218 WRITE_DATA_DST_SEL(0) | in gfx_v9_4_3_write_data_to_reg()305 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v9_4_3_ring_test_ib()2634 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v9_4_3_ring_emit_fence_kiq()2643 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v9_4_3_ring_emit_fence_kiq()
965 WRITE_DATA_DST_SEL(0) | in gfx_v9_0_write_data_to_reg()1048 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v9_0_ring_test_ib()5385 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v9_0_ring_emit_fence_kiq()5394 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v9_0_ring_emit_fence_kiq()5433 WRITE_DATA_DST_SEL(8) | in gfx_v9_0_ring_emit_ce_meta()5546 WRITE_DATA_DST_SEL(8) | in gfx_v9_0_ring_emit_de_meta()
285 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); in gfx_v11_0_write_data_to_reg()401 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v11_0_ring_test_ib()5444 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v11_0_ring_emit_fence_kiq()5453 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v11_0_ring_emit_fence_kiq()5614 WRITE_DATA_DST_SEL(8) | in gfx_v11_0_ring_emit_de_meta()
1700 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
3738 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); in gfx_v10_0_write_data_to_reg()3846 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v10_0_ring_test_ib()8458 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v10_0_ring_emit_fence_kiq()8467 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v10_0_ring_emit_fence_kiq()8615 WRITE_DATA_DST_SEL(8) | in gfx_v10_0_ring_emit_ce_meta()8666 WRITE_DATA_DST_SEL(8) | in gfx_v10_0_ring_emit_de_meta()
2327 WRITE_DATA_DST_SEL(0))); in gfx_v6_0_ring_emit_wreg()
1637 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
3742 radeon_ring_write(ring, WRITE_DATA_DST_SEL(1)); in cik_ring_ib_execute()5684 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()5698 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()5705 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()5716 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()5727 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()
1728 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
5077 WRITE_DATA_DST_SEL(0))); in si_vm_flush()5092 WRITE_DATA_DST_SEL(0))); in si_vm_flush()5100 WRITE_DATA_DST_SEL(0))); in si_vm_flush()
