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Searched refs:WREG32_P (Results 1 – 25 of 71) sorted by relevance

123

/Linux-v6.6/drivers/gpu/drm/radeon/
Duvd_v1_0.c227 WREG32_P(UVD_VCPU_CNTL, 0x10, ~0x10); in uvd_v1_0_init()
277 WREG32_P(UVD_MASTINT_EN, 0, ~(1 << 1)); in uvd_v1_0_start()
280 WREG32_P(UVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); in uvd_v1_0_start()
281 WREG32_P(UVD_RB_ARB_CTRL, 1 << 3, ~(1 << 3)); in uvd_v1_0_start()
291 WREG32_P(SRBM_SOFT_RESET, 0, ~SOFT_RESET_UVD); in uvd_v1_0_start()
321 WREG32_P(UVD_LMI_CTRL2, 0, ~(1 << 8)); in uvd_v1_0_start()
323 WREG32_P(UVD_RB_ARB_CTRL, 0, ~(1 << 3)); in uvd_v1_0_start()
342 WREG32_P(UVD_SOFT_RESET, VCPU_SOFT_RESET, ~VCPU_SOFT_RESET); in uvd_v1_0_start()
344 WREG32_P(UVD_SOFT_RESET, 0, ~VCPU_SOFT_RESET); in uvd_v1_0_start()
355 WREG32_P(UVD_MASTINT_EN, 3<<1, ~(3 << 1)); in uvd_v1_0_start()
[all …]
Drs780_dpm.c202 WREG32_P(FVTHROT_SLOW_CLK_FEEDBACK_DIV_REG1, RANGE_SLOW_CLK_FEEDBACK_DIV_EN, in rs780_preset_ranges_slow_clk_fbdiv_en()
205 WREG32_P(FVTHROT_SLOW_CLK_FEEDBACK_DIV_REG1, in rs780_preset_ranges_slow_clk_fbdiv_en()
214 WREG32_P(FVTHROT_FBDIV_REG1, STARTING_FEEDBACK_DIV(fbdiv), in rs780_preset_starting_fbdiv()
217 WREG32_P(FVTHROT_FBDIV_REG2, FORCED_FEEDBACK_DIV(fbdiv), in rs780_preset_starting_fbdiv()
220 WREG32_P(FVTHROT_FBDIV_REG1, FORCE_FEEDBACK_DIV, ~FORCE_FEEDBACK_DIV); in rs780_preset_starting_fbdiv()
260 WREG32_P(FVTHROT_PWM_CTRL_REG0, in rs780_voltage_scaling_init()
264 WREG32_P(FVTHROT_PWM_CTRL_REG0, in rs780_voltage_scaling_init()
268 WREG32_P(FVTHROT_PWM_CTRL_REG0, FORCE_STARTING_PWM_HIGHTIME, in rs780_voltage_scaling_init()
272 WREG32_P(FVTHROT_PWM_CTRL_REG0, INVERT_PWM_WAVEFORM, ~INVERT_PWM_WAVEFORM); in rs780_voltage_scaling_init()
274 WREG32_P(FVTHROT_PWM_CTRL_REG0, 0, ~INVERT_PWM_WAVEFORM); in rs780_voltage_scaling_init()
[all …]
Dr600_dpm.c247 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); in r600_gfx_clockgating_enable()
249 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); in r600_gfx_clockgating_enable()
269 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN); in r600_dynamicpm_enable()
271 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); in r600_dynamicpm_enable()
277 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); in r600_enable_thermal_protection()
279 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); in r600_enable_thermal_protection()
284 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN); in r600_enable_acpi_pm()
290 WREG32_P(GENERAL_PWRMGT, ENABLE_GEN2PCIE, ~ENABLE_GEN2PCIE); in r600_enable_dynamic_pcie_gen2()
292 WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE); in r600_enable_dynamic_pcie_gen2()
306 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); in r600_enable_sclk_control()
[all …]
Dvce_v1_0.c222 WREG32_P(VCE_CLOCK_GATING_A, 0, ~(1 << 16)); in vce_v1_0_resume()
223 WREG32_P(VCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000); in vce_v1_0_resume()
224 WREG32_P(VCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F); in vce_v1_0_resume()
227 WREG32_P(VCE_LMI_FW_PERIODIC_CTRL, 0x4, ~0x4); in vce_v1_0_resume()
230 WREG32_P(VCE_LMI_CACHE_CTRL, 0x0, ~0x1); in vce_v1_0_resume()
252 WREG32_P(VCE_LMI_CTRL2, 0x0, ~0x100); in vce_v1_0_resume()
295 WREG32_P(VCE_STATUS, 1, ~1); in vce_v1_0_start()
311 WREG32_P(VCE_VCPU_CNTL, VCE_CLK_EN, ~VCE_CLK_EN); in vce_v1_0_start()
313 WREG32_P(VCE_SOFT_RESET, in vce_v1_0_start()
321 WREG32_P(VCE_SOFT_RESET, 0, ~( in vce_v1_0_start()
[all …]
Dvce_v2_0.c163 WREG32_P(VCE_CLOCK_GATING_A, 0, ~(1 << 16)); in vce_v2_0_resume()
164 WREG32_P(VCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000); in vce_v2_0_resume()
165 WREG32_P(VCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F); in vce_v2_0_resume()
169 WREG32_P(VCE_LMI_CACHE_CTRL, 0x0, ~0x1); in vce_v2_0_resume()
191 WREG32_P(VCE_LMI_CTRL2, 0x0, ~0x100); in vce_v2_0_resume()
193 WREG32_P(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN, in vce_v2_0_resume()
Dr600_hdmi.c187 WREG32_P(acr_ctl + offset, in r600_hdmi_update_acr()
193 WREG32_P(HDMI0_ACR_32_0 + offset, in r600_hdmi_update_acr()
196 WREG32_P(HDMI0_ACR_32_1 + offset, in r600_hdmi_update_acr()
200 WREG32_P(HDMI0_ACR_44_0 + offset, in r600_hdmi_update_acr()
203 WREG32_P(HDMI0_ACR_44_1 + offset, in r600_hdmi_update_acr()
207 WREG32_P(HDMI0_ACR_48_0 + offset, in r600_hdmi_update_acr()
210 WREG32_P(HDMI0_ACR_48_1 + offset, in r600_hdmi_update_acr()
311 WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset, in r600_hdmi_audio_workaround()
357 WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset, in r600_set_audio_packet()
371 WREG32_P(HDMI0_INFOFRAME_CONTROL1 + offset, in r600_set_audio_packet()
[all …]
Dsumo_dpm.c91 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); in sumo_gfx_clockgating_enable()
93 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); in sumo_gfx_clockgating_enable()
94 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON); in sumo_gfx_clockgating_enable()
95 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON); in sumo_gfx_clockgating_enable()
128 WREG32_P(CG_GIT, CG_GICST(p), ~CG_GICST_MASK); in sumo_program_git()
175 WREG32_P(CG_PWR_GATING_CNTL, PGP(p) | PGU(u), in sumo_gfx_powergating_initialize()
181 WREG32_P(CG_CG_VOLTAGE_CNTL, PGP(p) | PGU(u), in sumo_gfx_powergating_initialize()
277 WREG32_P(CG_PWR_GATING_CNTL, DYN_PWR_DOWN_EN, ~DYN_PWR_DOWN_EN); in sumo_gfx_powergating_enable()
279 WREG32_P(CG_PWR_GATING_CNTL, 0, ~DYN_PWR_DOWN_EN); in sumo_gfx_powergating_enable()
436 WREG32_P(CG_FFCT_0 + (i * 4), UTC_0(sumo_utc[i]), ~UTC_0_MASK); in sumo_program_tp()
[all …]
Ddce3_1_afmt.c180 WREG32_P(HDMI0_ACR_32_0 + offset, in dce3_2_hdmi_update_acr()
183 WREG32_P(HDMI0_ACR_32_1 + offset, in dce3_2_hdmi_update_acr()
187 WREG32_P(HDMI0_ACR_44_0 + offset, in dce3_2_hdmi_update_acr()
190 WREG32_P(HDMI0_ACR_44_1 + offset, in dce3_2_hdmi_update_acr()
194 WREG32_P(HDMI0_ACR_48_0 + offset, in dce3_2_hdmi_update_acr()
197 WREG32_P(HDMI0_ACR_48_1 + offset, in dce3_2_hdmi_update_acr()
Drv6xx_dpm.c317 WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4), in rv6xx_set_engine_spread_spectrum_clk_s()
324 WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4), in rv6xx_set_engine_spread_spectrum_clk_v()
332 WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4), in rv6xx_enable_engine_spread_spectrum()
335 WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4), in rv6xx_enable_engine_spread_spectrum()
342 WREG32_P(CG_MPLL_SPREAD_SPECTRUM, CLKS(clk_s), ~CLKS_MASK); in rv6xx_set_memory_spread_spectrum_clk_s()
348 WREG32_P(CG_MPLL_SPREAD_SPECTRUM, CLKV(clk_v), ~CLKV_MASK); in rv6xx_set_memory_spread_spectrum_clk_v()
355 WREG32_P(CG_MPLL_SPREAD_SPECTRUM, SSEN, ~SSEN); in rv6xx_enable_memory_spread_spectrum()
357 WREG32_P(CG_MPLL_SPREAD_SPECTRUM, 0, ~SSEN); in rv6xx_enable_memory_spread_spectrum()
364 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN); in rv6xx_enable_dynamic_spread_spectrum()
366 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN); in rv6xx_enable_dynamic_spread_spectrum()
[all …]
Drv770_dpm.c135 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); in rv770_gfx_clock_gating_enable()
137 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); in rv770_gfx_clock_gating_enable()
138 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON); in rv770_gfx_clock_gating_enable()
139 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON); in rv770_gfx_clock_gating_enable()
178 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); in rv770_restore_cgcg()
183 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); in rv770_start_dpm()
185 WREG32_P(MCLK_PWRMGT_CNTL, 0, ~MPLL_PWRMGT_OFF); in rv770_start_dpm()
187 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN); in rv770_start_dpm()
199 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); in rv770_stop_dpm()
201 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); in rv770_stop_dpm()
[all …]
Dcypress_dpm.c91 WREG32_P(GENERAL_PWRMGT, ENABLE_GEN2PCIE, ~ENABLE_GEN2PCIE); in cypress_enable_dynamic_pcie_gen2()
93 WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE); in cypress_enable_dynamic_pcie_gen2()
102 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
103 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
104 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
109 WREG32_P(SMC_MSG, HOST_SMC_MSG(PPSMC_MSG_SwitchToMinimumPower),
140 WREG32_P(SCLK_PWRMGT_CNTL, DYN_LIGHT_SLEEP_EN, ~DYN_LIGHT_SLEEP_EN); in cypress_gfx_clock_gating_enable()
142 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); in cypress_gfx_clock_gating_enable()
144 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); in cypress_gfx_clock_gating_enable()
145 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON); in cypress_gfx_clock_gating_enable()
[all …]
Drv770_smc.c382 WREG32_P(SMC_IO, SMC_RST_N, ~SMC_RST_N); in rv770_start_smc()
387 WREG32_P(SMC_IO, 0, ~SMC_RST_N); in rv770_reset_smc()
392 WREG32_P(SMC_IO, 0, ~SMC_CLK_EN); in rv770_stop_smc_clock()
397 WREG32_P(SMC_IO, SMC_CLK_EN, ~SMC_CLK_EN); in rv770_start_smc_clock()
421 WREG32_P(SMC_MSG, HOST_SMC_MSG(msg), ~HOST_SMC_MSG_MASK); in rv770_send_msg_to_smc()
Dci_smc.c42 WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0); in ci_set_smc_sram_address()
230 WREG32_P(SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, ~AUTO_INCREMENT_IND_0); in ci_load_smc_ucode()
240 WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0); in ci_load_smc_ucode()
Drv770.c64 WREG32_P(CG_UPLL_FUNC_CNTL_2, in rv770_set_uvd_clocks()
70 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK); in rv770_set_uvd_clocks()
85 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(0x50000), ~UPLL_FB_DIV_MASK); in rv770_set_uvd_clocks()
88 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~(UPLL_RESET_MASK | UPLL_SLEEP_MASK)); in rv770_set_uvd_clocks()
91 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK); in rv770_set_uvd_clocks()
92 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(1), ~UPLL_FB_DIV(1)); in rv770_set_uvd_clocks()
99 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK); in rv770_set_uvd_clocks()
102 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REF_DIV(1), ~UPLL_REF_DIV_MASK); in rv770_set_uvd_clocks()
103 WREG32_P(CG_UPLL_FUNC_CNTL_2, in rv770_set_uvd_clocks()
110 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), in rv770_set_uvd_clocks()
[all …]
Dradeon_legacy_crtc.c331 WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask)); in radeon_crtc_dpms()
333 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN | in radeon_crtc_dpms()
335 WREG32_P(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl, ~(mask | crtc_ext_cntl)); in radeon_crtc_dpms()
347 WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask)); in radeon_crtc_dpms()
349 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN | in radeon_crtc_dpms()
351 WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~(mask | crtc_ext_cntl)); in radeon_crtc_dpms()
937 WREG32_P(RADEON_CLOCK_CNTL_INDEX, in radeon_set_pll()
958 WREG32_P(RADEON_CLOCK_CNTL_INDEX, in radeon_set_pll()
/Linux-v6.6/drivers/gpu/drm/amd/amdgpu/
Duvd_v3_1.c331 WREG32_P(mmUVD_STATUS, 1<<2, ~(1<<2)); in uvd_v3_1_start()
337 WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); in uvd_v3_1_start()
344 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); in uvd_v3_1_start()
372 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); in uvd_v3_1_start()
374 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK); in uvd_v3_1_start()
376 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); in uvd_v3_1_start()
378 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v3_1_start()
395 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, in uvd_v3_1_start()
398 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v3_1_start()
409 WREG32_P(mmUVD_MASTINT_EN, 3<<1, ~(3 << 1)); in uvd_v3_1_start()
[all …]
Duvd_v4_2.c289 WREG32_P(mmUVD_STATUS, 1<<2, ~(1<<2)); in uvd_v4_2_start()
295 WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); in uvd_v4_2_start()
302 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); in uvd_v4_2_start()
330 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); in uvd_v4_2_start()
332 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK); in uvd_v4_2_start()
334 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); in uvd_v4_2_start()
336 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v4_2_start()
353 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, in uvd_v4_2_start()
356 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v4_2_start()
367 WREG32_P(mmUVD_MASTINT_EN, 3<<1, ~(3 << 1)); in uvd_v4_2_start()
[all …]
Dvce_v2_0.c130 WREG32_P(mmVCE_SOFT_RESET, in vce_v2_0_firmware_loaded()
134 WREG32_P(mmVCE_SOFT_RESET, 0, in vce_v2_0_firmware_loaded()
172 WREG32_P(mmVCE_CLOCK_GATING_A, 0, ~(1 << 16)); in vce_v2_0_mc_resume()
173 WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000); in vce_v2_0_mc_resume()
174 WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F); in vce_v2_0_mc_resume()
178 WREG32_P(mmVCE_LMI_CACHE_CTRL, 0x0, ~0x1); in vce_v2_0_mc_resume()
200 WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100); in vce_v2_0_mc_resume()
236 WREG32_P(mmVCE_STATUS, 1, ~1); in vce_v2_0_start()
265 WREG32_P(mmVCE_STATUS, 0, ~1); in vce_v2_0_start()
291 WREG32_P(mmVCE_LMI_CTRL2, 1 << 8, ~(1 << 8)); in vce_v2_0_stop()
[all …]
Duvd_v5_0.c324 WREG32_P(mmUVD_POWER_STATUS, 0, ~(1 << 2)); in uvd_v5_0_start()
333 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); in uvd_v5_0_start()
336 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); in uvd_v5_0_start()
348 WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); in uvd_v5_0_start()
378 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); in uvd_v5_0_start()
397 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, in uvd_v5_0_start()
400 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v5_0_start()
410 WREG32_P(mmUVD_MASTINT_EN, 3 << 1, ~(3 << 1)); in uvd_v5_0_start()
413 WREG32_P(mmUVD_STATUS, 0, ~(2 << 1)); in uvd_v5_0_start()
444 WREG32_P(mmUVD_RBC_RB_CNTL, 0, ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); in uvd_v5_0_start()
[all …]
Dvce_v4_0.c140 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SOFT_RESET), in vce_v4_0_firmware_loaded()
144 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SOFT_RESET), 0, in vce_v4_0_firmware_loaded()
366 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), VCE_STATUS__JOB_BUSY_MASK, in vce_v4_0_start()
369 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CNTL), 1, ~0x200001); in vce_v4_0_start()
371 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SOFT_RESET), 0, in vce_v4_0_start()
378 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), 0, ~VCE_STATUS__JOB_BUSY_MASK); in vce_v4_0_start()
392 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CNTL), 0, ~0x200001); in vce_v4_0_stop()
395 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SOFT_RESET), in vce_v4_0_stop()
640 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_A), 0, ~(1 << 16)); in vce_v4_0_mc_resume()
641 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING), 0x1FF000, ~0xFF9FF000); in vce_v4_0_mc_resume()
[all …]
Djpeg_v3_0.c288 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), 0, in jpeg_v3_0_disable_static_power_gating()
292 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), 0, in jpeg_v3_0_disable_static_power_gating()
301 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), in jpeg_v3_0_enable_static_power_gating()
355 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL), 0, in jpeg_v3_0_start()
359 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmJPEG_SYS_INT_EN), in jpeg_v3_0_start()
390 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL), in jpeg_v3_0_stop()
Dsi.c1644 WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK); in si_uvd_send_upll_ctlreq()
1649 WREG32_P(cg_upll_func_cntl, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK); in si_uvd_send_upll_ctlreq()
1661 WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK); in si_uvd_send_upll_ctlreq()
1781 WREG32_P(CG_UPLL_FUNC_CNTL_2, in si_set_uvd_clocks()
1786 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK); in si_set_uvd_clocks()
1800 WREG32_P(CG_UPLL_FUNC_CNTL_5, 0, ~RESET_ANTI_MUX_MASK); in si_set_uvd_clocks()
1803 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK); in si_set_uvd_clocks()
1806 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK); in si_set_uvd_clocks()
1809 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); in si_set_uvd_clocks()
1818 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK); in si_set_uvd_clocks()
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Dvcn_v2_5.c826 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1, in vcn_v2_5_start_dpg_mode()
928 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), in vcn_v2_5_start_dpg_mode()
957 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), in vcn_v2_5_start_dpg_mode()
981 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS), 0, in vcn_v2_5_start()
999 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), in vcn_v2_5_start()
1003 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0, in vcn_v2_5_start()
1055 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0, in vcn_v2_5_start()
1059 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 0, in vcn_v2_5_start()
1062 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, in vcn_v2_5_start()
1082 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), in vcn_v2_5_start()
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Dvce_v3_0.c306 WREG32_P(mmVCE_VCPU_CNTL, 1, ~0x200001); in vce_v3_0_start()
343 WREG32_P(mmVCE_VCPU_CNTL, 0, ~0x200001); in vce_v3_0_stop()
556 WREG32_P(mmVCE_CLOCK_GATING_A, 0, ~(1 << 16)); in vce_v3_0_mc_resume()
557 WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000); in vce_v3_0_mc_resume()
558 WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F); in vce_v3_0_mc_resume()
562 WREG32_P(mmVCE_LMI_CACHE_CTRL, 0x0, ~0x1); in vce_v3_0_mc_resume()
599 WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100); in vce_v3_0_mc_resume()
739 WREG32_P(mmVCE_SYS_INT_EN, val, ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK); in vce_v3_0_set_interrupt_state()
/Linux-v6.6/drivers/gpu/drm/amd/pm/legacy-dpm/
Dsi_smc.c42 WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0); in si_set_smc_sram_address()
229 WREG32_P(SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, ~AUTO_INCREMENT_IND_0); in amdgpu_si_load_smc_ucode()
239 WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0); in amdgpu_si_load_smc_ucode()

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