Searched refs:VPU_37XX_HOST_SS_FW_SOC_IRQ_EN (Results 1 – 2 of 2) sorted by relevance
63 #define ITF_FIREWALL_VIOLATION_MASK ((REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, CSS_ROM_CMX)) | \64 (REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, CSS_DBG)) | \65 (REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, CSS_CTRL)) | \66 (REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, DEC400)) | \67 (REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, MSS_NCE)) | \68 (REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, MSS_MBI)) | \69 (REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, MSS_MBI_CMX)))867 REGV_WR32(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, ITF_FIREWALL_VIOLATION_MASK); in ivpu_hw_37xx_irq_enable()878 REGV_WR32(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, 0x0); in ivpu_hw_37xx_irq_disable()
128 #define VPU_37XX_HOST_SS_FW_SOC_IRQ_EN 0x00000170u macro
