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Searched refs:UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT (Results 1 – 13 of 13) sorted by relevance

/Linux-v6.6/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_sh_mask.h652 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT … macro
Duvd_3_1_sh_mask.h524 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x0 macro
Duvd_4_0_sh_mask.h751 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x00000000 macro
Duvd_4_2_sh_mask.h528 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x0 macro
Duvd_5_0_sh_mask.h560 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x0 macro
Duvd_6_0_sh_mask.h562 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x0 macro
/Linux-v6.6/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h1172 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT … macro
Dvcn_2_5_sh_mask.h2682 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT … macro
Dvcn_2_0_0_sh_mask.h2678 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT … macro
Dvcn_2_6_0_sh_mask.h35 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT … macro
Dvcn_3_0_0_sh_mask.h3740 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT … macro
Dvcn_4_0_0_sh_mask.h3986 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT … macro
Dvcn_4_0_3_sh_mask.h4021 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT … macro