Searched refs:UVD_MPC_SET_MUX__SET_2__SHIFT (Results 1 – 19 of 19) sorted by relevance
| /Linux-v6.6/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| D | uvd_7_0_sh_mask.h | 636 #define UVD_MPC_SET_MUX__SET_2__SHIFT … macro
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| D | uvd_4_2_sh_mask.h | 518 #define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6 macro
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| D | uvd_3_1_sh_mask.h | 514 #define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6 macro
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| D | uvd_4_0_sh_mask.h | 533 #define UVD_MPC_SET_MUX__SET_2__SHIFT 0x00000006 macro
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| D | uvd_6_0_sh_mask.h | 552 #define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6 macro
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| D | uvd_5_0_sh_mask.h | 550 #define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6 macro
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| /Linux-v6.6/drivers/gpu/drm/amd/include/asic_reg/vcn/ |
| D | vcn_1_0_sh_mask.h | 1143 #define UVD_MPC_SET_MUX__SET_2__SHIFT … macro
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| D | vcn_2_5_sh_mask.h | 2884 #define UVD_MPC_SET_MUX__SET_2__SHIFT … macro
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| D | vcn_2_0_0_sh_mask.h | 2649 #define UVD_MPC_SET_MUX__SET_2__SHIFT … macro
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| D | vcn_2_6_0_sh_mask.h | 2876 #define UVD_MPC_SET_MUX__SET_2__SHIFT … macro
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| D | vcn_3_0_0_sh_mask.h | 3957 #define UVD_MPC_SET_MUX__SET_2__SHIFT … macro
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| D | vcn_4_0_0_sh_mask.h | 4207 #define UVD_MPC_SET_MUX__SET_2__SHIFT … macro
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| D | vcn_4_0_3_sh_mask.h | 4250 #define UVD_MPC_SET_MUX__SET_2__SHIFT … macro
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| /Linux-v6.6/drivers/gpu/drm/amd/amdgpu/ |
| D | vcn_v4_0_3.c | 791 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); in vcn_v4_0_3_start_dpg_mode()
1117 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); in vcn_v4_0_3_start()
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| D | vcn_v1_0.c | 845 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); in vcn_v1_0_start_spg_mode()
1028 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0xFFFFFFFF, 0); in vcn_v1_0_start_dpg_mode()
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| D | vcn_v2_0.c | 860 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); in vcn_v2_0_start_dpg_mode()
993 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); in vcn_v2_0_start()
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| D | vcn_v4_0.c | 979 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); in vcn_v4_0_start_dpg_mode()
1118 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); in vcn_v4_0_start()
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| D | vcn_v2_5.c | 885 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); in vcn_v2_5_start_dpg_mode()
1039 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); in vcn_v2_5_start()
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| D | vcn_v3_0.c | 1008 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); in vcn_v3_0_start_dpg_mode()
1172 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); in vcn_v3_0_start()
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