1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2014-2023, The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/clk.h>
7 #include <linux/delay.h>
8 #include <linux/err.h>
9 #include <linux/io.h>
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/of.h>
13 #include <linux/phy/phy.h>
14 #include <linux/platform_device.h>
15 #include <linux/reset.h>
16 #include <linux/slab.h>
17
18 #define USB2PHY_PORT_UTMI_CTRL1 0x40
19
20 #define USB2PHY_PORT_UTMI_CTRL2 0x44
21 #define UTMI_ULPI_SEL BIT(7)
22 #define UTMI_TEST_MUX_SEL BIT(6)
23
24 #define HS_PHY_CTRL_REG 0x10
25 #define UTMI_OTG_VBUS_VALID BIT(20)
26 #define SW_SESSVLD_SEL BIT(28)
27
28 #define USB_PHY_UTMI_CTRL0 0x3c
29
30 #define USB_PHY_UTMI_CTRL5 0x50
31 #define POR_EN BIT(1)
32
33 #define USB_PHY_HS_PHY_CTRL_COMMON0 0x54
34 #define COMMONONN BIT(7)
35 #define FSEL BIT(4)
36 #define RETENABLEN BIT(3)
37 #define FREQ_24MHZ (BIT(6) | BIT(4))
38
39 #define USB_PHY_HS_PHY_CTRL2 0x64
40 #define USB2_SUSPEND_N_SEL BIT(3)
41 #define USB2_SUSPEND_N BIT(2)
42 #define USB2_UTMI_CLK_EN BIT(1)
43
44 #define USB_PHY_CFG0 0x94
45 #define UTMI_PHY_OVERRIDE_EN BIT(1)
46
47 #define USB_PHY_REFCLK_CTRL 0xa0
48 #define CLKCORE BIT(1)
49
50 #define USB2PHY_PORT_POWERDOWN 0xa4
51 #define POWER_UP BIT(0)
52 #define POWER_DOWN 0
53
54 #define USB_PHY_FSEL_SEL 0xb8
55 #define FREQ_SEL BIT(0)
56
57 #define USB2PHY_USB_PHY_M31_XCFGI_1 0xbc
58 #define USB2_0_TX_ENABLE BIT(2)
59
60 #define USB2PHY_USB_PHY_M31_XCFGI_4 0xc8
61 #define HSTX_SLEW_RATE_565PS GENMASK(1, 0)
62 #define PLL_CHARGING_PUMP_CURRENT_35UA GENMASK(4, 3)
63 #define ODT_VALUE_38_02_OHM GENMASK(7, 6)
64
65 #define USB2PHY_USB_PHY_M31_XCFGI_5 0xcc
66 #define ODT_VALUE_45_02_OHM BIT(2)
67 #define HSTX_PRE_EMPHASIS_LEVEL_0_55MA BIT(0)
68
69 #define USB2PHY_USB_PHY_M31_XCFGI_11 0xe4
70 #define XCFG_COARSE_TUNE_NUM BIT(1)
71 #define XCFG_FINE_TUNE_NUM BIT(3)
72
73 struct m31_phy_regs {
74 u32 off;
75 u32 val;
76 u32 delay;
77 };
78
79 struct m31_priv_data {
80 bool ulpi_mode;
81 const struct m31_phy_regs *regs;
82 unsigned int nregs;
83 };
84
85 static struct m31_phy_regs m31_ipq5332_regs[] = {
86 {
87 USB_PHY_CFG0,
88 UTMI_PHY_OVERRIDE_EN,
89 0
90 },
91 {
92 USB_PHY_UTMI_CTRL5,
93 POR_EN,
94 15
95 },
96 {
97 USB_PHY_FSEL_SEL,
98 FREQ_SEL,
99 0
100 },
101 {
102 USB_PHY_HS_PHY_CTRL_COMMON0,
103 COMMONONN | FREQ_24MHZ | RETENABLEN,
104 0
105 },
106 {
107 USB_PHY_UTMI_CTRL5,
108 POR_EN,
109 0
110 },
111 {
112 USB_PHY_HS_PHY_CTRL2,
113 USB2_SUSPEND_N_SEL | USB2_SUSPEND_N | USB2_UTMI_CLK_EN,
114 0
115 },
116 {
117 USB2PHY_USB_PHY_M31_XCFGI_11,
118 XCFG_COARSE_TUNE_NUM | XCFG_FINE_TUNE_NUM,
119 0
120 },
121 {
122 USB2PHY_USB_PHY_M31_XCFGI_4,
123 HSTX_SLEW_RATE_565PS | PLL_CHARGING_PUMP_CURRENT_35UA | ODT_VALUE_38_02_OHM,
124 0
125 },
126 {
127 USB2PHY_USB_PHY_M31_XCFGI_1,
128 USB2_0_TX_ENABLE,
129 0
130 },
131 {
132 USB2PHY_USB_PHY_M31_XCFGI_5,
133 ODT_VALUE_45_02_OHM | HSTX_PRE_EMPHASIS_LEVEL_0_55MA,
134 4
135 },
136 {
137 USB_PHY_UTMI_CTRL5,
138 0x0,
139 0
140 },
141 {
142 USB_PHY_HS_PHY_CTRL2,
143 USB2_SUSPEND_N | USB2_UTMI_CLK_EN,
144 0
145 },
146 };
147
148 struct m31usb_phy {
149 struct phy *phy;
150 void __iomem *base;
151 const struct m31_phy_regs *regs;
152 int nregs;
153
154 struct regulator *vreg;
155 struct clk *clk;
156 struct reset_control *reset;
157
158 bool ulpi_mode;
159 };
160
m31usb_phy_init(struct phy * phy)161 static int m31usb_phy_init(struct phy *phy)
162 {
163 struct m31usb_phy *qphy = phy_get_drvdata(phy);
164 const struct m31_phy_regs *regs = qphy->regs;
165 int i, ret;
166
167 ret = regulator_enable(qphy->vreg);
168 if (ret) {
169 dev_err(&phy->dev, "failed to enable regulator, %d\n", ret);
170 return ret;
171 }
172
173 ret = clk_prepare_enable(qphy->clk);
174 if (ret) {
175 regulator_disable(qphy->vreg);
176 dev_err(&phy->dev, "failed to enable cfg ahb clock, %d\n", ret);
177 return ret;
178 }
179
180 /* Perform phy reset */
181 reset_control_assert(qphy->reset);
182 udelay(5);
183 reset_control_deassert(qphy->reset);
184
185 /* configure for ULPI mode if requested */
186 if (qphy->ulpi_mode)
187 writel(0x0, qphy->base + USB2PHY_PORT_UTMI_CTRL2);
188
189 /* Enable the PHY */
190 writel(POWER_UP, qphy->base + USB2PHY_PORT_POWERDOWN);
191
192 /* Turn on phy ref clock */
193 for (i = 0; i < qphy->nregs; i++) {
194 writel(regs[i].val, qphy->base + regs[i].off);
195 if (regs[i].delay)
196 udelay(regs[i].delay);
197 }
198
199 return 0;
200 }
201
m31usb_phy_shutdown(struct phy * phy)202 static int m31usb_phy_shutdown(struct phy *phy)
203 {
204 struct m31usb_phy *qphy = phy_get_drvdata(phy);
205
206 /* Disable the PHY */
207 writel_relaxed(POWER_DOWN, qphy->base + USB2PHY_PORT_POWERDOWN);
208
209 clk_disable_unprepare(qphy->clk);
210
211 regulator_disable(qphy->vreg);
212
213 return 0;
214 }
215
216 static const struct phy_ops m31usb_phy_gen_ops = {
217 .power_on = m31usb_phy_init,
218 .power_off = m31usb_phy_shutdown,
219 .owner = THIS_MODULE,
220 };
221
m31usb_phy_probe(struct platform_device * pdev)222 static int m31usb_phy_probe(struct platform_device *pdev)
223 {
224 struct phy_provider *phy_provider;
225 const struct m31_priv_data *data;
226 struct device *dev = &pdev->dev;
227 struct m31usb_phy *qphy;
228
229 qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
230 if (!qphy)
231 return -ENOMEM;
232
233 qphy->base = devm_platform_ioremap_resource(pdev, 0);
234 if (IS_ERR(qphy->base))
235 return PTR_ERR(qphy->base);
236
237 qphy->reset = devm_reset_control_get_exclusive_by_index(dev, 0);
238 if (IS_ERR(qphy->reset))
239 return PTR_ERR(qphy->reset);
240
241 qphy->clk = devm_clk_get(dev, NULL);
242 if (IS_ERR(qphy->clk))
243 return dev_err_probe(dev, PTR_ERR(qphy->clk),
244 "failed to get clk\n");
245
246 data = of_device_get_match_data(dev);
247 qphy->regs = data->regs;
248 qphy->nregs = data->nregs;
249 qphy->ulpi_mode = data->ulpi_mode;
250
251 qphy->phy = devm_phy_create(dev, NULL, &m31usb_phy_gen_ops);
252 if (IS_ERR(qphy->phy))
253 return dev_err_probe(dev, PTR_ERR(qphy->phy),
254 "failed to create phy\n");
255
256 qphy->vreg = devm_regulator_get(dev, "vdda-phy");
257 if (IS_ERR(qphy->vreg))
258 return dev_err_probe(dev, PTR_ERR(qphy->vreg),
259 "failed to get vreg\n");
260
261 phy_set_drvdata(qphy->phy, qphy);
262
263 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
264 if (!IS_ERR(phy_provider))
265 dev_info(dev, "Registered M31 USB phy\n");
266
267 return PTR_ERR_OR_ZERO(phy_provider);
268 }
269
270 static const struct m31_priv_data m31_ipq5332_data = {
271 .ulpi_mode = false,
272 .regs = m31_ipq5332_regs,
273 .nregs = ARRAY_SIZE(m31_ipq5332_regs),
274 };
275
276 static const struct of_device_id m31usb_phy_id_table[] = {
277 { .compatible = "qcom,ipq5332-usb-hsphy", .data = &m31_ipq5332_data },
278 { },
279 };
280 MODULE_DEVICE_TABLE(of, m31usb_phy_id_table);
281
282 static struct platform_driver m31usb_phy_driver = {
283 .probe = m31usb_phy_probe,
284 .driver = {
285 .name = "qcom-m31usb-phy",
286 .of_match_table = m31usb_phy_id_table,
287 },
288 };
289
290 module_platform_driver(m31usb_phy_driver);
291
292 MODULE_DESCRIPTION("USB2 Qualcomm M31 HSPHY driver");
293 MODULE_LICENSE("GPL");
294
