Searched refs:UCR1_TRDYEN (Results 1 – 1 of 1) sorted by relevance
66 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ macro422 imx_uart_writel(sport, ucr1 & ~UCR1_TRDYEN, UCR1); in imx_uart_stop_tx()543 ucr1 &= ~UCR1_TRDYEN; in imx_uart_transmit_buffer()730 imx_uart_writel(sport, ucr1 | UCR1_TRDYEN, UCR1); in imx_uart_start_tx()739 ucr1 |= UCR1_TRDYEN; in imx_uart_start_tx()986 if ((ucr1 & UCR1_TRDYEN) == 0) in imx_uart_int()1589 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_RXDMAEN | in imx_uart_shutdown()1877 ucr1 &= ~(UCR1_TRDYEN | UCR1_RTSDEN | UCR1_RRDYEN); in imx_uart_poll_init()2021 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN); in imx_uart_console_write()2357 ucr1 &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN | UCR1_RTSDEN); in imx_uart_probe()
