Searched refs:UCR1_RRDYEN (Results 1 – 1 of 1) sorted by relevance
69 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ macro395 ucr1 |= UCR1_RRDYEN; in imx_uart_start_rx()484 ucr1 &= ~UCR1_RRDYEN; in imx_uart_stop_rx()982 if ((ucr1 & UCR1_RRDYEN) == 0) in imx_uart_int()1474 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN; in imx_uart_startup()1526 ucr1 |= UCR1_RRDYEN; in imx_uart_startup()1589 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_RXDMAEN | in imx_uart_shutdown()1877 ucr1 &= ~(UCR1_TRDYEN | UCR1_RTSDEN | UCR1_RRDYEN); in imx_uart_poll_init()1886 imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1); in imx_uart_poll_init()2021 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN); in imx_uart_console_write()[all …]
