Searched refs:UART_BAUD_CLK_DIVISOR_REG (Results 1 – 1 of 1) sorted by relevance
80 #define UART_BAUD_CLK_DIVISOR_REG 0x54 macro164 port->membase + UART_BAUD_CLK_DIVISOR_REG); in pci1xxxx_set_divisor()187 clock_div = readl(port->membase + UART_BAUD_CLK_DIVISOR_REG); in pci1xxxx_rs485_config()
