1 // SPDX-License-Identifier: GPL-2.0-only
2 /* CAN bus driver for Microchip 251x/25625 CAN Controller with SPI Interface
3 *
4 * MCP2510 support and bug fixes by Christian Pellegrin
5 * <chripell@evolware.org>
6 *
7 * Copyright 2009 Christian Pellegrin EVOL S.r.l.
8 *
9 * Copyright 2007 Raymarine UK, Ltd. All Rights Reserved.
10 * Written under contract by:
11 * Chris Elston, Katalix Systems, Ltd.
12 *
13 * Based on Microchip MCP251x CAN controller driver written by
14 * David Vrabel, Copyright 2006 Arcom Control Systems Ltd.
15 *
16 * Based on CAN bus driver for the CCAN controller written by
17 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix
18 * - Simon Kallweit, intefo AG
19 * Copyright 2007
20 */
21
22 #include <linux/bitfield.h>
23 #include <linux/can/core.h>
24 #include <linux/can/dev.h>
25 #include <linux/clk.h>
26 #include <linux/completion.h>
27 #include <linux/delay.h>
28 #include <linux/device.h>
29 #include <linux/ethtool.h>
30 #include <linux/freezer.h>
31 #include <linux/gpio.h>
32 #include <linux/gpio/driver.h>
33 #include <linux/interrupt.h>
34 #include <linux/io.h>
35 #include <linux/iopoll.h>
36 #include <linux/kernel.h>
37 #include <linux/module.h>
38 #include <linux/netdevice.h>
39 #include <linux/platform_device.h>
40 #include <linux/property.h>
41 #include <linux/regulator/consumer.h>
42 #include <linux/slab.h>
43 #include <linux/spi/spi.h>
44 #include <linux/uaccess.h>
45
46 /* SPI interface instruction set */
47 #define INSTRUCTION_WRITE 0x02
48 #define INSTRUCTION_READ 0x03
49 #define INSTRUCTION_BIT_MODIFY 0x05
50 #define INSTRUCTION_LOAD_TXB(n) (0x40 + 2 * (n))
51 #define INSTRUCTION_READ_RXB(n) (((n) == 0) ? 0x90 : 0x94)
52 #define INSTRUCTION_RESET 0xC0
53 #define RTS_TXB0 0x01
54 #define RTS_TXB1 0x02
55 #define RTS_TXB2 0x04
56 #define INSTRUCTION_RTS(n) (0x80 | ((n) & 0x07))
57
58 /* MPC251x registers */
59 #define BFPCTRL 0x0c
60 # define BFPCTRL_B0BFM BIT(0)
61 # define BFPCTRL_B1BFM BIT(1)
62 # define BFPCTRL_BFM(n) (BFPCTRL_B0BFM << (n))
63 # define BFPCTRL_BFM_MASK GENMASK(1, 0)
64 # define BFPCTRL_B0BFE BIT(2)
65 # define BFPCTRL_B1BFE BIT(3)
66 # define BFPCTRL_BFE(n) (BFPCTRL_B0BFE << (n))
67 # define BFPCTRL_BFE_MASK GENMASK(3, 2)
68 # define BFPCTRL_B0BFS BIT(4)
69 # define BFPCTRL_B1BFS BIT(5)
70 # define BFPCTRL_BFS(n) (BFPCTRL_B0BFS << (n))
71 # define BFPCTRL_BFS_MASK GENMASK(5, 4)
72 #define TXRTSCTRL 0x0d
73 # define TXRTSCTRL_B0RTSM BIT(0)
74 # define TXRTSCTRL_B1RTSM BIT(1)
75 # define TXRTSCTRL_B2RTSM BIT(2)
76 # define TXRTSCTRL_RTSM(n) (TXRTSCTRL_B0RTSM << (n))
77 # define TXRTSCTRL_RTSM_MASK GENMASK(2, 0)
78 # define TXRTSCTRL_B0RTS BIT(3)
79 # define TXRTSCTRL_B1RTS BIT(4)
80 # define TXRTSCTRL_B2RTS BIT(5)
81 # define TXRTSCTRL_RTS(n) (TXRTSCTRL_B0RTS << (n))
82 # define TXRTSCTRL_RTS_MASK GENMASK(5, 3)
83 #define CANSTAT 0x0e
84 #define CANCTRL 0x0f
85 # define CANCTRL_REQOP_MASK 0xe0
86 # define CANCTRL_REQOP_CONF 0x80
87 # define CANCTRL_REQOP_LISTEN_ONLY 0x60
88 # define CANCTRL_REQOP_LOOPBACK 0x40
89 # define CANCTRL_REQOP_SLEEP 0x20
90 # define CANCTRL_REQOP_NORMAL 0x00
91 # define CANCTRL_OSM 0x08
92 # define CANCTRL_ABAT 0x10
93 #define TEC 0x1c
94 #define REC 0x1d
95 #define CNF1 0x2a
96 # define CNF1_SJW_SHIFT 6
97 #define CNF2 0x29
98 # define CNF2_BTLMODE 0x80
99 # define CNF2_SAM 0x40
100 # define CNF2_PS1_SHIFT 3
101 #define CNF3 0x28
102 # define CNF3_SOF 0x08
103 # define CNF3_WAKFIL 0x04
104 # define CNF3_PHSEG2_MASK 0x07
105 #define CANINTE 0x2b
106 # define CANINTE_MERRE 0x80
107 # define CANINTE_WAKIE 0x40
108 # define CANINTE_ERRIE 0x20
109 # define CANINTE_TX2IE 0x10
110 # define CANINTE_TX1IE 0x08
111 # define CANINTE_TX0IE 0x04
112 # define CANINTE_RX1IE 0x02
113 # define CANINTE_RX0IE 0x01
114 #define CANINTF 0x2c
115 # define CANINTF_MERRF 0x80
116 # define CANINTF_WAKIF 0x40
117 # define CANINTF_ERRIF 0x20
118 # define CANINTF_TX2IF 0x10
119 # define CANINTF_TX1IF 0x08
120 # define CANINTF_TX0IF 0x04
121 # define CANINTF_RX1IF 0x02
122 # define CANINTF_RX0IF 0x01
123 # define CANINTF_RX (CANINTF_RX0IF | CANINTF_RX1IF)
124 # define CANINTF_TX (CANINTF_TX2IF | CANINTF_TX1IF | CANINTF_TX0IF)
125 # define CANINTF_ERR (CANINTF_ERRIF)
126 #define EFLG 0x2d
127 # define EFLG_EWARN 0x01
128 # define EFLG_RXWAR 0x02
129 # define EFLG_TXWAR 0x04
130 # define EFLG_RXEP 0x08
131 # define EFLG_TXEP 0x10
132 # define EFLG_TXBO 0x20
133 # define EFLG_RX0OVR 0x40
134 # define EFLG_RX1OVR 0x80
135 #define TXBCTRL(n) (((n) * 0x10) + 0x30 + TXBCTRL_OFF)
136 # define TXBCTRL_ABTF 0x40
137 # define TXBCTRL_MLOA 0x20
138 # define TXBCTRL_TXERR 0x10
139 # define TXBCTRL_TXREQ 0x08
140 #define TXBSIDH(n) (((n) * 0x10) + 0x30 + TXBSIDH_OFF)
141 # define SIDH_SHIFT 3
142 #define TXBSIDL(n) (((n) * 0x10) + 0x30 + TXBSIDL_OFF)
143 # define SIDL_SID_MASK 7
144 # define SIDL_SID_SHIFT 5
145 # define SIDL_EXIDE_SHIFT 3
146 # define SIDL_EID_SHIFT 16
147 # define SIDL_EID_MASK 3
148 #define TXBEID8(n) (((n) * 0x10) + 0x30 + TXBEID8_OFF)
149 #define TXBEID0(n) (((n) * 0x10) + 0x30 + TXBEID0_OFF)
150 #define TXBDLC(n) (((n) * 0x10) + 0x30 + TXBDLC_OFF)
151 # define DLC_RTR_SHIFT 6
152 #define TXBCTRL_OFF 0
153 #define TXBSIDH_OFF 1
154 #define TXBSIDL_OFF 2
155 #define TXBEID8_OFF 3
156 #define TXBEID0_OFF 4
157 #define TXBDLC_OFF 5
158 #define TXBDAT_OFF 6
159 #define RXBCTRL(n) (((n) * 0x10) + 0x60 + RXBCTRL_OFF)
160 # define RXBCTRL_BUKT 0x04
161 # define RXBCTRL_RXM0 0x20
162 # define RXBCTRL_RXM1 0x40
163 #define RXBSIDH(n) (((n) * 0x10) + 0x60 + RXBSIDH_OFF)
164 # define RXBSIDH_SHIFT 3
165 #define RXBSIDL(n) (((n) * 0x10) + 0x60 + RXBSIDL_OFF)
166 # define RXBSIDL_IDE 0x08
167 # define RXBSIDL_SRR 0x10
168 # define RXBSIDL_EID 3
169 # define RXBSIDL_SHIFT 5
170 #define RXBEID8(n) (((n) * 0x10) + 0x60 + RXBEID8_OFF)
171 #define RXBEID0(n) (((n) * 0x10) + 0x60 + RXBEID0_OFF)
172 #define RXBDLC(n) (((n) * 0x10) + 0x60 + RXBDLC_OFF)
173 # define RXBDLC_LEN_MASK 0x0f
174 # define RXBDLC_RTR 0x40
175 #define RXBCTRL_OFF 0
176 #define RXBSIDH_OFF 1
177 #define RXBSIDL_OFF 2
178 #define RXBEID8_OFF 3
179 #define RXBEID0_OFF 4
180 #define RXBDLC_OFF 5
181 #define RXBDAT_OFF 6
182 #define RXFSID(n) ((n < 3) ? 0 : 4)
183 #define RXFSIDH(n) ((n) * 4 + RXFSID(n))
184 #define RXFSIDL(n) ((n) * 4 + 1 + RXFSID(n))
185 #define RXFEID8(n) ((n) * 4 + 2 + RXFSID(n))
186 #define RXFEID0(n) ((n) * 4 + 3 + RXFSID(n))
187 #define RXMSIDH(n) ((n) * 4 + 0x20)
188 #define RXMSIDL(n) ((n) * 4 + 0x21)
189 #define RXMEID8(n) ((n) * 4 + 0x22)
190 #define RXMEID0(n) ((n) * 4 + 0x23)
191
192 #define GET_BYTE(val, byte) \
193 (((val) >> ((byte) * 8)) & 0xff)
194 #define SET_BYTE(val, byte) \
195 (((val) & 0xff) << ((byte) * 8))
196
197 /* Buffer size required for the largest SPI transfer (i.e., reading a
198 * frame)
199 */
200 #define CAN_FRAME_MAX_DATA_LEN 8
201 #define SPI_TRANSFER_BUF_LEN (6 + CAN_FRAME_MAX_DATA_LEN)
202 #define CAN_FRAME_MAX_BITS 128
203
204 #define TX_ECHO_SKB_MAX 1
205
206 #define MCP251X_OST_DELAY_MS (5)
207
208 #define DEVICE_NAME "mcp251x"
209
210 static const struct can_bittiming_const mcp251x_bittiming_const = {
211 .name = DEVICE_NAME,
212 .tseg1_min = 3,
213 .tseg1_max = 16,
214 .tseg2_min = 2,
215 .tseg2_max = 8,
216 .sjw_max = 4,
217 .brp_min = 1,
218 .brp_max = 64,
219 .brp_inc = 1,
220 };
221
222 enum mcp251x_model {
223 CAN_MCP251X_MCP2510 = 0x2510,
224 CAN_MCP251X_MCP2515 = 0x2515,
225 CAN_MCP251X_MCP25625 = 0x25625,
226 };
227
228 struct mcp251x_priv {
229 struct can_priv can;
230 struct net_device *net;
231 struct spi_device *spi;
232 enum mcp251x_model model;
233
234 struct mutex mcp_lock; /* SPI device lock */
235
236 u8 *spi_tx_buf;
237 u8 *spi_rx_buf;
238
239 struct sk_buff *tx_skb;
240
241 struct workqueue_struct *wq;
242 struct work_struct tx_work;
243 struct work_struct restart_work;
244
245 int force_quit;
246 int after_suspend;
247 #define AFTER_SUSPEND_UP 1
248 #define AFTER_SUSPEND_DOWN 2
249 #define AFTER_SUSPEND_POWER 4
250 #define AFTER_SUSPEND_RESTART 8
251 int restart_tx;
252 bool tx_busy;
253
254 struct regulator *power;
255 struct regulator *transceiver;
256 struct clk *clk;
257 #ifdef CONFIG_GPIOLIB
258 struct gpio_chip gpio;
259 u8 reg_bfpctrl;
260 #endif
261 };
262
263 #define MCP251X_IS(_model) \
264 static inline int mcp251x_is_##_model(struct spi_device *spi) \
265 { \
266 struct mcp251x_priv *priv = spi_get_drvdata(spi); \
267 return priv->model == CAN_MCP251X_MCP##_model; \
268 }
269
270 MCP251X_IS(2510);
271
mcp251x_clean(struct net_device * net)272 static void mcp251x_clean(struct net_device *net)
273 {
274 struct mcp251x_priv *priv = netdev_priv(net);
275
276 if (priv->tx_skb || priv->tx_busy)
277 net->stats.tx_errors++;
278 dev_kfree_skb(priv->tx_skb);
279 if (priv->tx_busy)
280 can_free_echo_skb(priv->net, 0, NULL);
281 priv->tx_skb = NULL;
282 priv->tx_busy = false;
283 }
284
285 /* Note about handling of error return of mcp251x_spi_trans: accessing
286 * registers via SPI is not really different conceptually than using
287 * normal I/O assembler instructions, although it's much more
288 * complicated from a practical POV. So it's not advisable to always
289 * check the return value of this function. Imagine that every
290 * read{b,l}, write{b,l} and friends would be bracketed in "if ( < 0)
291 * error();", it would be a great mess (well there are some situation
292 * when exception handling C++ like could be useful after all). So we
293 * just check that transfers are OK at the beginning of our
294 * conversation with the chip and to avoid doing really nasty things
295 * (like injecting bogus packets in the network stack).
296 */
mcp251x_spi_trans(struct spi_device * spi,int len)297 static int mcp251x_spi_trans(struct spi_device *spi, int len)
298 {
299 struct mcp251x_priv *priv = spi_get_drvdata(spi);
300 struct spi_transfer t = {
301 .tx_buf = priv->spi_tx_buf,
302 .rx_buf = priv->spi_rx_buf,
303 .len = len,
304 .cs_change = 0,
305 };
306 struct spi_message m;
307 int ret;
308
309 spi_message_init(&m);
310 spi_message_add_tail(&t, &m);
311
312 ret = spi_sync(spi, &m);
313 if (ret)
314 dev_err(&spi->dev, "spi transfer failed: ret = %d\n", ret);
315 return ret;
316 }
317
mcp251x_spi_write(struct spi_device * spi,int len)318 static int mcp251x_spi_write(struct spi_device *spi, int len)
319 {
320 struct mcp251x_priv *priv = spi_get_drvdata(spi);
321 int ret;
322
323 ret = spi_write(spi, priv->spi_tx_buf, len);
324 if (ret)
325 dev_err(&spi->dev, "spi write failed: ret = %d\n", ret);
326
327 return ret;
328 }
329
mcp251x_read_reg(struct spi_device * spi,u8 reg)330 static u8 mcp251x_read_reg(struct spi_device *spi, u8 reg)
331 {
332 struct mcp251x_priv *priv = spi_get_drvdata(spi);
333 u8 val = 0;
334
335 priv->spi_tx_buf[0] = INSTRUCTION_READ;
336 priv->spi_tx_buf[1] = reg;
337
338 if (spi->controller->flags & SPI_CONTROLLER_HALF_DUPLEX) {
339 spi_write_then_read(spi, priv->spi_tx_buf, 2, &val, 1);
340 } else {
341 mcp251x_spi_trans(spi, 3);
342 val = priv->spi_rx_buf[2];
343 }
344
345 return val;
346 }
347
mcp251x_read_2regs(struct spi_device * spi,u8 reg,u8 * v1,u8 * v2)348 static void mcp251x_read_2regs(struct spi_device *spi, u8 reg, u8 *v1, u8 *v2)
349 {
350 struct mcp251x_priv *priv = spi_get_drvdata(spi);
351
352 priv->spi_tx_buf[0] = INSTRUCTION_READ;
353 priv->spi_tx_buf[1] = reg;
354
355 if (spi->controller->flags & SPI_CONTROLLER_HALF_DUPLEX) {
356 u8 val[2] = { 0 };
357
358 spi_write_then_read(spi, priv->spi_tx_buf, 2, val, 2);
359 *v1 = val[0];
360 *v2 = val[1];
361 } else {
362 mcp251x_spi_trans(spi, 4);
363
364 *v1 = priv->spi_rx_buf[2];
365 *v2 = priv->spi_rx_buf[3];
366 }
367 }
368
mcp251x_write_reg(struct spi_device * spi,u8 reg,u8 val)369 static void mcp251x_write_reg(struct spi_device *spi, u8 reg, u8 val)
370 {
371 struct mcp251x_priv *priv = spi_get_drvdata(spi);
372
373 priv->spi_tx_buf[0] = INSTRUCTION_WRITE;
374 priv->spi_tx_buf[1] = reg;
375 priv->spi_tx_buf[2] = val;
376
377 mcp251x_spi_write(spi, 3);
378 }
379
mcp251x_write_2regs(struct spi_device * spi,u8 reg,u8 v1,u8 v2)380 static void mcp251x_write_2regs(struct spi_device *spi, u8 reg, u8 v1, u8 v2)
381 {
382 struct mcp251x_priv *priv = spi_get_drvdata(spi);
383
384 priv->spi_tx_buf[0] = INSTRUCTION_WRITE;
385 priv->spi_tx_buf[1] = reg;
386 priv->spi_tx_buf[2] = v1;
387 priv->spi_tx_buf[3] = v2;
388
389 mcp251x_spi_write(spi, 4);
390 }
391
mcp251x_write_bits(struct spi_device * spi,u8 reg,u8 mask,u8 val)392 static void mcp251x_write_bits(struct spi_device *spi, u8 reg,
393 u8 mask, u8 val)
394 {
395 struct mcp251x_priv *priv = spi_get_drvdata(spi);
396
397 priv->spi_tx_buf[0] = INSTRUCTION_BIT_MODIFY;
398 priv->spi_tx_buf[1] = reg;
399 priv->spi_tx_buf[2] = mask;
400 priv->spi_tx_buf[3] = val;
401
402 mcp251x_spi_write(spi, 4);
403 }
404
mcp251x_read_stat(struct spi_device * spi)405 static u8 mcp251x_read_stat(struct spi_device *spi)
406 {
407 return mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK;
408 }
409
410 #define mcp251x_read_stat_poll_timeout(addr, val, cond, delay_us, timeout_us) \
411 readx_poll_timeout(mcp251x_read_stat, addr, val, cond, \
412 delay_us, timeout_us)
413
414 #ifdef CONFIG_GPIOLIB
415 enum {
416 MCP251X_GPIO_TX0RTS = 0, /* inputs */
417 MCP251X_GPIO_TX1RTS,
418 MCP251X_GPIO_TX2RTS,
419 MCP251X_GPIO_RX0BF, /* outputs */
420 MCP251X_GPIO_RX1BF,
421 };
422
423 #define MCP251X_GPIO_INPUT_MASK \
424 GENMASK(MCP251X_GPIO_TX2RTS, MCP251X_GPIO_TX0RTS)
425 #define MCP251X_GPIO_OUTPUT_MASK \
426 GENMASK(MCP251X_GPIO_RX1BF, MCP251X_GPIO_RX0BF)
427
428 static const char * const mcp251x_gpio_names[] = {
429 [MCP251X_GPIO_TX0RTS] = "TX0RTS", /* inputs */
430 [MCP251X_GPIO_TX1RTS] = "TX1RTS",
431 [MCP251X_GPIO_TX2RTS] = "TX2RTS",
432 [MCP251X_GPIO_RX0BF] = "RX0BF", /* outputs */
433 [MCP251X_GPIO_RX1BF] = "RX1BF",
434 };
435
mcp251x_gpio_is_input(unsigned int offset)436 static inline bool mcp251x_gpio_is_input(unsigned int offset)
437 {
438 return offset <= MCP251X_GPIO_TX2RTS;
439 }
440
mcp251x_gpio_request(struct gpio_chip * chip,unsigned int offset)441 static int mcp251x_gpio_request(struct gpio_chip *chip,
442 unsigned int offset)
443 {
444 struct mcp251x_priv *priv = gpiochip_get_data(chip);
445 u8 val;
446
447 /* nothing to be done for inputs */
448 if (mcp251x_gpio_is_input(offset))
449 return 0;
450
451 val = BFPCTRL_BFE(offset - MCP251X_GPIO_RX0BF);
452
453 mutex_lock(&priv->mcp_lock);
454 mcp251x_write_bits(priv->spi, BFPCTRL, val, val);
455 mutex_unlock(&priv->mcp_lock);
456
457 priv->reg_bfpctrl |= val;
458
459 return 0;
460 }
461
mcp251x_gpio_free(struct gpio_chip * chip,unsigned int offset)462 static void mcp251x_gpio_free(struct gpio_chip *chip,
463 unsigned int offset)
464 {
465 struct mcp251x_priv *priv = gpiochip_get_data(chip);
466 u8 val;
467
468 /* nothing to be done for inputs */
469 if (mcp251x_gpio_is_input(offset))
470 return;
471
472 val = BFPCTRL_BFE(offset - MCP251X_GPIO_RX0BF);
473
474 mutex_lock(&priv->mcp_lock);
475 mcp251x_write_bits(priv->spi, BFPCTRL, val, 0);
476 mutex_unlock(&priv->mcp_lock);
477
478 priv->reg_bfpctrl &= ~val;
479 }
480
mcp251x_gpio_get_direction(struct gpio_chip * chip,unsigned int offset)481 static int mcp251x_gpio_get_direction(struct gpio_chip *chip,
482 unsigned int offset)
483 {
484 if (mcp251x_gpio_is_input(offset))
485 return GPIOF_DIR_IN;
486
487 return GPIOF_DIR_OUT;
488 }
489
mcp251x_gpio_get(struct gpio_chip * chip,unsigned int offset)490 static int mcp251x_gpio_get(struct gpio_chip *chip, unsigned int offset)
491 {
492 struct mcp251x_priv *priv = gpiochip_get_data(chip);
493 u8 reg, mask, val;
494
495 if (mcp251x_gpio_is_input(offset)) {
496 reg = TXRTSCTRL;
497 mask = TXRTSCTRL_RTS(offset);
498 } else {
499 reg = BFPCTRL;
500 mask = BFPCTRL_BFS(offset - MCP251X_GPIO_RX0BF);
501 }
502
503 mutex_lock(&priv->mcp_lock);
504 val = mcp251x_read_reg(priv->spi, reg);
505 mutex_unlock(&priv->mcp_lock);
506
507 return !!(val & mask);
508 }
509
mcp251x_gpio_get_multiple(struct gpio_chip * chip,unsigned long * maskp,unsigned long * bitsp)510 static int mcp251x_gpio_get_multiple(struct gpio_chip *chip,
511 unsigned long *maskp, unsigned long *bitsp)
512 {
513 struct mcp251x_priv *priv = gpiochip_get_data(chip);
514 unsigned long bits = 0;
515 u8 val;
516
517 mutex_lock(&priv->mcp_lock);
518 if (maskp[0] & MCP251X_GPIO_INPUT_MASK) {
519 val = mcp251x_read_reg(priv->spi, TXRTSCTRL);
520 val = FIELD_GET(TXRTSCTRL_RTS_MASK, val);
521 bits |= FIELD_PREP(MCP251X_GPIO_INPUT_MASK, val);
522 }
523 if (maskp[0] & MCP251X_GPIO_OUTPUT_MASK) {
524 val = mcp251x_read_reg(priv->spi, BFPCTRL);
525 val = FIELD_GET(BFPCTRL_BFS_MASK, val);
526 bits |= FIELD_PREP(MCP251X_GPIO_OUTPUT_MASK, val);
527 }
528 mutex_unlock(&priv->mcp_lock);
529
530 bitsp[0] = bits;
531 return 0;
532 }
533
mcp251x_gpio_set(struct gpio_chip * chip,unsigned int offset,int value)534 static void mcp251x_gpio_set(struct gpio_chip *chip, unsigned int offset,
535 int value)
536 {
537 struct mcp251x_priv *priv = gpiochip_get_data(chip);
538 u8 mask, val;
539
540 mask = BFPCTRL_BFS(offset - MCP251X_GPIO_RX0BF);
541 val = value ? mask : 0;
542
543 mutex_lock(&priv->mcp_lock);
544 mcp251x_write_bits(priv->spi, BFPCTRL, mask, val);
545 mutex_unlock(&priv->mcp_lock);
546
547 priv->reg_bfpctrl &= ~mask;
548 priv->reg_bfpctrl |= val;
549 }
550
551 static void
mcp251x_gpio_set_multiple(struct gpio_chip * chip,unsigned long * maskp,unsigned long * bitsp)552 mcp251x_gpio_set_multiple(struct gpio_chip *chip,
553 unsigned long *maskp, unsigned long *bitsp)
554 {
555 struct mcp251x_priv *priv = gpiochip_get_data(chip);
556 u8 mask, val;
557
558 mask = FIELD_GET(MCP251X_GPIO_OUTPUT_MASK, maskp[0]);
559 mask = FIELD_PREP(BFPCTRL_BFS_MASK, mask);
560
561 val = FIELD_GET(MCP251X_GPIO_OUTPUT_MASK, bitsp[0]);
562 val = FIELD_PREP(BFPCTRL_BFS_MASK, val);
563
564 if (!mask)
565 return;
566
567 mutex_lock(&priv->mcp_lock);
568 mcp251x_write_bits(priv->spi, BFPCTRL, mask, val);
569 mutex_unlock(&priv->mcp_lock);
570
571 priv->reg_bfpctrl &= ~mask;
572 priv->reg_bfpctrl |= val;
573 }
574
mcp251x_gpio_restore(struct spi_device * spi)575 static void mcp251x_gpio_restore(struct spi_device *spi)
576 {
577 struct mcp251x_priv *priv = spi_get_drvdata(spi);
578
579 mcp251x_write_reg(spi, BFPCTRL, priv->reg_bfpctrl);
580 }
581
mcp251x_gpio_setup(struct mcp251x_priv * priv)582 static int mcp251x_gpio_setup(struct mcp251x_priv *priv)
583 {
584 struct gpio_chip *gpio = &priv->gpio;
585
586 if (!device_property_present(&priv->spi->dev, "gpio-controller"))
587 return 0;
588
589 /* gpiochip handles TX[0..2]RTS and RX[0..1]BF */
590 gpio->label = priv->spi->modalias;
591 gpio->parent = &priv->spi->dev;
592 gpio->owner = THIS_MODULE;
593 gpio->request = mcp251x_gpio_request;
594 gpio->free = mcp251x_gpio_free;
595 gpio->get_direction = mcp251x_gpio_get_direction;
596 gpio->get = mcp251x_gpio_get;
597 gpio->get_multiple = mcp251x_gpio_get_multiple;
598 gpio->set = mcp251x_gpio_set;
599 gpio->set_multiple = mcp251x_gpio_set_multiple;
600 gpio->base = -1;
601 gpio->ngpio = ARRAY_SIZE(mcp251x_gpio_names);
602 gpio->names = mcp251x_gpio_names;
603 gpio->can_sleep = true;
604
605 return devm_gpiochip_add_data(&priv->spi->dev, gpio, priv);
606 }
607 #else
mcp251x_gpio_restore(struct spi_device * spi)608 static inline void mcp251x_gpio_restore(struct spi_device *spi)
609 {
610 }
611
mcp251x_gpio_setup(struct mcp251x_priv * priv)612 static inline int mcp251x_gpio_setup(struct mcp251x_priv *priv)
613 {
614 return 0;
615 }
616 #endif
617
mcp251x_hw_tx_frame(struct spi_device * spi,u8 * buf,int len,int tx_buf_idx)618 static void mcp251x_hw_tx_frame(struct spi_device *spi, u8 *buf,
619 int len, int tx_buf_idx)
620 {
621 struct mcp251x_priv *priv = spi_get_drvdata(spi);
622
623 if (mcp251x_is_2510(spi)) {
624 int i;
625
626 for (i = 1; i < TXBDAT_OFF + len; i++)
627 mcp251x_write_reg(spi, TXBCTRL(tx_buf_idx) + i,
628 buf[i]);
629 } else {
630 memcpy(priv->spi_tx_buf, buf, TXBDAT_OFF + len);
631 mcp251x_spi_write(spi, TXBDAT_OFF + len);
632 }
633 }
634
mcp251x_hw_tx(struct spi_device * spi,struct can_frame * frame,int tx_buf_idx)635 static void mcp251x_hw_tx(struct spi_device *spi, struct can_frame *frame,
636 int tx_buf_idx)
637 {
638 struct mcp251x_priv *priv = spi_get_drvdata(spi);
639 u32 sid, eid, exide, rtr;
640 u8 buf[SPI_TRANSFER_BUF_LEN];
641
642 exide = (frame->can_id & CAN_EFF_FLAG) ? 1 : 0; /* Extended ID Enable */
643 if (exide)
644 sid = (frame->can_id & CAN_EFF_MASK) >> 18;
645 else
646 sid = frame->can_id & CAN_SFF_MASK; /* Standard ID */
647 eid = frame->can_id & CAN_EFF_MASK; /* Extended ID */
648 rtr = (frame->can_id & CAN_RTR_FLAG) ? 1 : 0; /* Remote transmission */
649
650 buf[TXBCTRL_OFF] = INSTRUCTION_LOAD_TXB(tx_buf_idx);
651 buf[TXBSIDH_OFF] = sid >> SIDH_SHIFT;
652 buf[TXBSIDL_OFF] = ((sid & SIDL_SID_MASK) << SIDL_SID_SHIFT) |
653 (exide << SIDL_EXIDE_SHIFT) |
654 ((eid >> SIDL_EID_SHIFT) & SIDL_EID_MASK);
655 buf[TXBEID8_OFF] = GET_BYTE(eid, 1);
656 buf[TXBEID0_OFF] = GET_BYTE(eid, 0);
657 buf[TXBDLC_OFF] = (rtr << DLC_RTR_SHIFT) | frame->len;
658 memcpy(buf + TXBDAT_OFF, frame->data, frame->len);
659 mcp251x_hw_tx_frame(spi, buf, frame->len, tx_buf_idx);
660
661 /* use INSTRUCTION_RTS, to avoid "repeated frame problem" */
662 priv->spi_tx_buf[0] = INSTRUCTION_RTS(1 << tx_buf_idx);
663 mcp251x_spi_write(priv->spi, 1);
664 }
665
mcp251x_hw_rx_frame(struct spi_device * spi,u8 * buf,int buf_idx)666 static void mcp251x_hw_rx_frame(struct spi_device *spi, u8 *buf,
667 int buf_idx)
668 {
669 struct mcp251x_priv *priv = spi_get_drvdata(spi);
670
671 if (mcp251x_is_2510(spi)) {
672 int i, len;
673
674 for (i = 1; i < RXBDAT_OFF; i++)
675 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
676
677 len = can_cc_dlc2len(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK);
678 for (; i < (RXBDAT_OFF + len); i++)
679 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
680 } else {
681 priv->spi_tx_buf[RXBCTRL_OFF] = INSTRUCTION_READ_RXB(buf_idx);
682 if (spi->controller->flags & SPI_CONTROLLER_HALF_DUPLEX) {
683 spi_write_then_read(spi, priv->spi_tx_buf, 1,
684 priv->spi_rx_buf,
685 SPI_TRANSFER_BUF_LEN);
686 memcpy(buf + 1, priv->spi_rx_buf,
687 SPI_TRANSFER_BUF_LEN - 1);
688 } else {
689 mcp251x_spi_trans(spi, SPI_TRANSFER_BUF_LEN);
690 memcpy(buf, priv->spi_rx_buf, SPI_TRANSFER_BUF_LEN);
691 }
692 }
693 }
694
mcp251x_hw_rx(struct spi_device * spi,int buf_idx)695 static void mcp251x_hw_rx(struct spi_device *spi, int buf_idx)
696 {
697 struct mcp251x_priv *priv = spi_get_drvdata(spi);
698 struct sk_buff *skb;
699 struct can_frame *frame;
700 u8 buf[SPI_TRANSFER_BUF_LEN];
701
702 skb = alloc_can_skb(priv->net, &frame);
703 if (!skb) {
704 dev_err(&spi->dev, "cannot allocate RX skb\n");
705 priv->net->stats.rx_dropped++;
706 return;
707 }
708
709 mcp251x_hw_rx_frame(spi, buf, buf_idx);
710 if (buf[RXBSIDL_OFF] & RXBSIDL_IDE) {
711 /* Extended ID format */
712 frame->can_id = CAN_EFF_FLAG;
713 frame->can_id |=
714 /* Extended ID part */
715 SET_BYTE(buf[RXBSIDL_OFF] & RXBSIDL_EID, 2) |
716 SET_BYTE(buf[RXBEID8_OFF], 1) |
717 SET_BYTE(buf[RXBEID0_OFF], 0) |
718 /* Standard ID part */
719 (((buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) |
720 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT)) << 18);
721 /* Remote transmission request */
722 if (buf[RXBDLC_OFF] & RXBDLC_RTR)
723 frame->can_id |= CAN_RTR_FLAG;
724 } else {
725 /* Standard ID format */
726 frame->can_id =
727 (buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) |
728 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT);
729 if (buf[RXBSIDL_OFF] & RXBSIDL_SRR)
730 frame->can_id |= CAN_RTR_FLAG;
731 }
732 /* Data length */
733 frame->len = can_cc_dlc2len(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK);
734 if (!(frame->can_id & CAN_RTR_FLAG)) {
735 memcpy(frame->data, buf + RXBDAT_OFF, frame->len);
736
737 priv->net->stats.rx_bytes += frame->len;
738 }
739 priv->net->stats.rx_packets++;
740
741 netif_rx(skb);
742 }
743
mcp251x_hw_sleep(struct spi_device * spi)744 static void mcp251x_hw_sleep(struct spi_device *spi)
745 {
746 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_SLEEP);
747 }
748
749 /* May only be called when device is sleeping! */
mcp251x_hw_wake(struct spi_device * spi)750 static int mcp251x_hw_wake(struct spi_device *spi)
751 {
752 u8 value;
753 int ret;
754
755 /* Force wakeup interrupt to wake device, but don't execute IST */
756 disable_irq(spi->irq);
757 mcp251x_write_2regs(spi, CANINTE, CANINTE_WAKIE, CANINTF_WAKIF);
758
759 /* Wait for oscillator startup timer after wake up */
760 mdelay(MCP251X_OST_DELAY_MS);
761
762 /* Put device into config mode */
763 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_CONF);
764
765 /* Wait for the device to enter config mode */
766 ret = mcp251x_read_stat_poll_timeout(spi, value, value == CANCTRL_REQOP_CONF,
767 MCP251X_OST_DELAY_MS * 1000,
768 USEC_PER_SEC);
769 if (ret) {
770 dev_err(&spi->dev, "MCP251x didn't enter in config mode\n");
771 return ret;
772 }
773
774 /* Disable and clear pending interrupts */
775 mcp251x_write_2regs(spi, CANINTE, 0x00, 0x00);
776 enable_irq(spi->irq);
777
778 return 0;
779 }
780
mcp251x_hard_start_xmit(struct sk_buff * skb,struct net_device * net)781 static netdev_tx_t mcp251x_hard_start_xmit(struct sk_buff *skb,
782 struct net_device *net)
783 {
784 struct mcp251x_priv *priv = netdev_priv(net);
785 struct spi_device *spi = priv->spi;
786
787 if (priv->tx_skb || priv->tx_busy) {
788 dev_warn(&spi->dev, "hard_xmit called while tx busy\n");
789 return NETDEV_TX_BUSY;
790 }
791
792 if (can_dev_dropped_skb(net, skb))
793 return NETDEV_TX_OK;
794
795 netif_stop_queue(net);
796 priv->tx_skb = skb;
797 queue_work(priv->wq, &priv->tx_work);
798
799 return NETDEV_TX_OK;
800 }
801
mcp251x_do_set_mode(struct net_device * net,enum can_mode mode)802 static int mcp251x_do_set_mode(struct net_device *net, enum can_mode mode)
803 {
804 struct mcp251x_priv *priv = netdev_priv(net);
805
806 switch (mode) {
807 case CAN_MODE_START:
808 mcp251x_clean(net);
809 /* We have to delay work since SPI I/O may sleep */
810 priv->can.state = CAN_STATE_ERROR_ACTIVE;
811 priv->restart_tx = 1;
812 if (priv->can.restart_ms == 0)
813 priv->after_suspend = AFTER_SUSPEND_RESTART;
814 queue_work(priv->wq, &priv->restart_work);
815 break;
816 default:
817 return -EOPNOTSUPP;
818 }
819
820 return 0;
821 }
822
mcp251x_set_normal_mode(struct spi_device * spi)823 static int mcp251x_set_normal_mode(struct spi_device *spi)
824 {
825 struct mcp251x_priv *priv = spi_get_drvdata(spi);
826 u8 value;
827 int ret;
828
829 /* Enable interrupts */
830 mcp251x_write_reg(spi, CANINTE,
831 CANINTE_ERRIE | CANINTE_TX2IE | CANINTE_TX1IE |
832 CANINTE_TX0IE | CANINTE_RX1IE | CANINTE_RX0IE);
833
834 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
835 /* Put device into loopback mode */
836 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LOOPBACK);
837 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) {
838 /* Put device into listen-only mode */
839 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LISTEN_ONLY);
840 } else {
841 /* Put device into normal mode */
842 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_NORMAL);
843
844 /* Wait for the device to enter normal mode */
845 ret = mcp251x_read_stat_poll_timeout(spi, value, value == 0,
846 MCP251X_OST_DELAY_MS * 1000,
847 USEC_PER_SEC);
848 if (ret) {
849 dev_err(&spi->dev, "MCP251x didn't enter in normal mode\n");
850 return ret;
851 }
852 }
853 priv->can.state = CAN_STATE_ERROR_ACTIVE;
854 return 0;
855 }
856
mcp251x_do_set_bittiming(struct net_device * net)857 static int mcp251x_do_set_bittiming(struct net_device *net)
858 {
859 struct mcp251x_priv *priv = netdev_priv(net);
860 struct can_bittiming *bt = &priv->can.bittiming;
861 struct spi_device *spi = priv->spi;
862
863 mcp251x_write_reg(spi, CNF1, ((bt->sjw - 1) << CNF1_SJW_SHIFT) |
864 (bt->brp - 1));
865 mcp251x_write_reg(spi, CNF2, CNF2_BTLMODE |
866 (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES ?
867 CNF2_SAM : 0) |
868 ((bt->phase_seg1 - 1) << CNF2_PS1_SHIFT) |
869 (bt->prop_seg - 1));
870 mcp251x_write_bits(spi, CNF3, CNF3_PHSEG2_MASK,
871 (bt->phase_seg2 - 1));
872 dev_dbg(&spi->dev, "CNF: 0x%02x 0x%02x 0x%02x\n",
873 mcp251x_read_reg(spi, CNF1),
874 mcp251x_read_reg(spi, CNF2),
875 mcp251x_read_reg(spi, CNF3));
876
877 return 0;
878 }
879
mcp251x_setup(struct net_device * net,struct spi_device * spi)880 static int mcp251x_setup(struct net_device *net, struct spi_device *spi)
881 {
882 mcp251x_do_set_bittiming(net);
883
884 mcp251x_write_reg(spi, RXBCTRL(0),
885 RXBCTRL_BUKT | RXBCTRL_RXM0 | RXBCTRL_RXM1);
886 mcp251x_write_reg(spi, RXBCTRL(1),
887 RXBCTRL_RXM0 | RXBCTRL_RXM1);
888 return 0;
889 }
890
mcp251x_hw_reset(struct spi_device * spi)891 static int mcp251x_hw_reset(struct spi_device *spi)
892 {
893 struct mcp251x_priv *priv = spi_get_drvdata(spi);
894 u8 value;
895 int ret;
896
897 /* Wait for oscillator startup timer after power up */
898 mdelay(MCP251X_OST_DELAY_MS);
899
900 priv->spi_tx_buf[0] = INSTRUCTION_RESET;
901 ret = mcp251x_spi_write(spi, 1);
902 if (ret)
903 return ret;
904
905 /* Wait for oscillator startup timer after reset */
906 mdelay(MCP251X_OST_DELAY_MS);
907
908 /* Wait for reset to finish */
909 ret = mcp251x_read_stat_poll_timeout(spi, value, value == CANCTRL_REQOP_CONF,
910 MCP251X_OST_DELAY_MS * 1000,
911 USEC_PER_SEC);
912 if (ret)
913 dev_err(&spi->dev, "MCP251x didn't enter in conf mode after reset\n");
914 return ret;
915 }
916
mcp251x_hw_probe(struct spi_device * spi)917 static int mcp251x_hw_probe(struct spi_device *spi)
918 {
919 u8 ctrl;
920 int ret;
921
922 ret = mcp251x_hw_reset(spi);
923 if (ret)
924 return ret;
925
926 ctrl = mcp251x_read_reg(spi, CANCTRL);
927
928 dev_dbg(&spi->dev, "CANCTRL 0x%02x\n", ctrl);
929
930 /* Check for power up default value */
931 if ((ctrl & 0x17) != 0x07)
932 return -ENODEV;
933
934 return 0;
935 }
936
mcp251x_power_enable(struct regulator * reg,int enable)937 static int mcp251x_power_enable(struct regulator *reg, int enable)
938 {
939 if (IS_ERR_OR_NULL(reg))
940 return 0;
941
942 if (enable)
943 return regulator_enable(reg);
944 else
945 return regulator_disable(reg);
946 }
947
mcp251x_stop(struct net_device * net)948 static int mcp251x_stop(struct net_device *net)
949 {
950 struct mcp251x_priv *priv = netdev_priv(net);
951 struct spi_device *spi = priv->spi;
952
953 close_candev(net);
954
955 priv->force_quit = 1;
956 free_irq(spi->irq, priv);
957
958 mutex_lock(&priv->mcp_lock);
959
960 /* Disable and clear pending interrupts */
961 mcp251x_write_2regs(spi, CANINTE, 0x00, 0x00);
962
963 mcp251x_write_reg(spi, TXBCTRL(0), 0);
964 mcp251x_clean(net);
965
966 mcp251x_hw_sleep(spi);
967
968 mcp251x_power_enable(priv->transceiver, 0);
969
970 priv->can.state = CAN_STATE_STOPPED;
971
972 mutex_unlock(&priv->mcp_lock);
973
974 return 0;
975 }
976
mcp251x_error_skb(struct net_device * net,int can_id,int data1)977 static void mcp251x_error_skb(struct net_device *net, int can_id, int data1)
978 {
979 struct sk_buff *skb;
980 struct can_frame *frame;
981
982 skb = alloc_can_err_skb(net, &frame);
983 if (skb) {
984 frame->can_id |= can_id;
985 frame->data[1] = data1;
986 netif_rx(skb);
987 } else {
988 netdev_err(net, "cannot allocate error skb\n");
989 }
990 }
991
mcp251x_tx_work_handler(struct work_struct * ws)992 static void mcp251x_tx_work_handler(struct work_struct *ws)
993 {
994 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
995 tx_work);
996 struct spi_device *spi = priv->spi;
997 struct net_device *net = priv->net;
998 struct can_frame *frame;
999
1000 mutex_lock(&priv->mcp_lock);
1001 if (priv->tx_skb) {
1002 if (priv->can.state == CAN_STATE_BUS_OFF) {
1003 mcp251x_clean(net);
1004 } else {
1005 frame = (struct can_frame *)priv->tx_skb->data;
1006
1007 if (frame->len > CAN_FRAME_MAX_DATA_LEN)
1008 frame->len = CAN_FRAME_MAX_DATA_LEN;
1009 mcp251x_hw_tx(spi, frame, 0);
1010 priv->tx_busy = true;
1011 can_put_echo_skb(priv->tx_skb, net, 0, 0);
1012 priv->tx_skb = NULL;
1013 }
1014 }
1015 mutex_unlock(&priv->mcp_lock);
1016 }
1017
mcp251x_restart_work_handler(struct work_struct * ws)1018 static void mcp251x_restart_work_handler(struct work_struct *ws)
1019 {
1020 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
1021 restart_work);
1022 struct spi_device *spi = priv->spi;
1023 struct net_device *net = priv->net;
1024
1025 mutex_lock(&priv->mcp_lock);
1026 if (priv->after_suspend) {
1027 if (priv->after_suspend & AFTER_SUSPEND_POWER) {
1028 mcp251x_hw_reset(spi);
1029 mcp251x_setup(net, spi);
1030 mcp251x_gpio_restore(spi);
1031 } else {
1032 mcp251x_hw_wake(spi);
1033 }
1034 priv->force_quit = 0;
1035 if (priv->after_suspend & AFTER_SUSPEND_RESTART) {
1036 mcp251x_set_normal_mode(spi);
1037 } else if (priv->after_suspend & AFTER_SUSPEND_UP) {
1038 netif_device_attach(net);
1039 mcp251x_clean(net);
1040 mcp251x_set_normal_mode(spi);
1041 netif_wake_queue(net);
1042 } else {
1043 mcp251x_hw_sleep(spi);
1044 }
1045 priv->after_suspend = 0;
1046 }
1047
1048 if (priv->restart_tx) {
1049 priv->restart_tx = 0;
1050 mcp251x_write_reg(spi, TXBCTRL(0), 0);
1051 mcp251x_clean(net);
1052 netif_wake_queue(net);
1053 mcp251x_error_skb(net, CAN_ERR_RESTARTED, 0);
1054 }
1055 mutex_unlock(&priv->mcp_lock);
1056 }
1057
mcp251x_can_ist(int irq,void * dev_id)1058 static irqreturn_t mcp251x_can_ist(int irq, void *dev_id)
1059 {
1060 struct mcp251x_priv *priv = dev_id;
1061 struct spi_device *spi = priv->spi;
1062 struct net_device *net = priv->net;
1063
1064 mutex_lock(&priv->mcp_lock);
1065 while (!priv->force_quit) {
1066 enum can_state new_state;
1067 u8 intf, eflag;
1068 u8 clear_intf = 0;
1069 int can_id = 0, data1 = 0;
1070
1071 mcp251x_read_2regs(spi, CANINTF, &intf, &eflag);
1072
1073 /* receive buffer 0 */
1074 if (intf & CANINTF_RX0IF) {
1075 mcp251x_hw_rx(spi, 0);
1076 /* Free one buffer ASAP
1077 * (The MCP2515/25625 does this automatically.)
1078 */
1079 if (mcp251x_is_2510(spi))
1080 mcp251x_write_bits(spi, CANINTF,
1081 CANINTF_RX0IF, 0x00);
1082
1083 /* check if buffer 1 is already known to be full, no need to re-read */
1084 if (!(intf & CANINTF_RX1IF)) {
1085 u8 intf1, eflag1;
1086
1087 /* intf needs to be read again to avoid a race condition */
1088 mcp251x_read_2regs(spi, CANINTF, &intf1, &eflag1);
1089
1090 /* combine flags from both operations for error handling */
1091 intf |= intf1;
1092 eflag |= eflag1;
1093 }
1094 }
1095
1096 /* receive buffer 1 */
1097 if (intf & CANINTF_RX1IF) {
1098 mcp251x_hw_rx(spi, 1);
1099 /* The MCP2515/25625 does this automatically. */
1100 if (mcp251x_is_2510(spi))
1101 clear_intf |= CANINTF_RX1IF;
1102 }
1103
1104 /* mask out flags we don't care about */
1105 intf &= CANINTF_RX | CANINTF_TX | CANINTF_ERR;
1106
1107 /* any error or tx interrupt we need to clear? */
1108 if (intf & (CANINTF_ERR | CANINTF_TX))
1109 clear_intf |= intf & (CANINTF_ERR | CANINTF_TX);
1110 if (clear_intf)
1111 mcp251x_write_bits(spi, CANINTF, clear_intf, 0x00);
1112
1113 if (eflag & (EFLG_RX0OVR | EFLG_RX1OVR))
1114 mcp251x_write_bits(spi, EFLG, eflag, 0x00);
1115
1116 /* Update can state */
1117 if (eflag & EFLG_TXBO) {
1118 new_state = CAN_STATE_BUS_OFF;
1119 can_id |= CAN_ERR_BUSOFF;
1120 } else if (eflag & EFLG_TXEP) {
1121 new_state = CAN_STATE_ERROR_PASSIVE;
1122 can_id |= CAN_ERR_CRTL;
1123 data1 |= CAN_ERR_CRTL_TX_PASSIVE;
1124 } else if (eflag & EFLG_RXEP) {
1125 new_state = CAN_STATE_ERROR_PASSIVE;
1126 can_id |= CAN_ERR_CRTL;
1127 data1 |= CAN_ERR_CRTL_RX_PASSIVE;
1128 } else if (eflag & EFLG_TXWAR) {
1129 new_state = CAN_STATE_ERROR_WARNING;
1130 can_id |= CAN_ERR_CRTL;
1131 data1 |= CAN_ERR_CRTL_TX_WARNING;
1132 } else if (eflag & EFLG_RXWAR) {
1133 new_state = CAN_STATE_ERROR_WARNING;
1134 can_id |= CAN_ERR_CRTL;
1135 data1 |= CAN_ERR_CRTL_RX_WARNING;
1136 } else {
1137 new_state = CAN_STATE_ERROR_ACTIVE;
1138 }
1139
1140 /* Update can state statistics */
1141 switch (priv->can.state) {
1142 case CAN_STATE_ERROR_ACTIVE:
1143 if (new_state >= CAN_STATE_ERROR_WARNING &&
1144 new_state <= CAN_STATE_BUS_OFF)
1145 priv->can.can_stats.error_warning++;
1146 fallthrough;
1147 case CAN_STATE_ERROR_WARNING:
1148 if (new_state >= CAN_STATE_ERROR_PASSIVE &&
1149 new_state <= CAN_STATE_BUS_OFF)
1150 priv->can.can_stats.error_passive++;
1151 break;
1152 default:
1153 break;
1154 }
1155 priv->can.state = new_state;
1156
1157 if (intf & CANINTF_ERRIF) {
1158 /* Handle overflow counters */
1159 if (eflag & (EFLG_RX0OVR | EFLG_RX1OVR)) {
1160 if (eflag & EFLG_RX0OVR) {
1161 net->stats.rx_over_errors++;
1162 net->stats.rx_errors++;
1163 }
1164 if (eflag & EFLG_RX1OVR) {
1165 net->stats.rx_over_errors++;
1166 net->stats.rx_errors++;
1167 }
1168 can_id |= CAN_ERR_CRTL;
1169 data1 |= CAN_ERR_CRTL_RX_OVERFLOW;
1170 }
1171 mcp251x_error_skb(net, can_id, data1);
1172 }
1173
1174 if (priv->can.state == CAN_STATE_BUS_OFF) {
1175 if (priv->can.restart_ms == 0) {
1176 priv->force_quit = 1;
1177 priv->can.can_stats.bus_off++;
1178 can_bus_off(net);
1179 mcp251x_hw_sleep(spi);
1180 break;
1181 }
1182 }
1183
1184 if (intf == 0)
1185 break;
1186
1187 if (intf & CANINTF_TX) {
1188 if (priv->tx_busy) {
1189 net->stats.tx_packets++;
1190 net->stats.tx_bytes += can_get_echo_skb(net, 0,
1191 NULL);
1192 priv->tx_busy = false;
1193 }
1194 netif_wake_queue(net);
1195 }
1196 }
1197 mutex_unlock(&priv->mcp_lock);
1198 return IRQ_HANDLED;
1199 }
1200
mcp251x_open(struct net_device * net)1201 static int mcp251x_open(struct net_device *net)
1202 {
1203 struct mcp251x_priv *priv = netdev_priv(net);
1204 struct spi_device *spi = priv->spi;
1205 unsigned long flags = 0;
1206 int ret;
1207
1208 ret = open_candev(net);
1209 if (ret) {
1210 dev_err(&spi->dev, "unable to set initial baudrate!\n");
1211 return ret;
1212 }
1213
1214 mutex_lock(&priv->mcp_lock);
1215 mcp251x_power_enable(priv->transceiver, 1);
1216
1217 priv->force_quit = 0;
1218 priv->tx_skb = NULL;
1219 priv->tx_busy = false;
1220
1221 if (!dev_fwnode(&spi->dev))
1222 flags = IRQF_TRIGGER_FALLING;
1223
1224 ret = request_threaded_irq(spi->irq, NULL, mcp251x_can_ist,
1225 flags | IRQF_ONESHOT, dev_name(&spi->dev),
1226 priv);
1227 if (ret) {
1228 dev_err(&spi->dev, "failed to acquire irq %d\n", spi->irq);
1229 goto out_close;
1230 }
1231
1232 ret = mcp251x_hw_wake(spi);
1233 if (ret)
1234 goto out_free_irq;
1235 ret = mcp251x_setup(net, spi);
1236 if (ret)
1237 goto out_free_irq;
1238 ret = mcp251x_set_normal_mode(spi);
1239 if (ret)
1240 goto out_free_irq;
1241
1242 netif_wake_queue(net);
1243 mutex_unlock(&priv->mcp_lock);
1244
1245 return 0;
1246
1247 out_free_irq:
1248 free_irq(spi->irq, priv);
1249 mcp251x_hw_sleep(spi);
1250 out_close:
1251 mcp251x_power_enable(priv->transceiver, 0);
1252 close_candev(net);
1253 mutex_unlock(&priv->mcp_lock);
1254 return ret;
1255 }
1256
1257 static const struct net_device_ops mcp251x_netdev_ops = {
1258 .ndo_open = mcp251x_open,
1259 .ndo_stop = mcp251x_stop,
1260 .ndo_start_xmit = mcp251x_hard_start_xmit,
1261 .ndo_change_mtu = can_change_mtu,
1262 };
1263
1264 static const struct ethtool_ops mcp251x_ethtool_ops = {
1265 .get_ts_info = ethtool_op_get_ts_info,
1266 };
1267
1268 static const struct of_device_id mcp251x_of_match[] = {
1269 {
1270 .compatible = "microchip,mcp2510",
1271 .data = (void *)CAN_MCP251X_MCP2510,
1272 },
1273 {
1274 .compatible = "microchip,mcp2515",
1275 .data = (void *)CAN_MCP251X_MCP2515,
1276 },
1277 {
1278 .compatible = "microchip,mcp25625",
1279 .data = (void *)CAN_MCP251X_MCP25625,
1280 },
1281 { }
1282 };
1283 MODULE_DEVICE_TABLE(of, mcp251x_of_match);
1284
1285 static const struct spi_device_id mcp251x_id_table[] = {
1286 {
1287 .name = "mcp2510",
1288 .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP2510,
1289 },
1290 {
1291 .name = "mcp2515",
1292 .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP2515,
1293 },
1294 {
1295 .name = "mcp25625",
1296 .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP25625,
1297 },
1298 { }
1299 };
1300 MODULE_DEVICE_TABLE(spi, mcp251x_id_table);
1301
mcp251x_can_probe(struct spi_device * spi)1302 static int mcp251x_can_probe(struct spi_device *spi)
1303 {
1304 const void *match = device_get_match_data(&spi->dev);
1305 struct net_device *net;
1306 struct mcp251x_priv *priv;
1307 struct clk *clk;
1308 u32 freq;
1309 int ret;
1310
1311 clk = devm_clk_get_optional(&spi->dev, NULL);
1312 if (IS_ERR(clk))
1313 return PTR_ERR(clk);
1314
1315 freq = clk_get_rate(clk);
1316 if (freq == 0)
1317 device_property_read_u32(&spi->dev, "clock-frequency", &freq);
1318
1319 /* Sanity check */
1320 if (freq < 1000000 || freq > 25000000)
1321 return -ERANGE;
1322
1323 /* Allocate can/net device */
1324 net = alloc_candev(sizeof(struct mcp251x_priv), TX_ECHO_SKB_MAX);
1325 if (!net)
1326 return -ENOMEM;
1327
1328 ret = clk_prepare_enable(clk);
1329 if (ret)
1330 goto out_free;
1331
1332 net->netdev_ops = &mcp251x_netdev_ops;
1333 net->ethtool_ops = &mcp251x_ethtool_ops;
1334 net->flags |= IFF_ECHO;
1335
1336 priv = netdev_priv(net);
1337 priv->can.bittiming_const = &mcp251x_bittiming_const;
1338 priv->can.do_set_mode = mcp251x_do_set_mode;
1339 priv->can.clock.freq = freq / 2;
1340 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES |
1341 CAN_CTRLMODE_LOOPBACK | CAN_CTRLMODE_LISTENONLY;
1342 if (match)
1343 priv->model = (enum mcp251x_model)(uintptr_t)match;
1344 else
1345 priv->model = spi_get_device_id(spi)->driver_data;
1346 priv->net = net;
1347 priv->clk = clk;
1348
1349 spi_set_drvdata(spi, priv);
1350
1351 /* Configure the SPI bus */
1352 spi->bits_per_word = 8;
1353 if (mcp251x_is_2510(spi))
1354 spi->max_speed_hz = spi->max_speed_hz ? : 5 * 1000 * 1000;
1355 else
1356 spi->max_speed_hz = spi->max_speed_hz ? : 10 * 1000 * 1000;
1357 ret = spi_setup(spi);
1358 if (ret)
1359 goto out_clk;
1360
1361 priv->power = devm_regulator_get_optional(&spi->dev, "vdd");
1362 priv->transceiver = devm_regulator_get_optional(&spi->dev, "xceiver");
1363 if ((PTR_ERR(priv->power) == -EPROBE_DEFER) ||
1364 (PTR_ERR(priv->transceiver) == -EPROBE_DEFER)) {
1365 ret = -EPROBE_DEFER;
1366 goto out_clk;
1367 }
1368
1369 ret = mcp251x_power_enable(priv->power, 1);
1370 if (ret)
1371 goto out_clk;
1372
1373 priv->wq = alloc_workqueue("mcp251x_wq", WQ_FREEZABLE | WQ_MEM_RECLAIM,
1374 0);
1375 if (!priv->wq) {
1376 ret = -ENOMEM;
1377 goto out_clk;
1378 }
1379 INIT_WORK(&priv->tx_work, mcp251x_tx_work_handler);
1380 INIT_WORK(&priv->restart_work, mcp251x_restart_work_handler);
1381
1382 priv->spi = spi;
1383 mutex_init(&priv->mcp_lock);
1384
1385 priv->spi_tx_buf = devm_kzalloc(&spi->dev, SPI_TRANSFER_BUF_LEN,
1386 GFP_KERNEL);
1387 if (!priv->spi_tx_buf) {
1388 ret = -ENOMEM;
1389 goto error_probe;
1390 }
1391
1392 priv->spi_rx_buf = devm_kzalloc(&spi->dev, SPI_TRANSFER_BUF_LEN,
1393 GFP_KERNEL);
1394 if (!priv->spi_rx_buf) {
1395 ret = -ENOMEM;
1396 goto error_probe;
1397 }
1398
1399 SET_NETDEV_DEV(net, &spi->dev);
1400
1401 /* Here is OK to not lock the MCP, no one knows about it yet */
1402 ret = mcp251x_hw_probe(spi);
1403 if (ret) {
1404 if (ret == -ENODEV)
1405 dev_err(&spi->dev, "Cannot initialize MCP%x. Wrong wiring?\n",
1406 priv->model);
1407 goto error_probe;
1408 }
1409
1410 mcp251x_hw_sleep(spi);
1411
1412 ret = register_candev(net);
1413 if (ret)
1414 goto error_probe;
1415
1416 ret = mcp251x_gpio_setup(priv);
1417 if (ret)
1418 goto out_unregister_candev;
1419
1420 netdev_info(net, "MCP%x successfully initialized.\n", priv->model);
1421 return 0;
1422
1423 out_unregister_candev:
1424 unregister_candev(net);
1425
1426 error_probe:
1427 destroy_workqueue(priv->wq);
1428 priv->wq = NULL;
1429 mcp251x_power_enable(priv->power, 0);
1430
1431 out_clk:
1432 clk_disable_unprepare(clk);
1433
1434 out_free:
1435 free_candev(net);
1436
1437 dev_err(&spi->dev, "Probe failed, err=%d\n", -ret);
1438 return ret;
1439 }
1440
mcp251x_can_remove(struct spi_device * spi)1441 static void mcp251x_can_remove(struct spi_device *spi)
1442 {
1443 struct mcp251x_priv *priv = spi_get_drvdata(spi);
1444 struct net_device *net = priv->net;
1445
1446 unregister_candev(net);
1447
1448 mcp251x_power_enable(priv->power, 0);
1449
1450 destroy_workqueue(priv->wq);
1451 priv->wq = NULL;
1452
1453 clk_disable_unprepare(priv->clk);
1454
1455 free_candev(net);
1456 }
1457
mcp251x_can_suspend(struct device * dev)1458 static int __maybe_unused mcp251x_can_suspend(struct device *dev)
1459 {
1460 struct spi_device *spi = to_spi_device(dev);
1461 struct mcp251x_priv *priv = spi_get_drvdata(spi);
1462 struct net_device *net = priv->net;
1463
1464 priv->force_quit = 1;
1465 disable_irq(spi->irq);
1466 /* Note: at this point neither IST nor workqueues are running.
1467 * open/stop cannot be called anyway so locking is not needed
1468 */
1469 if (netif_running(net)) {
1470 netif_device_detach(net);
1471
1472 mcp251x_hw_sleep(spi);
1473 mcp251x_power_enable(priv->transceiver, 0);
1474 priv->after_suspend = AFTER_SUSPEND_UP;
1475 } else {
1476 priv->after_suspend = AFTER_SUSPEND_DOWN;
1477 }
1478
1479 mcp251x_power_enable(priv->power, 0);
1480 priv->after_suspend |= AFTER_SUSPEND_POWER;
1481
1482 return 0;
1483 }
1484
mcp251x_can_resume(struct device * dev)1485 static int __maybe_unused mcp251x_can_resume(struct device *dev)
1486 {
1487 struct spi_device *spi = to_spi_device(dev);
1488 struct mcp251x_priv *priv = spi_get_drvdata(spi);
1489
1490 if (priv->after_suspend & AFTER_SUSPEND_POWER)
1491 mcp251x_power_enable(priv->power, 1);
1492 if (priv->after_suspend & AFTER_SUSPEND_UP)
1493 mcp251x_power_enable(priv->transceiver, 1);
1494
1495 if (priv->after_suspend & (AFTER_SUSPEND_POWER | AFTER_SUSPEND_UP))
1496 queue_work(priv->wq, &priv->restart_work);
1497 else
1498 priv->after_suspend = 0;
1499
1500 priv->force_quit = 0;
1501 enable_irq(spi->irq);
1502 return 0;
1503 }
1504
1505 static SIMPLE_DEV_PM_OPS(mcp251x_can_pm_ops, mcp251x_can_suspend,
1506 mcp251x_can_resume);
1507
1508 static struct spi_driver mcp251x_can_driver = {
1509 .driver = {
1510 .name = DEVICE_NAME,
1511 .of_match_table = mcp251x_of_match,
1512 .pm = &mcp251x_can_pm_ops,
1513 },
1514 .id_table = mcp251x_id_table,
1515 .probe = mcp251x_can_probe,
1516 .remove = mcp251x_can_remove,
1517 };
1518 module_spi_driver(mcp251x_can_driver);
1519
1520 MODULE_AUTHOR("Chris Elston <celston@katalix.com>, "
1521 "Christian Pellegrin <chripell@evolware.org>");
1522 MODULE_DESCRIPTION("Microchip 251x/25625 CAN driver");
1523 MODULE_LICENSE("GPL v2");
1524
