Searched refs:TRCVMIDCCTLR1 (Results 1 – 3 of 3) sorted by relevance
55 ((offset >= TRCCIDCCTLR0) && (offset <= TRCVMIDCCTLR1))) { in etm4_cfg_map_reg_offset()74 CHECKREG(TRCVMIDCCTLR1, vmid_mask1); in etm4_cfg_map_reg_offset()
102 #define TRCVMIDCCTLR1 0x68C macro460 CASE_##op((val), TRCVMIDCCTLR1) \
498 etm4x_relaxed_write32(csa, config->vmid_mask1, TRCVMIDCCTLR1); in etm4_enable_hw()1752 state->trcvmidcctlr0 = etm4x_read32(csa, TRCVMIDCCTLR1); in __etm4_cpu_save()1876 etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR1); in __etm4_cpu_restore()
