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Searched refs:TEGRA30_CLK_PLL_P (Results 1 – 5 of 5) sorted by relevance

/Linux-v6.6/drivers/clk/tegra/
Dclk-tegra30.c540 { .con_id = "pll_p", .dt_id = TEGRA30_CLK_PLL_P },
800 [tegra_clk_pll_p] = { .dt_id = TEGRA30_CLK_PLL_P, .present = true },
1199 { TEGRA30_CLK_UARTA, TEGRA30_CLK_PLL_P, 408000000, 0 },
1200 { TEGRA30_CLK_UARTB, TEGRA30_CLK_PLL_P, 408000000, 0 },
1201 { TEGRA30_CLK_UARTC, TEGRA30_CLK_PLL_P, 408000000, 0 },
1202 { TEGRA30_CLK_UARTD, TEGRA30_CLK_PLL_P, 408000000, 0 },
1203 { TEGRA30_CLK_UARTE, TEGRA30_CLK_PLL_P, 408000000, 0 },
1211 { TEGRA30_CLK_SDMMC1, TEGRA30_CLK_PLL_P, 48000000, 0 },
1212 { TEGRA30_CLK_SDMMC2, TEGRA30_CLK_PLL_P, 48000000, 0 },
1213 { TEGRA30_CLK_SDMMC3, TEGRA30_CLK_PLL_P, 48000000, 0 },
[all …]
/Linux-v6.6/include/dt-bindings/clock/
Dtegra30-car.h206 #define TEGRA30_CLK_PLL_P 179 macro
/Linux-v6.6/arch/arm/boot/dts/nvidia/
Dtegra30.dtsi233 <&tegra_car TEGRA30_CLK_PLL_P>;
265 <&tegra_car TEGRA30_CLK_PLL_P>;
Dtegra30-asus-transformer-common.dtsi112 assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_P>;
Dtegra30-pegatron-chagall.dts94 assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_P>;