Searched refs:SOR_LANE_SEQ_CTL_TRIGGER (Results 1 – 2 of 2) sorted by relevance
157 #define SOR_LANE_SEQ_CTL_TRIGGER (1 << 31) macro
675 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | in tegra_sor_power_up_lanes()683 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) in tegra_sor_power_up_lanes()689 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0) in tegra_sor_power_up_lanes()707 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP | in tegra_sor_power_down_lanes()715 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) in tegra_sor_power_down_lanes()721 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0) in tegra_sor_power_down_lanes()2323 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | in tegra_sor_hdmi_enable()2329 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) in tegra_sor_hdmi_enable()
