Searched refs:SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT (Results 1 – 24 of 24) sorted by relevance
34 #define SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT 3 macro
665 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +694 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
570 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
560 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
772 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
730 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
1746 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +1907 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +2006 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
1814 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +1845 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
1840 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +1871 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1989 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +2021 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
2022 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +2052 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
1582 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +1681 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
1113 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
1057 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
2328 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +2360 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1688 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1570 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1415 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
6871 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +6924 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +6982 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +7020 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
1775 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 * 2 +
1817 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
6096 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +6146 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +6181 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
4132 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +4170 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9164 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +9220 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +9255 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
