Searched refs:SEC_CONTROL_REG (Results 1 – 1 of 1) sorted by relevance
54 #define SEC_CONTROL_REG 0x301200 macro424 reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_set_endian()432 writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG); in sec_set_endian()516 val = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_enable_clock_gate()518 writel_relaxed(val, qm->io_base + SEC_CONTROL_REG); in sec_enable_clock_gate()534 val = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_disable_clock_gate()536 writel_relaxed(val, qm->io_base + SEC_CONTROL_REG); in sec_disable_clock_gate()557 reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_engine_init()559 writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG); in sec_engine_init()634 val1 = readl(qm->io_base + SEC_CONTROL_REG); in sec_master_ooo_ctrl()[all …]
