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Searched refs:RX_DESC_NUM (Results 1 – 5 of 5) sorted by relevance

/Linux-v6.6/drivers/net/ethernet/moxa/
Dmoxart_ether.h64 #define RX_DESC_NUM 64 macro
65 #define RX_DESC_NUM_MASK (RX_DESC_NUM - 1)
303 dma_addr_t rx_mapping[RX_DESC_NUM];
306 unsigned char *rx_buf[RX_DESC_NUM];
314 unsigned char *tx_buf[RX_DESC_NUM];
Dmoxart_ether.c82 RX_REG_DESC_SIZE * RX_DESC_NUM, in moxart_mac_free_memory()
134 for (i = 0; i < RX_DESC_NUM; i++) { in moxart_mac_setup_desc_ring()
198 for (i = 0; i < RX_DESC_NUM; i++) in moxart_mac_stop()
507 RX_DESC_NUM, &priv->rx_base, in moxart_mac_probe()
521 priv->rx_buf_base = kmalloc_array(priv->rx_buf_size, RX_DESC_NUM, in moxart_mac_probe()
538 netif_napi_add_weight(ndev, &priv->napi, moxart_rx_poll, RX_DESC_NUM); in moxart_mac_probe()
/Linux-v6.6/drivers/net/ethernet/hisilicon/
Dhip04_eth.c153 #define RX_DESC_NUM 128 macro
156 #define RX_NEXT(N) (((N) + 1) & (RX_DESC_NUM-1))
236 unsigned char *rx_buf[RX_DESC_NUM];
237 dma_addr_t rx_phys[RX_DESC_NUM];
330 val = RX_DESC_NUM << PPE_CFG_RX_DEPTH_SHIFT; in hip04_config_fifo()
734 for (i = 0; i < RX_DESC_NUM; i++) { in hip04_mac_open()
771 for (i = 0; i < RX_DESC_NUM; i++) { in hip04_mac_stop()
867 for (i = 0; i < RX_DESC_NUM; i++) { in hip04_alloc_ring()
881 for (i = 0; i < RX_DESC_NUM; i++) in hip04_free_ring()
934 priv->chan = arg.args[1] * RX_DESC_NUM; in hip04_mac_probe()
Dhix5hd2_gmac.c172 #define RX_DESC_NUM 1024 macro
252 struct sk_buff *rx_skb[RX_DESC_NUM];
403 hix5hd2_set_desc_depth(priv, RX_DESC_NUM, TX_DESC_NUM); in hix5hd2_hw_init()
476 num = CIRC_SPACE(start, end, RX_DESC_NUM); in hix5hd2_rx_refill()
498 pos = dma_ring_incr(pos, RX_DESC_NUM); in hix5hd2_rx_refill()
520 num = CIRC_CNT(end, start, RX_DESC_NUM); in hix5hd2_rx()
555 pos = dma_ring_incr(pos, RX_DESC_NUM); in hix5hd2_rx()
799 for (i = 0; i < RX_DESC_NUM; i++) { in hix5hd2_free_dma_desc_rings()
998 priv->rx_fq.count = RX_DESC_NUM; in hix5hd2_init_hw_desc_queue()
999 priv->rx_bq.count = RX_DESC_NUM; in hix5hd2_init_hw_desc_queue()
/Linux-v6.6/Documentation/devicetree/bindings/net/
Dhisilicon-hip04-net.txt12 channel, recv channel start from channel * number (RX_DESC_NUM)
25 Each controller's recv channel start from channel * number (RX_DESC_NUM).