1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020  Realtek Corporation
3  */
4 
5 #ifndef __RTW89_CORE_H__
6 #define __RTW89_CORE_H__
7 
8 #include <linux/average.h>
9 #include <linux/bitfield.h>
10 #include <linux/firmware.h>
11 #include <linux/iopoll.h>
12 #include <linux/workqueue.h>
13 #include <net/mac80211.h>
14 
15 struct rtw89_dev;
16 struct rtw89_pci_info;
17 struct rtw89_mac_gen_def;
18 struct rtw89_phy_gen_def;
19 
20 extern const struct ieee80211_ops rtw89_ops;
21 
22 #define MASKBYTE0 0xff
23 #define MASKBYTE1 0xff00
24 #define MASKBYTE2 0xff0000
25 #define MASKBYTE3 0xff000000
26 #define MASKBYTE4 0xff00000000ULL
27 #define MASKHWORD 0xffff0000
28 #define MASKLWORD 0x0000ffff
29 #define MASKDWORD 0xffffffff
30 #define RFREG_MASK 0xfffff
31 #define INV_RF_DATA 0xffffffff
32 
33 #define RTW89_TRACK_WORK_PERIOD	round_jiffies_relative(HZ * 2)
34 #define RTW89_FORBID_BA_TIMER round_jiffies_relative(HZ * 4)
35 #define CFO_TRACK_MAX_USER 64
36 #define MAX_RSSI 110
37 #define RSSI_FACTOR 1
38 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI)
39 #define RTW89_TX_DIV_RSSI_RAW_TH (2 << RSSI_FACTOR)
40 #define RTW89_RADIOTAP_ROOM ALIGN(sizeof(struct ieee80211_radiotap_he), 64)
41 
42 #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0)
43 #define RTW89_HTC_VARIANT_HE 3
44 #define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2)
45 #define RTW89_HTC_VARIANT_HE_CID_OM 1
46 #define RTW89_HTC_VARIANT_HE_CID_CAS 6
47 #define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6)
48 
49 #define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6)
50 enum htc_om_channel_width {
51 	HTC_OM_CHANNEL_WIDTH_20 = 0,
52 	HTC_OM_CHANNEL_WIDTH_40 = 1,
53 	HTC_OM_CHANNEL_WIDTH_80 = 2,
54 	HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3,
55 };
56 #define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9)
57 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11)
58 #define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12)
59 #define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15)
60 #define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16)
61 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17)
62 
63 #define RTW89_TF_PAD GENMASK(11, 0)
64 #define RTW89_TF_BASIC_USER_INFO_SZ 6
65 
66 #define RTW89_GET_TF_USER_INFO_AID12(data)	\
67 	le32_get_bits(*((const __le32 *)(data)), GENMASK(11, 0))
68 #define RTW89_GET_TF_USER_INFO_RUA(data)	\
69 	le32_get_bits(*((const __le32 *)(data)), GENMASK(19, 12))
70 #define RTW89_GET_TF_USER_INFO_UL_MCS(data)	\
71 	le32_get_bits(*((const __le32 *)(data)), GENMASK(24, 21))
72 
73 enum rtw89_subband {
74 	RTW89_CH_2G = 0,
75 	RTW89_CH_5G_BAND_1 = 1,
76 	/* RTW89_CH_5G_BAND_2 = 2, unused */
77 	RTW89_CH_5G_BAND_3 = 3,
78 	RTW89_CH_5G_BAND_4 = 4,
79 
80 	RTW89_CH_6G_BAND_IDX0, /* Low */
81 	RTW89_CH_6G_BAND_IDX1, /* Low */
82 	RTW89_CH_6G_BAND_IDX2, /* Mid */
83 	RTW89_CH_6G_BAND_IDX3, /* Mid */
84 	RTW89_CH_6G_BAND_IDX4, /* High */
85 	RTW89_CH_6G_BAND_IDX5, /* High */
86 	RTW89_CH_6G_BAND_IDX6, /* Ultra-high */
87 	RTW89_CH_6G_BAND_IDX7, /* Ultra-high */
88 
89 	RTW89_SUBBAND_NR,
90 	RTW89_SUBBAND_2GHZ_5GHZ_NR = RTW89_CH_5G_BAND_4 + 1,
91 };
92 
93 enum rtw89_gain_offset {
94 	RTW89_GAIN_OFFSET_2G_CCK,
95 	RTW89_GAIN_OFFSET_2G_OFDM,
96 	RTW89_GAIN_OFFSET_5G_LOW,
97 	RTW89_GAIN_OFFSET_5G_MID,
98 	RTW89_GAIN_OFFSET_5G_HIGH,
99 
100 	RTW89_GAIN_OFFSET_NR,
101 };
102 
103 enum rtw89_hci_type {
104 	RTW89_HCI_TYPE_PCIE,
105 	RTW89_HCI_TYPE_USB,
106 	RTW89_HCI_TYPE_SDIO,
107 };
108 
109 enum rtw89_core_chip_id {
110 	RTL8852A,
111 	RTL8852B,
112 	RTL8852C,
113 	RTL8851B,
114 	RTL8922A,
115 };
116 
117 enum rtw89_chip_gen {
118 	RTW89_CHIP_AX,
119 	RTW89_CHIP_BE,
120 
121 	RTW89_CHIP_GEN_NUM,
122 };
123 
124 enum rtw89_cv {
125 	CHIP_CAV,
126 	CHIP_CBV,
127 	CHIP_CCV,
128 	CHIP_CDV,
129 	CHIP_CEV,
130 	CHIP_CFV,
131 	CHIP_CV_MAX,
132 	CHIP_CV_INVALID = CHIP_CV_MAX,
133 };
134 
135 enum rtw89_bacam_ver {
136 	RTW89_BACAM_V0,
137 	RTW89_BACAM_V1,
138 
139 	RTW89_BACAM_V0_EXT = 99,
140 };
141 
142 enum rtw89_core_tx_type {
143 	RTW89_CORE_TX_TYPE_DATA,
144 	RTW89_CORE_TX_TYPE_MGMT,
145 	RTW89_CORE_TX_TYPE_FWCMD,
146 };
147 
148 enum rtw89_core_rx_type {
149 	RTW89_CORE_RX_TYPE_WIFI		= 0,
150 	RTW89_CORE_RX_TYPE_PPDU_STAT	= 1,
151 	RTW89_CORE_RX_TYPE_CHAN_INFO	= 2,
152 	RTW89_CORE_RX_TYPE_BB_SCOPE	= 3,
153 	RTW89_CORE_RX_TYPE_F2P_TXCMD	= 4,
154 	RTW89_CORE_RX_TYPE_SS2FW	= 5,
155 	RTW89_CORE_RX_TYPE_TX_REPORT	= 6,
156 	RTW89_CORE_RX_TYPE_TX_REL_HOST	= 7,
157 	RTW89_CORE_RX_TYPE_DFS_REPORT	= 8,
158 	RTW89_CORE_RX_TYPE_TX_REL_CPU	= 9,
159 	RTW89_CORE_RX_TYPE_C2H		= 10,
160 	RTW89_CORE_RX_TYPE_CSI		= 11,
161 	RTW89_CORE_RX_TYPE_CQI		= 12,
162 	RTW89_CORE_RX_TYPE_H2C		= 13,
163 	RTW89_CORE_RX_TYPE_FWDL		= 14,
164 };
165 
166 enum rtw89_txq_flags {
167 	RTW89_TXQ_F_AMPDU		= 0,
168 	RTW89_TXQ_F_BLOCK_BA		= 1,
169 	RTW89_TXQ_F_FORBID_BA		= 2,
170 };
171 
172 enum rtw89_net_type {
173 	RTW89_NET_TYPE_NO_LINK		= 0,
174 	RTW89_NET_TYPE_AD_HOC		= 1,
175 	RTW89_NET_TYPE_INFRA		= 2,
176 	RTW89_NET_TYPE_AP_MODE		= 3,
177 };
178 
179 enum rtw89_wifi_role {
180 	RTW89_WIFI_ROLE_NONE,
181 	RTW89_WIFI_ROLE_STATION,
182 	RTW89_WIFI_ROLE_AP,
183 	RTW89_WIFI_ROLE_AP_VLAN,
184 	RTW89_WIFI_ROLE_ADHOC,
185 	RTW89_WIFI_ROLE_ADHOC_MASTER,
186 	RTW89_WIFI_ROLE_MESH_POINT,
187 	RTW89_WIFI_ROLE_MONITOR,
188 	RTW89_WIFI_ROLE_P2P_DEVICE,
189 	RTW89_WIFI_ROLE_P2P_CLIENT,
190 	RTW89_WIFI_ROLE_P2P_GO,
191 	RTW89_WIFI_ROLE_NAN,
192 	RTW89_WIFI_ROLE_MLME_MAX
193 };
194 
195 enum rtw89_upd_mode {
196 	RTW89_ROLE_CREATE,
197 	RTW89_ROLE_REMOVE,
198 	RTW89_ROLE_TYPE_CHANGE,
199 	RTW89_ROLE_INFO_CHANGE,
200 	RTW89_ROLE_CON_DISCONN,
201 	RTW89_ROLE_BAND_SW,
202 	RTW89_ROLE_FW_RESTORE,
203 };
204 
205 enum rtw89_self_role {
206 	RTW89_SELF_ROLE_CLIENT,
207 	RTW89_SELF_ROLE_AP,
208 	RTW89_SELF_ROLE_AP_CLIENT
209 };
210 
211 enum rtw89_msk_sO_el {
212 	RTW89_NO_MSK,
213 	RTW89_SMA,
214 	RTW89_TMA,
215 	RTW89_BSSID
216 };
217 
218 enum rtw89_sch_tx_sel {
219 	RTW89_SCH_TX_SEL_ALL,
220 	RTW89_SCH_TX_SEL_HIQ,
221 	RTW89_SCH_TX_SEL_MG0,
222 	RTW89_SCH_TX_SEL_MACID,
223 };
224 
225 /* RTW89_ADDR_CAM_SEC_NONE	: not enabled
226  * RTW89_ADDR_CAM_SEC_ALL_UNI	: 0 - 6 unicast
227  * RTW89_ADDR_CAM_SEC_NORMAL	: 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP
228  * RTW89_ADDR_CAM_SEC_4GROUP	: 0 - 1 unicast, 2 - 5 group, 6 BIP
229  */
230 enum rtw89_add_cam_sec_mode {
231 	RTW89_ADDR_CAM_SEC_NONE		= 0,
232 	RTW89_ADDR_CAM_SEC_ALL_UNI	= 1,
233 	RTW89_ADDR_CAM_SEC_NORMAL	= 2,
234 	RTW89_ADDR_CAM_SEC_4GROUP	= 3,
235 };
236 
237 enum rtw89_sec_key_type {
238 	RTW89_SEC_KEY_TYPE_NONE		= 0,
239 	RTW89_SEC_KEY_TYPE_WEP40	= 1,
240 	RTW89_SEC_KEY_TYPE_WEP104	= 2,
241 	RTW89_SEC_KEY_TYPE_TKIP		= 3,
242 	RTW89_SEC_KEY_TYPE_WAPI		= 4,
243 	RTW89_SEC_KEY_TYPE_GCMSMS4	= 5,
244 	RTW89_SEC_KEY_TYPE_CCMP128	= 6,
245 	RTW89_SEC_KEY_TYPE_CCMP256	= 7,
246 	RTW89_SEC_KEY_TYPE_GCMP128	= 8,
247 	RTW89_SEC_KEY_TYPE_GCMP256	= 9,
248 	RTW89_SEC_KEY_TYPE_BIP_CCMP128	= 10,
249 };
250 
251 enum rtw89_port {
252 	RTW89_PORT_0 = 0,
253 	RTW89_PORT_1 = 1,
254 	RTW89_PORT_2 = 2,
255 	RTW89_PORT_3 = 3,
256 	RTW89_PORT_4 = 4,
257 	RTW89_PORT_NUM
258 };
259 
260 enum rtw89_band {
261 	RTW89_BAND_2G = 0,
262 	RTW89_BAND_5G = 1,
263 	RTW89_BAND_6G = 2,
264 	RTW89_BAND_NUM,
265 };
266 
267 enum rtw89_hw_rate {
268 	RTW89_HW_RATE_CCK1	= 0x0,
269 	RTW89_HW_RATE_CCK2	= 0x1,
270 	RTW89_HW_RATE_CCK5_5	= 0x2,
271 	RTW89_HW_RATE_CCK11	= 0x3,
272 	RTW89_HW_RATE_OFDM6	= 0x4,
273 	RTW89_HW_RATE_OFDM9	= 0x5,
274 	RTW89_HW_RATE_OFDM12	= 0x6,
275 	RTW89_HW_RATE_OFDM18	= 0x7,
276 	RTW89_HW_RATE_OFDM24	= 0x8,
277 	RTW89_HW_RATE_OFDM36	= 0x9,
278 	RTW89_HW_RATE_OFDM48	= 0xA,
279 	RTW89_HW_RATE_OFDM54	= 0xB,
280 	RTW89_HW_RATE_MCS0	= 0x80,
281 	RTW89_HW_RATE_MCS1	= 0x81,
282 	RTW89_HW_RATE_MCS2	= 0x82,
283 	RTW89_HW_RATE_MCS3	= 0x83,
284 	RTW89_HW_RATE_MCS4	= 0x84,
285 	RTW89_HW_RATE_MCS5	= 0x85,
286 	RTW89_HW_RATE_MCS6	= 0x86,
287 	RTW89_HW_RATE_MCS7	= 0x87,
288 	RTW89_HW_RATE_MCS8	= 0x88,
289 	RTW89_HW_RATE_MCS9	= 0x89,
290 	RTW89_HW_RATE_MCS10	= 0x8A,
291 	RTW89_HW_RATE_MCS11	= 0x8B,
292 	RTW89_HW_RATE_MCS12	= 0x8C,
293 	RTW89_HW_RATE_MCS13	= 0x8D,
294 	RTW89_HW_RATE_MCS14	= 0x8E,
295 	RTW89_HW_RATE_MCS15	= 0x8F,
296 	RTW89_HW_RATE_MCS16	= 0x90,
297 	RTW89_HW_RATE_MCS17	= 0x91,
298 	RTW89_HW_RATE_MCS18	= 0x92,
299 	RTW89_HW_RATE_MCS19	= 0x93,
300 	RTW89_HW_RATE_MCS20	= 0x94,
301 	RTW89_HW_RATE_MCS21	= 0x95,
302 	RTW89_HW_RATE_MCS22	= 0x96,
303 	RTW89_HW_RATE_MCS23	= 0x97,
304 	RTW89_HW_RATE_MCS24	= 0x98,
305 	RTW89_HW_RATE_MCS25	= 0x99,
306 	RTW89_HW_RATE_MCS26	= 0x9A,
307 	RTW89_HW_RATE_MCS27	= 0x9B,
308 	RTW89_HW_RATE_MCS28	= 0x9C,
309 	RTW89_HW_RATE_MCS29	= 0x9D,
310 	RTW89_HW_RATE_MCS30	= 0x9E,
311 	RTW89_HW_RATE_MCS31	= 0x9F,
312 	RTW89_HW_RATE_VHT_NSS1_MCS0	= 0x100,
313 	RTW89_HW_RATE_VHT_NSS1_MCS1	= 0x101,
314 	RTW89_HW_RATE_VHT_NSS1_MCS2	= 0x102,
315 	RTW89_HW_RATE_VHT_NSS1_MCS3	= 0x103,
316 	RTW89_HW_RATE_VHT_NSS1_MCS4	= 0x104,
317 	RTW89_HW_RATE_VHT_NSS1_MCS5	= 0x105,
318 	RTW89_HW_RATE_VHT_NSS1_MCS6	= 0x106,
319 	RTW89_HW_RATE_VHT_NSS1_MCS7	= 0x107,
320 	RTW89_HW_RATE_VHT_NSS1_MCS8	= 0x108,
321 	RTW89_HW_RATE_VHT_NSS1_MCS9	= 0x109,
322 	RTW89_HW_RATE_VHT_NSS2_MCS0	= 0x110,
323 	RTW89_HW_RATE_VHT_NSS2_MCS1	= 0x111,
324 	RTW89_HW_RATE_VHT_NSS2_MCS2	= 0x112,
325 	RTW89_HW_RATE_VHT_NSS2_MCS3	= 0x113,
326 	RTW89_HW_RATE_VHT_NSS2_MCS4	= 0x114,
327 	RTW89_HW_RATE_VHT_NSS2_MCS5	= 0x115,
328 	RTW89_HW_RATE_VHT_NSS2_MCS6	= 0x116,
329 	RTW89_HW_RATE_VHT_NSS2_MCS7	= 0x117,
330 	RTW89_HW_RATE_VHT_NSS2_MCS8	= 0x118,
331 	RTW89_HW_RATE_VHT_NSS2_MCS9	= 0x119,
332 	RTW89_HW_RATE_VHT_NSS3_MCS0	= 0x120,
333 	RTW89_HW_RATE_VHT_NSS3_MCS1	= 0x121,
334 	RTW89_HW_RATE_VHT_NSS3_MCS2	= 0x122,
335 	RTW89_HW_RATE_VHT_NSS3_MCS3	= 0x123,
336 	RTW89_HW_RATE_VHT_NSS3_MCS4	= 0x124,
337 	RTW89_HW_RATE_VHT_NSS3_MCS5	= 0x125,
338 	RTW89_HW_RATE_VHT_NSS3_MCS6	= 0x126,
339 	RTW89_HW_RATE_VHT_NSS3_MCS7	= 0x127,
340 	RTW89_HW_RATE_VHT_NSS3_MCS8	= 0x128,
341 	RTW89_HW_RATE_VHT_NSS3_MCS9	= 0x129,
342 	RTW89_HW_RATE_VHT_NSS4_MCS0	= 0x130,
343 	RTW89_HW_RATE_VHT_NSS4_MCS1	= 0x131,
344 	RTW89_HW_RATE_VHT_NSS4_MCS2	= 0x132,
345 	RTW89_HW_RATE_VHT_NSS4_MCS3	= 0x133,
346 	RTW89_HW_RATE_VHT_NSS4_MCS4	= 0x134,
347 	RTW89_HW_RATE_VHT_NSS4_MCS5	= 0x135,
348 	RTW89_HW_RATE_VHT_NSS4_MCS6	= 0x136,
349 	RTW89_HW_RATE_VHT_NSS4_MCS7	= 0x137,
350 	RTW89_HW_RATE_VHT_NSS4_MCS8	= 0x138,
351 	RTW89_HW_RATE_VHT_NSS4_MCS9	= 0x139,
352 	RTW89_HW_RATE_HE_NSS1_MCS0	= 0x180,
353 	RTW89_HW_RATE_HE_NSS1_MCS1	= 0x181,
354 	RTW89_HW_RATE_HE_NSS1_MCS2	= 0x182,
355 	RTW89_HW_RATE_HE_NSS1_MCS3	= 0x183,
356 	RTW89_HW_RATE_HE_NSS1_MCS4	= 0x184,
357 	RTW89_HW_RATE_HE_NSS1_MCS5	= 0x185,
358 	RTW89_HW_RATE_HE_NSS1_MCS6	= 0x186,
359 	RTW89_HW_RATE_HE_NSS1_MCS7	= 0x187,
360 	RTW89_HW_RATE_HE_NSS1_MCS8	= 0x188,
361 	RTW89_HW_RATE_HE_NSS1_MCS9	= 0x189,
362 	RTW89_HW_RATE_HE_NSS1_MCS10	= 0x18A,
363 	RTW89_HW_RATE_HE_NSS1_MCS11	= 0x18B,
364 	RTW89_HW_RATE_HE_NSS2_MCS0	= 0x190,
365 	RTW89_HW_RATE_HE_NSS2_MCS1	= 0x191,
366 	RTW89_HW_RATE_HE_NSS2_MCS2	= 0x192,
367 	RTW89_HW_RATE_HE_NSS2_MCS3	= 0x193,
368 	RTW89_HW_RATE_HE_NSS2_MCS4	= 0x194,
369 	RTW89_HW_RATE_HE_NSS2_MCS5	= 0x195,
370 	RTW89_HW_RATE_HE_NSS2_MCS6	= 0x196,
371 	RTW89_HW_RATE_HE_NSS2_MCS7	= 0x197,
372 	RTW89_HW_RATE_HE_NSS2_MCS8	= 0x198,
373 	RTW89_HW_RATE_HE_NSS2_MCS9	= 0x199,
374 	RTW89_HW_RATE_HE_NSS2_MCS10	= 0x19A,
375 	RTW89_HW_RATE_HE_NSS2_MCS11	= 0x19B,
376 	RTW89_HW_RATE_HE_NSS3_MCS0	= 0x1A0,
377 	RTW89_HW_RATE_HE_NSS3_MCS1	= 0x1A1,
378 	RTW89_HW_RATE_HE_NSS3_MCS2	= 0x1A2,
379 	RTW89_HW_RATE_HE_NSS3_MCS3	= 0x1A3,
380 	RTW89_HW_RATE_HE_NSS3_MCS4	= 0x1A4,
381 	RTW89_HW_RATE_HE_NSS3_MCS5	= 0x1A5,
382 	RTW89_HW_RATE_HE_NSS3_MCS6	= 0x1A6,
383 	RTW89_HW_RATE_HE_NSS3_MCS7	= 0x1A7,
384 	RTW89_HW_RATE_HE_NSS3_MCS8	= 0x1A8,
385 	RTW89_HW_RATE_HE_NSS3_MCS9	= 0x1A9,
386 	RTW89_HW_RATE_HE_NSS3_MCS10	= 0x1AA,
387 	RTW89_HW_RATE_HE_NSS3_MCS11	= 0x1AB,
388 	RTW89_HW_RATE_HE_NSS4_MCS0	= 0x1B0,
389 	RTW89_HW_RATE_HE_NSS4_MCS1	= 0x1B1,
390 	RTW89_HW_RATE_HE_NSS4_MCS2	= 0x1B2,
391 	RTW89_HW_RATE_HE_NSS4_MCS3	= 0x1B3,
392 	RTW89_HW_RATE_HE_NSS4_MCS4	= 0x1B4,
393 	RTW89_HW_RATE_HE_NSS4_MCS5	= 0x1B5,
394 	RTW89_HW_RATE_HE_NSS4_MCS6	= 0x1B6,
395 	RTW89_HW_RATE_HE_NSS4_MCS7	= 0x1B7,
396 	RTW89_HW_RATE_HE_NSS4_MCS8	= 0x1B8,
397 	RTW89_HW_RATE_HE_NSS4_MCS9	= 0x1B9,
398 	RTW89_HW_RATE_HE_NSS4_MCS10	= 0x1BA,
399 	RTW89_HW_RATE_HE_NSS4_MCS11	= 0x1BB,
400 
401 	RTW89_HW_RATE_V1_MCS0		= 0x100,
402 	RTW89_HW_RATE_V1_MCS1		= 0x101,
403 	RTW89_HW_RATE_V1_MCS2		= 0x102,
404 	RTW89_HW_RATE_V1_MCS3		= 0x103,
405 	RTW89_HW_RATE_V1_MCS4		= 0x104,
406 	RTW89_HW_RATE_V1_MCS5		= 0x105,
407 	RTW89_HW_RATE_V1_MCS6		= 0x106,
408 	RTW89_HW_RATE_V1_MCS7		= 0x107,
409 	RTW89_HW_RATE_V1_MCS8		= 0x108,
410 	RTW89_HW_RATE_V1_MCS9		= 0x109,
411 	RTW89_HW_RATE_V1_MCS10		= 0x10A,
412 	RTW89_HW_RATE_V1_MCS11		= 0x10B,
413 	RTW89_HW_RATE_V1_MCS12		= 0x10C,
414 	RTW89_HW_RATE_V1_MCS13		= 0x10D,
415 	RTW89_HW_RATE_V1_MCS14		= 0x10E,
416 	RTW89_HW_RATE_V1_MCS15		= 0x10F,
417 	RTW89_HW_RATE_V1_MCS16		= 0x110,
418 	RTW89_HW_RATE_V1_MCS17		= 0x111,
419 	RTW89_HW_RATE_V1_MCS18		= 0x112,
420 	RTW89_HW_RATE_V1_MCS19		= 0x113,
421 	RTW89_HW_RATE_V1_MCS20		= 0x114,
422 	RTW89_HW_RATE_V1_MCS21		= 0x115,
423 	RTW89_HW_RATE_V1_MCS22		= 0x116,
424 	RTW89_HW_RATE_V1_MCS23		= 0x117,
425 	RTW89_HW_RATE_V1_MCS24		= 0x118,
426 	RTW89_HW_RATE_V1_MCS25		= 0x119,
427 	RTW89_HW_RATE_V1_MCS26		= 0x11A,
428 	RTW89_HW_RATE_V1_MCS27		= 0x11B,
429 	RTW89_HW_RATE_V1_MCS28		= 0x11C,
430 	RTW89_HW_RATE_V1_MCS29		= 0x11D,
431 	RTW89_HW_RATE_V1_MCS30		= 0x11E,
432 	RTW89_HW_RATE_V1_MCS31		= 0x11F,
433 	RTW89_HW_RATE_V1_VHT_NSS1_MCS0	= 0x200,
434 	RTW89_HW_RATE_V1_VHT_NSS1_MCS1	= 0x201,
435 	RTW89_HW_RATE_V1_VHT_NSS1_MCS2	= 0x202,
436 	RTW89_HW_RATE_V1_VHT_NSS1_MCS3	= 0x203,
437 	RTW89_HW_RATE_V1_VHT_NSS1_MCS4	= 0x204,
438 	RTW89_HW_RATE_V1_VHT_NSS1_MCS5	= 0x205,
439 	RTW89_HW_RATE_V1_VHT_NSS1_MCS6	= 0x206,
440 	RTW89_HW_RATE_V1_VHT_NSS1_MCS7	= 0x207,
441 	RTW89_HW_RATE_V1_VHT_NSS1_MCS8	= 0x208,
442 	RTW89_HW_RATE_V1_VHT_NSS1_MCS9	= 0x209,
443 	RTW89_HW_RATE_V1_VHT_NSS1_MCS10	= 0x20A,
444 	RTW89_HW_RATE_V1_VHT_NSS1_MCS11	= 0x20B,
445 	RTW89_HW_RATE_V1_VHT_NSS2_MCS0	= 0x220,
446 	RTW89_HW_RATE_V1_VHT_NSS2_MCS1	= 0x221,
447 	RTW89_HW_RATE_V1_VHT_NSS2_MCS2	= 0x222,
448 	RTW89_HW_RATE_V1_VHT_NSS2_MCS3	= 0x223,
449 	RTW89_HW_RATE_V1_VHT_NSS2_MCS4	= 0x224,
450 	RTW89_HW_RATE_V1_VHT_NSS2_MCS5	= 0x225,
451 	RTW89_HW_RATE_V1_VHT_NSS2_MCS6	= 0x226,
452 	RTW89_HW_RATE_V1_VHT_NSS2_MCS7	= 0x227,
453 	RTW89_HW_RATE_V1_VHT_NSS2_MCS8	= 0x228,
454 	RTW89_HW_RATE_V1_VHT_NSS2_MCS9	= 0x229,
455 	RTW89_HW_RATE_V1_VHT_NSS2_MCS10	= 0x22A,
456 	RTW89_HW_RATE_V1_VHT_NSS2_MCS11	= 0x22B,
457 	RTW89_HW_RATE_V1_VHT_NSS3_MCS0	= 0x240,
458 	RTW89_HW_RATE_V1_VHT_NSS3_MCS1	= 0x241,
459 	RTW89_HW_RATE_V1_VHT_NSS3_MCS2	= 0x242,
460 	RTW89_HW_RATE_V1_VHT_NSS3_MCS3	= 0x243,
461 	RTW89_HW_RATE_V1_VHT_NSS3_MCS4	= 0x244,
462 	RTW89_HW_RATE_V1_VHT_NSS3_MCS5	= 0x245,
463 	RTW89_HW_RATE_V1_VHT_NSS3_MCS6	= 0x246,
464 	RTW89_HW_RATE_V1_VHT_NSS3_MCS7	= 0x247,
465 	RTW89_HW_RATE_V1_VHT_NSS3_MCS8	= 0x248,
466 	RTW89_HW_RATE_V1_VHT_NSS3_MCS9	= 0x249,
467 	RTW89_HW_RATE_V1_VHT_NSS3_MCS10	= 0x24A,
468 	RTW89_HW_RATE_V1_VHT_NSS3_MCS11	= 0x24B,
469 	RTW89_HW_RATE_V1_VHT_NSS4_MCS0	= 0x260,
470 	RTW89_HW_RATE_V1_VHT_NSS4_MCS1	= 0x261,
471 	RTW89_HW_RATE_V1_VHT_NSS4_MCS2	= 0x262,
472 	RTW89_HW_RATE_V1_VHT_NSS4_MCS3	= 0x263,
473 	RTW89_HW_RATE_V1_VHT_NSS4_MCS4	= 0x264,
474 	RTW89_HW_RATE_V1_VHT_NSS4_MCS5	= 0x265,
475 	RTW89_HW_RATE_V1_VHT_NSS4_MCS6	= 0x266,
476 	RTW89_HW_RATE_V1_VHT_NSS4_MCS7	= 0x267,
477 	RTW89_HW_RATE_V1_VHT_NSS4_MCS8	= 0x268,
478 	RTW89_HW_RATE_V1_VHT_NSS4_MCS9	= 0x269,
479 	RTW89_HW_RATE_V1_VHT_NSS4_MCS10	= 0x26A,
480 	RTW89_HW_RATE_V1_VHT_NSS4_MCS11	= 0x26B,
481 	RTW89_HW_RATE_V1_HE_NSS1_MCS0	= 0x300,
482 	RTW89_HW_RATE_V1_HE_NSS1_MCS1	= 0x301,
483 	RTW89_HW_RATE_V1_HE_NSS1_MCS2	= 0x302,
484 	RTW89_HW_RATE_V1_HE_NSS1_MCS3	= 0x303,
485 	RTW89_HW_RATE_V1_HE_NSS1_MCS4	= 0x304,
486 	RTW89_HW_RATE_V1_HE_NSS1_MCS5	= 0x305,
487 	RTW89_HW_RATE_V1_HE_NSS1_MCS6	= 0x306,
488 	RTW89_HW_RATE_V1_HE_NSS1_MCS7	= 0x307,
489 	RTW89_HW_RATE_V1_HE_NSS1_MCS8	= 0x308,
490 	RTW89_HW_RATE_V1_HE_NSS1_MCS9	= 0x309,
491 	RTW89_HW_RATE_V1_HE_NSS1_MCS10	= 0x30A,
492 	RTW89_HW_RATE_V1_HE_NSS1_MCS11	= 0x30B,
493 	RTW89_HW_RATE_V1_HE_NSS2_MCS0	= 0x320,
494 	RTW89_HW_RATE_V1_HE_NSS2_MCS1	= 0x321,
495 	RTW89_HW_RATE_V1_HE_NSS2_MCS2	= 0x322,
496 	RTW89_HW_RATE_V1_HE_NSS2_MCS3	= 0x323,
497 	RTW89_HW_RATE_V1_HE_NSS2_MCS4	= 0x324,
498 	RTW89_HW_RATE_V1_HE_NSS2_MCS5	= 0x325,
499 	RTW89_HW_RATE_V1_HE_NSS2_MCS6	= 0x326,
500 	RTW89_HW_RATE_V1_HE_NSS2_MCS7	= 0x327,
501 	RTW89_HW_RATE_V1_HE_NSS2_MCS8	= 0x328,
502 	RTW89_HW_RATE_V1_HE_NSS2_MCS9	= 0x329,
503 	RTW89_HW_RATE_V1_HE_NSS2_MCS10	= 0x32A,
504 	RTW89_HW_RATE_V1_HE_NSS2_MCS11	= 0x32B,
505 	RTW89_HW_RATE_V1_HE_NSS3_MCS0	= 0x340,
506 	RTW89_HW_RATE_V1_HE_NSS3_MCS1	= 0x341,
507 	RTW89_HW_RATE_V1_HE_NSS3_MCS2	= 0x342,
508 	RTW89_HW_RATE_V1_HE_NSS3_MCS3	= 0x343,
509 	RTW89_HW_RATE_V1_HE_NSS3_MCS4	= 0x344,
510 	RTW89_HW_RATE_V1_HE_NSS3_MCS5	= 0x345,
511 	RTW89_HW_RATE_V1_HE_NSS3_MCS6	= 0x346,
512 	RTW89_HW_RATE_V1_HE_NSS3_MCS7	= 0x347,
513 	RTW89_HW_RATE_V1_HE_NSS3_MCS8	= 0x348,
514 	RTW89_HW_RATE_V1_HE_NSS3_MCS9	= 0x349,
515 	RTW89_HW_RATE_V1_HE_NSS3_MCS10	= 0x34A,
516 	RTW89_HW_RATE_V1_HE_NSS3_MCS11	= 0x34B,
517 	RTW89_HW_RATE_V1_HE_NSS4_MCS0	= 0x360,
518 	RTW89_HW_RATE_V1_HE_NSS4_MCS1	= 0x361,
519 	RTW89_HW_RATE_V1_HE_NSS4_MCS2	= 0x362,
520 	RTW89_HW_RATE_V1_HE_NSS4_MCS3	= 0x363,
521 	RTW89_HW_RATE_V1_HE_NSS4_MCS4	= 0x364,
522 	RTW89_HW_RATE_V1_HE_NSS4_MCS5	= 0x365,
523 	RTW89_HW_RATE_V1_HE_NSS4_MCS6	= 0x366,
524 	RTW89_HW_RATE_V1_HE_NSS4_MCS7	= 0x367,
525 	RTW89_HW_RATE_V1_HE_NSS4_MCS8	= 0x368,
526 	RTW89_HW_RATE_V1_HE_NSS4_MCS9	= 0x369,
527 	RTW89_HW_RATE_V1_HE_NSS4_MCS10	= 0x36A,
528 	RTW89_HW_RATE_V1_HE_NSS4_MCS11	= 0x36B,
529 	RTW89_HW_RATE_V1_EHT_NSS1_MCS0	= 0x400,
530 	RTW89_HW_RATE_V1_EHT_NSS1_MCS1	= 0x401,
531 	RTW89_HW_RATE_V1_EHT_NSS1_MCS2	= 0x402,
532 	RTW89_HW_RATE_V1_EHT_NSS1_MCS3	= 0x403,
533 	RTW89_HW_RATE_V1_EHT_NSS1_MCS4	= 0x404,
534 	RTW89_HW_RATE_V1_EHT_NSS1_MCS5	= 0x405,
535 	RTW89_HW_RATE_V1_EHT_NSS1_MCS6	= 0x406,
536 	RTW89_HW_RATE_V1_EHT_NSS1_MCS7	= 0x407,
537 	RTW89_HW_RATE_V1_EHT_NSS1_MCS8	= 0x408,
538 	RTW89_HW_RATE_V1_EHT_NSS1_MCS9	= 0x409,
539 	RTW89_HW_RATE_V1_EHT_NSS1_MCS10	= 0x40A,
540 	RTW89_HW_RATE_V1_EHT_NSS1_MCS11	= 0x40B,
541 	RTW89_HW_RATE_V1_EHT_NSS1_MCS12	= 0x40C,
542 	RTW89_HW_RATE_V1_EHT_NSS1_MCS13	= 0x40D,
543 	RTW89_HW_RATE_V1_EHT_NSS1_MCS14	= 0x40E,
544 	RTW89_HW_RATE_V1_EHT_NSS1_MCS15	= 0x40F,
545 	RTW89_HW_RATE_V1_EHT_NSS2_MCS0	= 0x420,
546 	RTW89_HW_RATE_V1_EHT_NSS2_MCS1	= 0x421,
547 	RTW89_HW_RATE_V1_EHT_NSS2_MCS2	= 0x422,
548 	RTW89_HW_RATE_V1_EHT_NSS2_MCS3	= 0x423,
549 	RTW89_HW_RATE_V1_EHT_NSS2_MCS4	= 0x424,
550 	RTW89_HW_RATE_V1_EHT_NSS2_MCS5	= 0x425,
551 	RTW89_HW_RATE_V1_EHT_NSS2_MCS6	= 0x426,
552 	RTW89_HW_RATE_V1_EHT_NSS2_MCS7	= 0x427,
553 	RTW89_HW_RATE_V1_EHT_NSS2_MCS8	= 0x428,
554 	RTW89_HW_RATE_V1_EHT_NSS2_MCS9	= 0x429,
555 	RTW89_HW_RATE_V1_EHT_NSS2_MCS10	= 0x42A,
556 	RTW89_HW_RATE_V1_EHT_NSS2_MCS11	= 0x42B,
557 	RTW89_HW_RATE_V1_EHT_NSS2_MCS12	= 0x42C,
558 	RTW89_HW_RATE_V1_EHT_NSS2_MCS13	= 0x42D,
559 	RTW89_HW_RATE_V1_EHT_NSS3_MCS0	= 0x440,
560 	RTW89_HW_RATE_V1_EHT_NSS3_MCS1	= 0x441,
561 	RTW89_HW_RATE_V1_EHT_NSS3_MCS2	= 0x442,
562 	RTW89_HW_RATE_V1_EHT_NSS3_MCS3	= 0x443,
563 	RTW89_HW_RATE_V1_EHT_NSS3_MCS4	= 0x444,
564 	RTW89_HW_RATE_V1_EHT_NSS3_MCS5	= 0x445,
565 	RTW89_HW_RATE_V1_EHT_NSS3_MCS6	= 0x446,
566 	RTW89_HW_RATE_V1_EHT_NSS3_MCS7	= 0x447,
567 	RTW89_HW_RATE_V1_EHT_NSS3_MCS8	= 0x448,
568 	RTW89_HW_RATE_V1_EHT_NSS3_MCS9	= 0x449,
569 	RTW89_HW_RATE_V1_EHT_NSS3_MCS10	= 0x44A,
570 	RTW89_HW_RATE_V1_EHT_NSS3_MCS11	= 0x44B,
571 	RTW89_HW_RATE_V1_EHT_NSS3_MCS12	= 0x44C,
572 	RTW89_HW_RATE_V1_EHT_NSS3_MCS13	= 0x44D,
573 	RTW89_HW_RATE_V1_EHT_NSS4_MCS0	= 0x460,
574 	RTW89_HW_RATE_V1_EHT_NSS4_MCS1	= 0x461,
575 	RTW89_HW_RATE_V1_EHT_NSS4_MCS2	= 0x462,
576 	RTW89_HW_RATE_V1_EHT_NSS4_MCS3	= 0x463,
577 	RTW89_HW_RATE_V1_EHT_NSS4_MCS4	= 0x464,
578 	RTW89_HW_RATE_V1_EHT_NSS4_MCS5	= 0x465,
579 	RTW89_HW_RATE_V1_EHT_NSS4_MCS6	= 0x466,
580 	RTW89_HW_RATE_V1_EHT_NSS4_MCS7	= 0x467,
581 	RTW89_HW_RATE_V1_EHT_NSS4_MCS8	= 0x468,
582 	RTW89_HW_RATE_V1_EHT_NSS4_MCS9	= 0x469,
583 	RTW89_HW_RATE_V1_EHT_NSS4_MCS10	= 0x46A,
584 	RTW89_HW_RATE_V1_EHT_NSS4_MCS11	= 0x46B,
585 	RTW89_HW_RATE_V1_EHT_NSS4_MCS12	= 0x46C,
586 	RTW89_HW_RATE_V1_EHT_NSS4_MCS13	= 0x46D,
587 
588 	RTW89_HW_RATE_NR,
589 	RTW89_HW_RATE_INVAL,
590 
591 	RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7),
592 	RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0),
593 	RTW89_HW_RATE_V1_MASK_MOD = GENMASK(10, 8),
594 	RTW89_HW_RATE_V1_MASK_VAL = GENMASK(7, 0),
595 };
596 
597 /* 2G channels,
598  * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
599  */
600 #define RTW89_2G_CH_NUM 14
601 
602 /* 5G channels,
603  * 36, 38, 40, 42, 44, 46, 48, 50,
604  * 52, 54, 56, 58, 60, 62, 64,
605  * 100, 102, 104, 106, 108, 110, 112, 114,
606  * 116, 118, 120, 122, 124, 126, 128, 130,
607  * 132, 134, 136, 138, 140, 142, 144,
608  * 149, 151, 153, 155, 157, 159, 161, 163,
609  * 165, 167, 169, 171, 173, 175, 177
610  */
611 #define RTW89_5G_CH_NUM 53
612 
613 /* 6G channels,
614  * 1, 3, 5, 7, 9, 11, 13, 15,
615  * 17, 19, 21, 23, 25, 27, 29, 33,
616  * 35, 37, 39, 41, 43, 45, 47, 49,
617  * 51, 53, 55, 57, 59, 61, 65, 67,
618  * 69, 71, 73, 75, 77, 79, 81, 83,
619  * 85, 87, 89, 91, 93, 97, 99, 101,
620  * 103, 105, 107, 109, 111, 113, 115, 117,
621  * 119, 121, 123, 125, 129, 131, 133, 135,
622  * 137, 139, 141, 143, 145, 147, 149, 151,
623  * 153, 155, 157, 161, 163, 165, 167, 169,
624  * 171, 173, 175, 177, 179, 181, 183, 185,
625  * 187, 189, 193, 195, 197, 199, 201, 203,
626  * 205, 207, 209, 211, 213, 215, 217, 219,
627  * 221, 225, 227, 229, 231, 233, 235, 237,
628  * 239, 241, 243, 245, 247, 249, 251, 253,
629  */
630 #define RTW89_6G_CH_NUM 120
631 
632 enum rtw89_rate_section {
633 	RTW89_RS_CCK,
634 	RTW89_RS_OFDM,
635 	RTW89_RS_MCS, /* for HT/VHT/HE */
636 	RTW89_RS_HEDCM,
637 	RTW89_RS_OFFSET,
638 	RTW89_RS_NUM,
639 	RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1,
640 	RTW89_RS_TX_SHAPE_NUM = RTW89_RS_OFDM + 1,
641 };
642 
643 enum rtw89_rate_num {
644 	RTW89_RATE_CCK_NUM	= 4,
645 	RTW89_RATE_OFDM_NUM	= 8,
646 	RTW89_RATE_MCS_NUM	= 12,
647 	RTW89_RATE_HEDCM_NUM	= 4, /* for HEDCM MCS0/1/3/4 */
648 	RTW89_RATE_OFFSET_NUM	= 5, /* for HE(HEDCM)/VHT/HT/OFDM/CCK offset */
649 };
650 
651 enum rtw89_nss {
652 	RTW89_NSS_1		= 0,
653 	RTW89_NSS_2		= 1,
654 	/* HE DCM only support 1ss and 2ss */
655 	RTW89_NSS_HEDCM_NUM	= RTW89_NSS_2 + 1,
656 	RTW89_NSS_3		= 2,
657 	RTW89_NSS_4		= 3,
658 	RTW89_NSS_NUM,
659 };
660 
661 enum rtw89_ntx {
662 	RTW89_1TX	= 0,
663 	RTW89_2TX	= 1,
664 	RTW89_NTX_NUM,
665 };
666 
667 enum rtw89_beamforming_type {
668 	RTW89_NONBF	= 0,
669 	RTW89_BF	= 1,
670 	RTW89_BF_NUM,
671 };
672 
673 enum rtw89_regulation_type {
674 	RTW89_WW	= 0,
675 	RTW89_ETSI	= 1,
676 	RTW89_FCC	= 2,
677 	RTW89_MKK	= 3,
678 	RTW89_NA	= 4,
679 	RTW89_IC	= 5,
680 	RTW89_KCC	= 6,
681 	RTW89_ACMA	= 7,
682 	RTW89_NCC	= 8,
683 	RTW89_MEXICO	= 9,
684 	RTW89_CHILE	= 10,
685 	RTW89_UKRAINE	= 11,
686 	RTW89_CN	= 12,
687 	RTW89_QATAR	= 13,
688 	RTW89_UK	= 14,
689 	RTW89_REGD_NUM,
690 };
691 
692 enum rtw89_reg_6ghz_power {
693 	RTW89_REG_6GHZ_POWER_VLP = 0,
694 	RTW89_REG_6GHZ_POWER_LPI = 1,
695 	RTW89_REG_6GHZ_POWER_STD = 2,
696 
697 	NUM_OF_RTW89_REG_6GHZ_POWER,
698 	RTW89_REG_6GHZ_POWER_DFLT = RTW89_REG_6GHZ_POWER_VLP,
699 };
700 
701 enum rtw89_fw_pkt_ofld_type {
702 	RTW89_PKT_OFLD_TYPE_PROBE_RSP = 0,
703 	RTW89_PKT_OFLD_TYPE_PS_POLL = 1,
704 	RTW89_PKT_OFLD_TYPE_NULL_DATA = 2,
705 	RTW89_PKT_OFLD_TYPE_QOS_NULL = 3,
706 	RTW89_PKT_OFLD_TYPE_CTS2SELF = 4,
707 	RTW89_PKT_OFLD_TYPE_ARP_RSP = 5,
708 	RTW89_PKT_OFLD_TYPE_NDP = 6,
709 	RTW89_PKT_OFLD_TYPE_EAPOL_KEY = 7,
710 	RTW89_PKT_OFLD_TYPE_SA_QUERY = 8,
711 	RTW89_PKT_OFLD_TYPE_PROBE_REQ = 12,
712 	RTW89_PKT_OFLD_TYPE_NUM,
713 };
714 
715 struct rtw89_txpwr_byrate {
716 	s8 cck[RTW89_RATE_CCK_NUM];
717 	s8 ofdm[RTW89_RATE_OFDM_NUM];
718 	s8 mcs[RTW89_NSS_NUM][RTW89_RATE_MCS_NUM];
719 	s8 hedcm[RTW89_NSS_HEDCM_NUM][RTW89_RATE_HEDCM_NUM];
720 	s8 offset[RTW89_RATE_OFFSET_NUM];
721 };
722 
723 enum rtw89_bandwidth_section_num {
724 	RTW89_BW20_SEC_NUM = 8,
725 	RTW89_BW40_SEC_NUM = 4,
726 	RTW89_BW80_SEC_NUM = 2,
727 };
728 
729 #define RTW89_TXPWR_LMT_PAGE_SIZE 40
730 
731 struct rtw89_txpwr_limit {
732 	s8 cck_20m[RTW89_BF_NUM];
733 	s8 cck_40m[RTW89_BF_NUM];
734 	s8 ofdm[RTW89_BF_NUM];
735 	s8 mcs_20m[RTW89_BW20_SEC_NUM][RTW89_BF_NUM];
736 	s8 mcs_40m[RTW89_BW40_SEC_NUM][RTW89_BF_NUM];
737 	s8 mcs_80m[RTW89_BW80_SEC_NUM][RTW89_BF_NUM];
738 	s8 mcs_160m[RTW89_BF_NUM];
739 	s8 mcs_40m_0p5[RTW89_BF_NUM];
740 	s8 mcs_40m_2p5[RTW89_BF_NUM];
741 };
742 
743 #define RTW89_RU_SEC_NUM 8
744 
745 #define RTW89_TXPWR_LMT_RU_PAGE_SIZE 24
746 
747 struct rtw89_txpwr_limit_ru {
748 	s8 ru26[RTW89_RU_SEC_NUM];
749 	s8 ru52[RTW89_RU_SEC_NUM];
750 	s8 ru106[RTW89_RU_SEC_NUM];
751 };
752 
753 struct rtw89_rate_desc {
754 	enum rtw89_nss nss;
755 	enum rtw89_rate_section rs;
756 	u8 idx;
757 };
758 
759 #define PHY_STS_HDR_LEN 8
760 #define RF_PATH_MAX 4
761 #define RTW89_MAX_PPDU_CNT 8
762 struct rtw89_rx_phy_ppdu {
763 	void *buf;
764 	u32 len;
765 	u8 rssi_avg;
766 	u8 rssi[RF_PATH_MAX];
767 	u8 mac_id;
768 	u8 chan_idx;
769 	u8 ie;
770 	u16 rate;
771 	struct {
772 		bool has;
773 		u8 avg_snr;
774 		u8 evm_max;
775 		u8 evm_min;
776 	} ofdm;
777 	bool to_self;
778 	bool valid;
779 };
780 
781 enum rtw89_mac_idx {
782 	RTW89_MAC_0 = 0,
783 	RTW89_MAC_1 = 1,
784 };
785 
786 enum rtw89_phy_idx {
787 	RTW89_PHY_0 = 0,
788 	RTW89_PHY_1 = 1,
789 	RTW89_PHY_MAX
790 };
791 
792 enum rtw89_sub_entity_idx {
793 	RTW89_SUB_ENTITY_0 = 0,
794 	RTW89_SUB_ENTITY_1 = 1,
795 
796 	NUM_OF_RTW89_SUB_ENTITY,
797 	RTW89_SUB_ENTITY_IDLE = NUM_OF_RTW89_SUB_ENTITY,
798 };
799 
800 enum rtw89_rf_path {
801 	RF_PATH_A = 0,
802 	RF_PATH_B = 1,
803 	RF_PATH_C = 2,
804 	RF_PATH_D = 3,
805 	RF_PATH_AB,
806 	RF_PATH_AC,
807 	RF_PATH_AD,
808 	RF_PATH_BC,
809 	RF_PATH_BD,
810 	RF_PATH_CD,
811 	RF_PATH_ABC,
812 	RF_PATH_ABD,
813 	RF_PATH_ACD,
814 	RF_PATH_BCD,
815 	RF_PATH_ABCD,
816 };
817 
818 enum rtw89_rf_path_bit {
819 	RF_A	= BIT(0),
820 	RF_B	= BIT(1),
821 	RF_C	= BIT(2),
822 	RF_D	= BIT(3),
823 
824 	RF_AB	= (RF_A | RF_B),
825 	RF_AC	= (RF_A | RF_C),
826 	RF_AD	= (RF_A | RF_D),
827 	RF_BC	= (RF_B | RF_C),
828 	RF_BD	= (RF_B | RF_D),
829 	RF_CD	= (RF_C | RF_D),
830 
831 	RF_ABC	= (RF_A | RF_B | RF_C),
832 	RF_ABD	= (RF_A | RF_B | RF_D),
833 	RF_ACD	= (RF_A | RF_C | RF_D),
834 	RF_BCD	= (RF_B | RF_C | RF_D),
835 
836 	RF_ABCD	= (RF_A | RF_B | RF_C | RF_D),
837 };
838 
839 enum rtw89_bandwidth {
840 	RTW89_CHANNEL_WIDTH_20	= 0,
841 	RTW89_CHANNEL_WIDTH_40	= 1,
842 	RTW89_CHANNEL_WIDTH_80	= 2,
843 	RTW89_CHANNEL_WIDTH_160	= 3,
844 	RTW89_CHANNEL_WIDTH_80_80	= 4,
845 	RTW89_CHANNEL_WIDTH_5	= 5,
846 	RTW89_CHANNEL_WIDTH_10	= 6,
847 };
848 
849 enum rtw89_ps_mode {
850 	RTW89_PS_MODE_NONE	= 0,
851 	RTW89_PS_MODE_RFOFF	= 1,
852 	RTW89_PS_MODE_CLK_GATED	= 2,
853 	RTW89_PS_MODE_PWR_GATED	= 3,
854 };
855 
856 #define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1)
857 #define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1)
858 #define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1)
859 #define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1)
860 
861 enum rtw89_ru_bandwidth {
862 	RTW89_RU26 = 0,
863 	RTW89_RU52 = 1,
864 	RTW89_RU106 = 2,
865 	RTW89_RU_NUM,
866 };
867 
868 enum rtw89_sc_offset {
869 	RTW89_SC_DONT_CARE	= 0,
870 	RTW89_SC_20_UPPER	= 1,
871 	RTW89_SC_20_LOWER	= 2,
872 	RTW89_SC_20_UPMOST	= 3,
873 	RTW89_SC_20_LOWEST	= 4,
874 	RTW89_SC_20_UP2X	= 5,
875 	RTW89_SC_20_LOW2X	= 6,
876 	RTW89_SC_20_UP3X	= 7,
877 	RTW89_SC_20_LOW3X	= 8,
878 	RTW89_SC_40_UPPER	= 9,
879 	RTW89_SC_40_LOWER	= 10,
880 };
881 
882 enum rtw89_wow_flags {
883 	RTW89_WOW_FLAG_EN_MAGIC_PKT,
884 	RTW89_WOW_FLAG_EN_REKEY_PKT,
885 	RTW89_WOW_FLAG_EN_DISCONNECT,
886 	RTW89_WOW_FLAG_NUM,
887 };
888 
889 struct rtw89_chan {
890 	u8 channel;
891 	u8 primary_channel;
892 	enum rtw89_band band_type;
893 	enum rtw89_bandwidth band_width;
894 
895 	/* The follow-up are derived from the above. We must ensure that it
896 	 * is assigned correctly in rtw89_chan_create() if new one is added.
897 	 */
898 	u32 freq;
899 	enum rtw89_subband subband_type;
900 	enum rtw89_sc_offset pri_ch_idx;
901 };
902 
903 struct rtw89_chan_rcd {
904 	u8 prev_primary_channel;
905 	enum rtw89_band prev_band_type;
906 	bool band_changed;
907 };
908 
909 struct rtw89_channel_help_params {
910 	u32 tx_en;
911 };
912 
913 struct rtw89_port_reg {
914 	u32 port_cfg;
915 	u32 tbtt_prohib;
916 	u32 bcn_area;
917 	u32 bcn_early;
918 	u32 tbtt_early;
919 	u32 tbtt_agg;
920 	u32 bcn_space;
921 	u32 bcn_forcetx;
922 	u32 bcn_err_cnt;
923 	u32 bcn_err_flag;
924 	u32 dtim_ctrl;
925 	u32 tbtt_shift;
926 	u32 bcn_cnt_tmr;
927 	u32 tsftr_l;
928 	u32 tsftr_h;
929 };
930 
931 struct rtw89_txwd_body {
932 	__le32 dword0;
933 	__le32 dword1;
934 	__le32 dword2;
935 	__le32 dword3;
936 	__le32 dword4;
937 	__le32 dword5;
938 } __packed;
939 
940 struct rtw89_txwd_body_v1 {
941 	__le32 dword0;
942 	__le32 dword1;
943 	__le32 dword2;
944 	__le32 dword3;
945 	__le32 dword4;
946 	__le32 dword5;
947 	__le32 dword6;
948 	__le32 dword7;
949 } __packed;
950 
951 struct rtw89_txwd_info {
952 	__le32 dword0;
953 	__le32 dword1;
954 	__le32 dword2;
955 	__le32 dword3;
956 	__le32 dword4;
957 	__le32 dword5;
958 } __packed;
959 
960 struct rtw89_rx_desc_info {
961 	u16 pkt_size;
962 	u8 pkt_type;
963 	u8 drv_info_size;
964 	u8 shift;
965 	u8 wl_hd_iv_len;
966 	bool long_rxdesc;
967 	bool bb_sel;
968 	bool mac_info_valid;
969 	u16 data_rate;
970 	u8 gi_ltf;
971 	u8 bw;
972 	u32 free_run_cnt;
973 	u8 user_id;
974 	bool sr_en;
975 	u8 ppdu_cnt;
976 	u8 ppdu_type;
977 	bool icv_err;
978 	bool crc32_err;
979 	bool hw_dec;
980 	bool sw_dec;
981 	bool addr1_match;
982 	u8 frag;
983 	u16 seq;
984 	u8 frame_type;
985 	u8 rx_pl_id;
986 	bool addr_cam_valid;
987 	u8 addr_cam_id;
988 	u8 sec_cam_id;
989 	u8 mac_id;
990 	u16 offset;
991 	u16 rxd_len;
992 	bool ready;
993 };
994 
995 struct rtw89_rxdesc_short {
996 	__le32 dword0;
997 	__le32 dword1;
998 	__le32 dword2;
999 	__le32 dword3;
1000 } __packed;
1001 
1002 struct rtw89_rxdesc_long {
1003 	__le32 dword0;
1004 	__le32 dword1;
1005 	__le32 dword2;
1006 	__le32 dword3;
1007 	__le32 dword4;
1008 	__le32 dword5;
1009 	__le32 dword6;
1010 	__le32 dword7;
1011 } __packed;
1012 
1013 struct rtw89_tx_desc_info {
1014 	u16 pkt_size;
1015 	u8 wp_offset;
1016 	u8 mac_id;
1017 	u8 qsel;
1018 	u8 ch_dma;
1019 	u8 hdr_llc_len;
1020 	bool is_bmc;
1021 	bool en_wd_info;
1022 	bool wd_page;
1023 	bool use_rate;
1024 	bool dis_data_fb;
1025 	bool tid_indicate;
1026 	bool agg_en;
1027 	bool bk;
1028 	u8 ampdu_density;
1029 	u8 ampdu_num;
1030 	bool sec_en;
1031 	u8 addr_info_nr;
1032 	u8 sec_keyid;
1033 	u8 sec_type;
1034 	u8 sec_cam_idx;
1035 	u8 sec_seq[6];
1036 	u16 data_rate;
1037 	u16 data_retry_lowest_rate;
1038 	bool fw_dl;
1039 	u16 seq;
1040 	bool a_ctrl_bsr;
1041 	u8 hw_ssn_sel;
1042 #define RTW89_MGMT_HW_SSN_SEL	1
1043 	u8 hw_seq_mode;
1044 #define RTW89_MGMT_HW_SEQ_MODE	1
1045 	bool hiq;
1046 	u8 port;
1047 	bool er_cap;
1048 };
1049 
1050 struct rtw89_core_tx_request {
1051 	enum rtw89_core_tx_type tx_type;
1052 
1053 	struct sk_buff *skb;
1054 	struct ieee80211_vif *vif;
1055 	struct ieee80211_sta *sta;
1056 	struct rtw89_tx_desc_info desc_info;
1057 };
1058 
1059 struct rtw89_txq {
1060 	struct list_head list;
1061 	unsigned long flags;
1062 	int wait_cnt;
1063 };
1064 
1065 struct rtw89_mac_ax_gnt {
1066 	u8 gnt_bt_sw_en;
1067 	u8 gnt_bt;
1068 	u8 gnt_wl_sw_en;
1069 	u8 gnt_wl;
1070 } __packed;
1071 
1072 #define RTW89_MAC_AX_COEX_GNT_NR 2
1073 struct rtw89_mac_ax_coex_gnt {
1074 	struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR];
1075 };
1076 
1077 enum rtw89_btc_ncnt {
1078 	BTC_NCNT_POWER_ON = 0x0,
1079 	BTC_NCNT_POWER_OFF,
1080 	BTC_NCNT_INIT_COEX,
1081 	BTC_NCNT_SCAN_START,
1082 	BTC_NCNT_SCAN_FINISH,
1083 	BTC_NCNT_SPECIAL_PACKET,
1084 	BTC_NCNT_SWITCH_BAND,
1085 	BTC_NCNT_RFK_TIMEOUT,
1086 	BTC_NCNT_SHOW_COEX_INFO,
1087 	BTC_NCNT_ROLE_INFO,
1088 	BTC_NCNT_CONTROL,
1089 	BTC_NCNT_RADIO_STATE,
1090 	BTC_NCNT_CUSTOMERIZE,
1091 	BTC_NCNT_WL_RFK,
1092 	BTC_NCNT_WL_STA,
1093 	BTC_NCNT_FWINFO,
1094 	BTC_NCNT_TIMER,
1095 	BTC_NCNT_NUM
1096 };
1097 
1098 enum rtw89_btc_btinfo {
1099 	BTC_BTINFO_L0 = 0,
1100 	BTC_BTINFO_L1,
1101 	BTC_BTINFO_L2,
1102 	BTC_BTINFO_L3,
1103 	BTC_BTINFO_H0,
1104 	BTC_BTINFO_H1,
1105 	BTC_BTINFO_H2,
1106 	BTC_BTINFO_H3,
1107 	BTC_BTINFO_MAX
1108 };
1109 
1110 enum rtw89_btc_dcnt {
1111 	BTC_DCNT_RUN = 0x0,
1112 	BTC_DCNT_CX_RUNINFO,
1113 	BTC_DCNT_RPT,
1114 	BTC_DCNT_RPT_HANG,
1115 	BTC_DCNT_CYCLE,
1116 	BTC_DCNT_CYCLE_HANG,
1117 	BTC_DCNT_W1,
1118 	BTC_DCNT_W1_HANG,
1119 	BTC_DCNT_B1,
1120 	BTC_DCNT_B1_HANG,
1121 	BTC_DCNT_TDMA_NONSYNC,
1122 	BTC_DCNT_SLOT_NONSYNC,
1123 	BTC_DCNT_BTCNT_HANG,
1124 	BTC_DCNT_WL_SLOT_DRIFT,
1125 	BTC_DCNT_WL_STA_LAST,
1126 	BTC_DCNT_BT_SLOT_DRIFT,
1127 	BTC_DCNT_BT_SLOT_FLOOD,
1128 	BTC_DCNT_FDDT_TRIG,
1129 	BTC_DCNT_E2G,
1130 	BTC_DCNT_E2G_HANG,
1131 	BTC_DCNT_NUM
1132 };
1133 
1134 enum rtw89_btc_wl_state_cnt {
1135 	BTC_WCNT_SCANAP = 0x0,
1136 	BTC_WCNT_DHCP,
1137 	BTC_WCNT_EAPOL,
1138 	BTC_WCNT_ARP,
1139 	BTC_WCNT_SCBDUPDATE,
1140 	BTC_WCNT_RFK_REQ,
1141 	BTC_WCNT_RFK_GO,
1142 	BTC_WCNT_RFK_REJECT,
1143 	BTC_WCNT_RFK_TIMEOUT,
1144 	BTC_WCNT_CH_UPDATE,
1145 	BTC_WCNT_NUM
1146 };
1147 
1148 enum rtw89_btc_bt_state_cnt {
1149 	BTC_BCNT_RETRY = 0x0,
1150 	BTC_BCNT_REINIT,
1151 	BTC_BCNT_REENABLE,
1152 	BTC_BCNT_SCBDREAD,
1153 	BTC_BCNT_RELINK,
1154 	BTC_BCNT_IGNOWL,
1155 	BTC_BCNT_INQPAG,
1156 	BTC_BCNT_INQ,
1157 	BTC_BCNT_PAGE,
1158 	BTC_BCNT_ROLESW,
1159 	BTC_BCNT_AFH,
1160 	BTC_BCNT_INFOUPDATE,
1161 	BTC_BCNT_INFOSAME,
1162 	BTC_BCNT_SCBDUPDATE,
1163 	BTC_BCNT_HIPRI_TX,
1164 	BTC_BCNT_HIPRI_RX,
1165 	BTC_BCNT_LOPRI_TX,
1166 	BTC_BCNT_LOPRI_RX,
1167 	BTC_BCNT_POLUT,
1168 	BTC_BCNT_RATECHG,
1169 	BTC_BCNT_NUM
1170 };
1171 
1172 enum rtw89_btc_bt_profile {
1173 	BTC_BT_NOPROFILE = 0,
1174 	BTC_BT_HFP = BIT(0),
1175 	BTC_BT_HID = BIT(1),
1176 	BTC_BT_A2DP = BIT(2),
1177 	BTC_BT_PAN = BIT(3),
1178 	BTC_PROFILE_MAX = 4,
1179 };
1180 
1181 struct rtw89_btc_ant_info {
1182 	u8 type;  /* shared, dedicated */
1183 	u8 num;
1184 	u8 isolation;
1185 
1186 	u8 single_pos: 1;/* Single antenna at S0 or S1 */
1187 	u8 diversity: 1;
1188 	u8 btg_pos: 2;
1189 	u8 stream_cnt: 4;
1190 };
1191 
1192 enum rtw89_tfc_dir {
1193 	RTW89_TFC_UL,
1194 	RTW89_TFC_DL,
1195 };
1196 
1197 struct rtw89_btc_wl_smap {
1198 	u32 busy: 1;
1199 	u32 scan: 1;
1200 	u32 connecting: 1;
1201 	u32 roaming: 1;
1202 	u32 _4way: 1;
1203 	u32 rf_off: 1;
1204 	u32 lps: 2;
1205 	u32 ips: 1;
1206 	u32 init_ok: 1;
1207 	u32 traffic_dir : 2;
1208 	u32 rf_off_pre: 1;
1209 	u32 lps_pre: 2;
1210 };
1211 
1212 enum rtw89_tfc_lv {
1213 	RTW89_TFC_IDLE,
1214 	RTW89_TFC_ULTRA_LOW,
1215 	RTW89_TFC_LOW,
1216 	RTW89_TFC_MID,
1217 	RTW89_TFC_HIGH,
1218 };
1219 
1220 #define RTW89_TP_SHIFT 18 /* bytes/2s --> Mbps */
1221 DECLARE_EWMA(tp, 10, 2);
1222 
1223 struct rtw89_traffic_stats {
1224 	/* units in bytes */
1225 	u64 tx_unicast;
1226 	u64 rx_unicast;
1227 	u32 tx_avg_len;
1228 	u32 rx_avg_len;
1229 
1230 	/* count for packets */
1231 	u64 tx_cnt;
1232 	u64 rx_cnt;
1233 
1234 	/* units in Mbps */
1235 	u32 tx_throughput;
1236 	u32 rx_throughput;
1237 	u32 tx_throughput_raw;
1238 	u32 rx_throughput_raw;
1239 
1240 	u32 rx_tf_acc;
1241 	u32 rx_tf_periodic;
1242 
1243 	enum rtw89_tfc_lv tx_tfc_lv;
1244 	enum rtw89_tfc_lv rx_tfc_lv;
1245 	struct ewma_tp tx_ewma_tp;
1246 	struct ewma_tp rx_ewma_tp;
1247 
1248 	u16 tx_rate;
1249 	u16 rx_rate;
1250 };
1251 
1252 struct rtw89_btc_statistic {
1253 	u8 rssi; /* 0%~110% (dBm = rssi -110) */
1254 	struct rtw89_traffic_stats traffic;
1255 };
1256 
1257 #define BTC_WL_RSSI_THMAX 4
1258 
1259 struct rtw89_btc_wl_link_info {
1260 	struct rtw89_btc_statistic stat;
1261 	enum rtw89_tfc_dir dir;
1262 	u8 rssi_state[BTC_WL_RSSI_THMAX];
1263 	u8 mac_addr[ETH_ALEN];
1264 	u8 busy;
1265 	u8 ch;
1266 	u8 bw;
1267 	u8 band;
1268 	u8 role;
1269 	u8 pid;
1270 	u8 phy;
1271 	u8 dtim_period;
1272 	u8 mode;
1273 
1274 	u8 mac_id;
1275 	u8 tx_retry;
1276 
1277 	u32 bcn_period;
1278 	u32 busy_t;
1279 	u32 tx_time;
1280 	u32 client_cnt;
1281 	u32 rx_rate_drop_cnt;
1282 
1283 	u32 active: 1;
1284 	u32 noa: 1;
1285 	u32 client_ps: 1;
1286 	u32 connected: 2;
1287 };
1288 
1289 union rtw89_btc_wl_state_map {
1290 	u32 val;
1291 	struct rtw89_btc_wl_smap map;
1292 };
1293 
1294 struct rtw89_btc_bt_hfp_desc {
1295 	u32 exist: 1;
1296 	u32 type: 2;
1297 	u32 rsvd: 29;
1298 };
1299 
1300 struct rtw89_btc_bt_hid_desc {
1301 	u32 exist: 1;
1302 	u32 slot_info: 2;
1303 	u32 pair_cnt: 2;
1304 	u32 type: 8;
1305 	u32 rsvd: 19;
1306 };
1307 
1308 struct rtw89_btc_bt_a2dp_desc {
1309 	u8 exist: 1;
1310 	u8 exist_last: 1;
1311 	u8 play_latency: 1;
1312 	u8 type: 3;
1313 	u8 active: 1;
1314 	u8 sink: 1;
1315 
1316 	u8 bitpool;
1317 	u16 vendor_id;
1318 	u32 device_name;
1319 	u32 flush_time;
1320 };
1321 
1322 struct rtw89_btc_bt_pan_desc {
1323 	u32 exist: 1;
1324 	u32 type: 1;
1325 	u32 active: 1;
1326 	u32 rsvd: 29;
1327 };
1328 
1329 struct rtw89_btc_bt_rfk_info {
1330 	u32 run: 1;
1331 	u32 req: 1;
1332 	u32 timeout: 1;
1333 	u32 rsvd: 29;
1334 };
1335 
1336 union rtw89_btc_bt_rfk_info_map {
1337 	u32 val;
1338 	struct rtw89_btc_bt_rfk_info map;
1339 };
1340 
1341 struct rtw89_btc_bt_ver_info {
1342 	u32 fw_coex; /* match with which coex_ver */
1343 	u32 fw;
1344 };
1345 
1346 struct rtw89_btc_bool_sta_chg {
1347 	u32 now: 1;
1348 	u32 last: 1;
1349 	u32 remain: 1;
1350 	u32 srvd: 29;
1351 };
1352 
1353 struct rtw89_btc_u8_sta_chg {
1354 	u8 now;
1355 	u8 last;
1356 	u8 remain;
1357 	u8 rsvd;
1358 };
1359 
1360 struct rtw89_btc_wl_scan_info {
1361 	u8 band[RTW89_PHY_MAX];
1362 	u8 phy_map;
1363 	u8 rsvd;
1364 };
1365 
1366 struct rtw89_btc_wl_dbcc_info {
1367 	u8 op_band[RTW89_PHY_MAX]; /* op band in each phy */
1368 	u8 scan_band[RTW89_PHY_MAX]; /* scan band in  each phy */
1369 	u8 real_band[RTW89_PHY_MAX];
1370 	u8 role[RTW89_PHY_MAX]; /* role in each phy */
1371 };
1372 
1373 struct rtw89_btc_wl_active_role {
1374 	u8 connected: 1;
1375 	u8 pid: 3;
1376 	u8 phy: 1;
1377 	u8 noa: 1;
1378 	u8 band: 2;
1379 
1380 	u8 client_ps: 1;
1381 	u8 bw: 7;
1382 
1383 	u8 role;
1384 	u8 ch;
1385 
1386 	u16 tx_lvl;
1387 	u16 rx_lvl;
1388 	u16 tx_rate;
1389 	u16 rx_rate;
1390 };
1391 
1392 struct rtw89_btc_wl_active_role_v1 {
1393 	u8 connected: 1;
1394 	u8 pid: 3;
1395 	u8 phy: 1;
1396 	u8 noa: 1;
1397 	u8 band: 2;
1398 
1399 	u8 client_ps: 1;
1400 	u8 bw: 7;
1401 
1402 	u8 role;
1403 	u8 ch;
1404 
1405 	u16 tx_lvl;
1406 	u16 rx_lvl;
1407 	u16 tx_rate;
1408 	u16 rx_rate;
1409 
1410 	u32 noa_duration; /* ms */
1411 };
1412 
1413 struct rtw89_btc_wl_active_role_v2 {
1414 	u8 connected: 1;
1415 	u8 pid: 3;
1416 	u8 phy: 1;
1417 	u8 noa: 1;
1418 	u8 band: 2;
1419 
1420 	u8 client_ps: 1;
1421 	u8 bw: 7;
1422 
1423 	u8 role;
1424 	u8 ch;
1425 
1426 	u32 noa_duration; /* ms */
1427 };
1428 
1429 struct rtw89_btc_wl_role_info_bpos {
1430 	u16 none: 1;
1431 	u16 station: 1;
1432 	u16 ap: 1;
1433 	u16 vap: 1;
1434 	u16 adhoc: 1;
1435 	u16 adhoc_master: 1;
1436 	u16 mesh: 1;
1437 	u16 moniter: 1;
1438 	u16 p2p_device: 1;
1439 	u16 p2p_gc: 1;
1440 	u16 p2p_go: 1;
1441 	u16 nan: 1;
1442 };
1443 
1444 struct rtw89_btc_wl_scc_ctrl {
1445 	u8 null_role1;
1446 	u8 null_role2;
1447 	u8 ebt_null; /* if tx null at EBT slot */
1448 };
1449 
1450 union rtw89_btc_wl_role_info_map {
1451 	u16 val;
1452 	struct rtw89_btc_wl_role_info_bpos role;
1453 };
1454 
1455 struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */
1456 	u8 connect_cnt;
1457 	u8 link_mode;
1458 	union rtw89_btc_wl_role_info_map role_map;
1459 	struct rtw89_btc_wl_active_role active_role[RTW89_PORT_NUM];
1460 };
1461 
1462 struct rtw89_btc_wl_role_info_v1 { /* struct size must be n*4 bytes */
1463 	u8 connect_cnt;
1464 	u8 link_mode;
1465 	union rtw89_btc_wl_role_info_map role_map;
1466 	struct rtw89_btc_wl_active_role_v1 active_role_v1[RTW89_PORT_NUM];
1467 	u32 mrole_type; /* btc_wl_mrole_type */
1468 	u32 mrole_noa_duration; /* ms */
1469 
1470 	u32 dbcc_en: 1;
1471 	u32 dbcc_chg: 1;
1472 	u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */
1473 	u32 link_mode_chg: 1;
1474 	u32 rsvd: 27;
1475 };
1476 
1477 struct rtw89_btc_wl_role_info_v2 { /* struct size must be n*4 bytes */
1478 	u8 connect_cnt;
1479 	u8 link_mode;
1480 	union rtw89_btc_wl_role_info_map role_map;
1481 	struct rtw89_btc_wl_active_role_v2 active_role_v2[RTW89_PORT_NUM];
1482 	u32 mrole_type; /* btc_wl_mrole_type */
1483 	u32 mrole_noa_duration; /* ms */
1484 
1485 	u32 dbcc_en: 1;
1486 	u32 dbcc_chg: 1;
1487 	u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */
1488 	u32 link_mode_chg: 1;
1489 	u32 rsvd: 27;
1490 };
1491 
1492 struct rtw89_btc_wl_ver_info {
1493 	u32 fw_coex; /* match with which coex_ver */
1494 	u32 fw;
1495 	u32 mac;
1496 	u32 bb;
1497 	u32 rf;
1498 };
1499 
1500 struct rtw89_btc_wl_afh_info {
1501 	u8 en;
1502 	u8 ch;
1503 	u8 bw;
1504 	u8 rsvd;
1505 } __packed;
1506 
1507 struct rtw89_btc_wl_rfk_info {
1508 	u32 state: 2;
1509 	u32 path_map: 4;
1510 	u32 phy_map: 2;
1511 	u32 band: 2;
1512 	u32 type: 8;
1513 	u32 rsvd: 14;
1514 };
1515 
1516 struct rtw89_btc_bt_smap {
1517 	u32 connect: 1;
1518 	u32 ble_connect: 1;
1519 	u32 acl_busy: 1;
1520 	u32 sco_busy: 1;
1521 	u32 mesh_busy: 1;
1522 	u32 inq_pag: 1;
1523 };
1524 
1525 union rtw89_btc_bt_state_map {
1526 	u32 val;
1527 	struct rtw89_btc_bt_smap map;
1528 };
1529 
1530 #define BTC_BT_RSSI_THMAX 4
1531 #define BTC_BT_AFH_GROUP 12
1532 #define BTC_BT_AFH_LE_GROUP 5
1533 
1534 struct rtw89_btc_bt_link_info {
1535 	struct rtw89_btc_u8_sta_chg profile_cnt;
1536 	struct rtw89_btc_bool_sta_chg multi_link;
1537 	struct rtw89_btc_bool_sta_chg relink;
1538 	struct rtw89_btc_bt_hfp_desc hfp_desc;
1539 	struct rtw89_btc_bt_hid_desc hid_desc;
1540 	struct rtw89_btc_bt_a2dp_desc a2dp_desc;
1541 	struct rtw89_btc_bt_pan_desc pan_desc;
1542 	union rtw89_btc_bt_state_map status;
1543 
1544 	u8 sut_pwr_level[BTC_PROFILE_MAX];
1545 	u8 golden_rx_shift[BTC_PROFILE_MAX];
1546 	u8 rssi_state[BTC_BT_RSSI_THMAX];
1547 	u8 afh_map[BTC_BT_AFH_GROUP];
1548 	u8 afh_map_le[BTC_BT_AFH_LE_GROUP];
1549 
1550 	u32 role_sw: 1;
1551 	u32 slave_role: 1;
1552 	u32 afh_update: 1;
1553 	u32 cqddr: 1;
1554 	u32 rssi: 8;
1555 	u32 tx_3m: 1;
1556 	u32 rsvd: 19;
1557 };
1558 
1559 struct rtw89_btc_3rdcx_info {
1560 	u8 type;   /* 0: none, 1:zigbee, 2:LTE  */
1561 	u8 hw_coex;
1562 	u16 rsvd;
1563 };
1564 
1565 struct rtw89_btc_dm_emap {
1566 	u32 init: 1;
1567 	u32 pta_owner: 1;
1568 	u32 wl_rfk_timeout: 1;
1569 	u32 bt_rfk_timeout: 1;
1570 	u32 wl_fw_hang: 1;
1571 	u32 cycle_hang: 1;
1572 	u32 w1_hang: 1;
1573 	u32 b1_hang: 1;
1574 	u32 tdma_no_sync: 1;
1575 	u32 slot_no_sync: 1;
1576 	u32 wl_slot_drift: 1;
1577 	u32 bt_slot_drift: 1;
1578 	u32 role_num_mismatch: 1;
1579 	u32 null1_tx_late: 1;
1580 	u32 bt_afh_conflict: 1;
1581 	u32 bt_leafh_conflict: 1;
1582 	u32 bt_slot_flood: 1;
1583 	u32 wl_e2g_hang: 1;
1584 	u32 wl_ver_mismatch: 1;
1585 	u32 bt_ver_mismatch: 1;
1586 };
1587 
1588 union rtw89_btc_dm_error_map {
1589 	u32 val;
1590 	struct rtw89_btc_dm_emap map;
1591 };
1592 
1593 struct rtw89_btc_rf_para {
1594 	u32 tx_pwr_freerun;
1595 	u32 rx_gain_freerun;
1596 	u32 tx_pwr_perpkt;
1597 	u32 rx_gain_perpkt;
1598 };
1599 
1600 struct rtw89_btc_wl_nhm {
1601 	u8 instant_wl_nhm_dbm;
1602 	u8 instant_wl_nhm_per_mhz;
1603 	u16 valid_record_times;
1604 	s8 record_pwr[16];
1605 	u8 record_ratio[16];
1606 	s8 pwr; /* dbm_per_MHz  */
1607 	u8 ratio;
1608 	u8 current_status;
1609 	u8 refresh;
1610 	bool start_flag;
1611 	s8 pwr_max;
1612 	s8 pwr_min;
1613 };
1614 
1615 struct rtw89_btc_wl_info {
1616 	struct rtw89_btc_wl_link_info link_info[RTW89_PORT_NUM];
1617 	struct rtw89_btc_wl_rfk_info rfk_info;
1618 	struct rtw89_btc_wl_ver_info  ver_info;
1619 	struct rtw89_btc_wl_afh_info afh_info;
1620 	struct rtw89_btc_wl_role_info role_info;
1621 	struct rtw89_btc_wl_role_info_v1 role_info_v1;
1622 	struct rtw89_btc_wl_role_info_v2 role_info_v2;
1623 	struct rtw89_btc_wl_scan_info scan_info;
1624 	struct rtw89_btc_wl_dbcc_info dbcc_info;
1625 	struct rtw89_btc_rf_para rf_para;
1626 	struct rtw89_btc_wl_nhm nhm;
1627 	union rtw89_btc_wl_state_map status;
1628 
1629 	u8 port_id[RTW89_WIFI_ROLE_MLME_MAX];
1630 	u8 rssi_level;
1631 	u8 cn_report;
1632 
1633 	bool scbd_change;
1634 	u32 scbd;
1635 };
1636 
1637 struct rtw89_btc_module {
1638 	struct rtw89_btc_ant_info ant;
1639 	u8 rfe_type;
1640 	u8 cv;
1641 
1642 	u8 bt_solo: 1;
1643 	u8 bt_pos: 1;
1644 	u8 switch_type: 1;
1645 	u8 wa_type: 3;
1646 
1647 	u8 kt_ver_adie;
1648 };
1649 
1650 #define RTW89_BTC_DM_MAXSTEP 30
1651 #define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8)
1652 
1653 struct rtw89_btc_dm_step {
1654 	u16 step[RTW89_BTC_DM_MAXSTEP];
1655 	u8 step_pos;
1656 	bool step_ov;
1657 };
1658 
1659 struct rtw89_btc_init_info {
1660 	struct rtw89_btc_module module;
1661 	u8 wl_guard_ch;
1662 
1663 	u8 wl_only: 1;
1664 	u8 wl_init_ok: 1;
1665 	u8 dbcc_en: 1;
1666 	u8 cx_other: 1;
1667 	u8 bt_only: 1;
1668 
1669 	u16 rsvd;
1670 };
1671 
1672 struct rtw89_btc_wl_tx_limit_para {
1673 	u16 enable;
1674 	u32 tx_time;	/* unit: us */
1675 	u16 tx_retry;
1676 };
1677 
1678 enum rtw89_btc_bt_scan_type {
1679 	BTC_SCAN_INQ	= 0,
1680 	BTC_SCAN_PAGE,
1681 	BTC_SCAN_BLE,
1682 	BTC_SCAN_INIT,
1683 	BTC_SCAN_TV,
1684 	BTC_SCAN_ADV,
1685 	BTC_SCAN_MAX1,
1686 };
1687 
1688 enum rtw89_btc_ble_scan_type {
1689 	CXSCAN_BG = 0,
1690 	CXSCAN_INIT,
1691 	CXSCAN_LE,
1692 	CXSCAN_MAX
1693 };
1694 
1695 #define RTW89_BTC_BTC_SCAN_V1_FLAG_ENABLE BIT(0)
1696 #define RTW89_BTC_BTC_SCAN_V1_FLAG_INTERLACE BIT(1)
1697 
1698 struct rtw89_btc_bt_scan_info_v1 {
1699 	__le16 win;
1700 	__le16 intvl;
1701 	__le32 flags;
1702 } __packed;
1703 
1704 struct rtw89_btc_bt_scan_info_v2 {
1705 	__le16 win;
1706 	__le16 intvl;
1707 } __packed;
1708 
1709 struct rtw89_btc_fbtc_btscan_v1 {
1710 	u8 fver; /* btc_ver::fcxbtscan */
1711 	u8 rsvd;
1712 	__le16 rsvd2;
1713 	struct rtw89_btc_bt_scan_info_v1 scan[BTC_SCAN_MAX1];
1714 } __packed;
1715 
1716 struct rtw89_btc_fbtc_btscan_v2 {
1717 	u8 fver; /* btc_ver::fcxbtscan */
1718 	u8 type;
1719 	__le16 rsvd2;
1720 	struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX];
1721 } __packed;
1722 
1723 union rtw89_btc_fbtc_btscan {
1724 	struct rtw89_btc_fbtc_btscan_v1 v1;
1725 	struct rtw89_btc_fbtc_btscan_v2 v2;
1726 };
1727 
1728 struct rtw89_btc_bt_info {
1729 	struct rtw89_btc_bt_link_info link_info;
1730 	struct rtw89_btc_bt_scan_info_v1 scan_info_v1[BTC_SCAN_MAX1];
1731 	struct rtw89_btc_bt_scan_info_v2 scan_info_v2[CXSCAN_MAX];
1732 	struct rtw89_btc_bt_ver_info ver_info;
1733 	struct rtw89_btc_bool_sta_chg enable;
1734 	struct rtw89_btc_bool_sta_chg inq_pag;
1735 	struct rtw89_btc_rf_para rf_para;
1736 	union rtw89_btc_bt_rfk_info_map rfk_info;
1737 
1738 	u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */
1739 
1740 	u32 scbd;
1741 	u32 feature;
1742 
1743 	u32 mbx_avl: 1;
1744 	u32 whql_test: 1;
1745 	u32 igno_wl: 1;
1746 	u32 reinit: 1;
1747 	u32 ble_scan_en: 1;
1748 	u32 btg_type: 1;
1749 	u32 inq: 1;
1750 	u32 pag: 1;
1751 	u32 run_patch_code: 1;
1752 	u32 hi_lna_rx: 1;
1753 	u32 scan_rx_low_pri: 1;
1754 	u32 scan_info_update: 1;
1755 	u32 rsvd: 20;
1756 };
1757 
1758 struct rtw89_btc_cx {
1759 	struct rtw89_btc_wl_info wl;
1760 	struct rtw89_btc_bt_info bt;
1761 	struct rtw89_btc_3rdcx_info other;
1762 	u32 state_map;
1763 	u32 cnt_bt[BTC_BCNT_NUM];
1764 	u32 cnt_wl[BTC_WCNT_NUM];
1765 };
1766 
1767 struct rtw89_btc_fbtc_tdma {
1768 	u8 type; /* btc_ver::fcxtdma */
1769 	u8 rxflctrl;
1770 	u8 txpause;
1771 	u8 wtgle_n;
1772 	u8 leak_n;
1773 	u8 ext_ctrl;
1774 	u8 rxflctrl_role;
1775 	u8 option_ctrl;
1776 } __packed;
1777 
1778 struct rtw89_btc_fbtc_tdma_v3 {
1779 	u8 fver; /* btc_ver::fcxtdma */
1780 	u8 rsvd;
1781 	__le16 rsvd1;
1782 	struct rtw89_btc_fbtc_tdma tdma;
1783 } __packed;
1784 
1785 union rtw89_btc_fbtc_tdma_le32 {
1786 	struct rtw89_btc_fbtc_tdma v1;
1787 	struct rtw89_btc_fbtc_tdma_v3 v3;
1788 };
1789 
1790 #define CXMREG_MAX 30
1791 #define CXMREG_MAX_V2 20
1792 #define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/
1793 #define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */
1794 
1795 enum rtw89_btc_bt_sta_counter {
1796 	BTC_BCNT_RFK_REQ = 0,
1797 	BTC_BCNT_RFK_GO = 1,
1798 	BTC_BCNT_RFK_REJECT = 2,
1799 	BTC_BCNT_RFK_FAIL = 3,
1800 	BTC_BCNT_RFK_TIMEOUT = 4,
1801 	BTC_BCNT_HI_TX = 5,
1802 	BTC_BCNT_HI_RX = 6,
1803 	BTC_BCNT_LO_TX = 7,
1804 	BTC_BCNT_LO_RX = 8,
1805 	BTC_BCNT_POLLUTED = 9,
1806 	BTC_BCNT_STA_MAX
1807 };
1808 
1809 enum rtw89_btc_bt_sta_counter_v105 {
1810 	BTC_BCNT_RFK_REQ_V105 = 0,
1811 	BTC_BCNT_HI_TX_V105 = 1,
1812 	BTC_BCNT_HI_RX_V105 = 2,
1813 	BTC_BCNT_LO_TX_V105 = 3,
1814 	BTC_BCNT_LO_RX_V105 = 4,
1815 	BTC_BCNT_POLLUTED_V105 = 5,
1816 	BTC_BCNT_STA_MAX_V105
1817 };
1818 
1819 struct rtw89_btc_fbtc_rpt_ctrl_v1 {
1820 	u16 fver; /* btc_ver::fcxbtcrpt */
1821 	u16 rpt_cnt; /* tmr counters */
1822 	u32 wl_fw_coex_ver; /* match which driver's coex version */
1823 	u32 wl_fw_cx_offload;
1824 	u32 wl_fw_ver;
1825 	u32 rpt_enable;
1826 	u32 rpt_para; /* ms */
1827 	u32 mb_send_fail_cnt; /* fw send mailbox fail counter */
1828 	u32 mb_send_ok_cnt; /* fw send mailbox ok counter */
1829 	u32 mb_recv_cnt; /* fw recv mailbox counter */
1830 	u32 mb_a2dp_empty_cnt; /* a2dp empty count */
1831 	u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */
1832 	u32 mb_a2dp_full_cnt; /* a2dp empty full counter */
1833 	u32 bt_rfk_cnt[BTC_BCNT_HI_TX];
1834 	u32 c2h_cnt; /* fw send c2h counter  */
1835 	u32 h2c_cnt; /* fw recv h2c counter */
1836 } __packed;
1837 
1838 struct rtw89_btc_fbtc_rpt_ctrl_info {
1839 	__le32 cnt; /* fw report counter */
1840 	__le32 en; /* report map */
1841 	__le32 para; /* not used */
1842 
1843 	__le32 cnt_c2h; /* fw send c2h counter  */
1844 	__le32 cnt_h2c; /* fw recv h2c counter */
1845 	__le32 len_c2h; /* The total length of the last C2H  */
1846 
1847 	__le32 cnt_aoac_rf_on;  /* rf-on counter for aoac switch notify */
1848 	__le32 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */
1849 } __packed;
1850 
1851 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 {
1852 	__le32 cx_ver; /* match which driver's coex version */
1853 	__le32 fw_ver;
1854 	__le32 en; /* report map */
1855 
1856 	__le16 cnt; /* fw report counter */
1857 	__le16 cnt_c2h; /* fw send c2h counter  */
1858 	__le16 cnt_h2c; /* fw recv h2c counter */
1859 	__le16 len_c2h; /* The total length of the last C2H  */
1860 
1861 	__le16 cnt_aoac_rf_on;  /* rf-on counter for aoac switch notify */
1862 	__le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */
1863 } __packed;
1864 
1865 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info {
1866 	__le32 cx_ver; /* match which driver's coex version */
1867 	__le32 cx_offload;
1868 	__le32 fw_ver;
1869 } __packed;
1870 
1871 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty {
1872 	__le32 cnt_empty; /* a2dp empty count */
1873 	__le32 cnt_flowctrl; /* a2dp empty flow control counter */
1874 	__le32 cnt_tx;
1875 	__le32 cnt_ack;
1876 	__le32 cnt_nack;
1877 } __packed;
1878 
1879 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox {
1880 	__le32 cnt_send_ok; /* fw send mailbox ok counter */
1881 	__le32 cnt_send_fail; /* fw send mailbox fail counter */
1882 	__le32 cnt_recv; /* fw recv mailbox counter */
1883 	struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty a2dp;
1884 } __packed;
1885 
1886 struct rtw89_btc_fbtc_rpt_ctrl_v4 {
1887 	u8 fver;
1888 	u8 rsvd;
1889 	__le16 rsvd1;
1890 	struct rtw89_btc_fbtc_rpt_ctrl_info rpt_info;
1891 	struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info wl_fw_info;
1892 	struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info;
1893 	__le32 bt_cnt[BTC_BCNT_STA_MAX];
1894 	struct rtw89_mac_ax_gnt gnt_val[RTW89_PHY_MAX];
1895 } __packed;
1896 
1897 struct rtw89_btc_fbtc_rpt_ctrl_v5 {
1898 	u8 fver;
1899 	u8 rsvd;
1900 	__le16 rsvd1;
1901 
1902 	u8 gnt_val[RTW89_PHY_MAX][4];
1903 	__le16 bt_cnt[BTC_BCNT_STA_MAX];
1904 
1905 	struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info;
1906 	struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info;
1907 } __packed;
1908 
1909 struct rtw89_btc_fbtc_rpt_ctrl_v105 {
1910 	u8 fver;
1911 	u8 rsvd;
1912 	__le16 rsvd1;
1913 
1914 	u8 gnt_val[RTW89_PHY_MAX][4];
1915 	__le16 bt_cnt[BTC_BCNT_STA_MAX_V105];
1916 
1917 	struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info;
1918 	struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info;
1919 } __packed;
1920 
1921 union rtw89_btc_fbtc_rpt_ctrl_ver_info {
1922 	struct rtw89_btc_fbtc_rpt_ctrl_v1 v1;
1923 	struct rtw89_btc_fbtc_rpt_ctrl_v4 v4;
1924 	struct rtw89_btc_fbtc_rpt_ctrl_v5 v5;
1925 	struct rtw89_btc_fbtc_rpt_ctrl_v105 v105;
1926 };
1927 
1928 enum rtw89_fbtc_ext_ctrl_type {
1929 	CXECTL_OFF = 0x0, /* tdma off */
1930 	CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */
1931 	CXECTL_EXT = 0x2,
1932 	CXECTL_MAX
1933 };
1934 
1935 union rtw89_btc_fbtc_rxflct {
1936 	u8 val;
1937 	u8 type: 3;
1938 	u8 tgln_n: 5;
1939 };
1940 
1941 enum rtw89_btc_cxst_state {
1942 	CXST_OFF = 0x0,
1943 	CXST_B2W = 0x1,
1944 	CXST_W1 = 0x2,
1945 	CXST_W2 = 0x3,
1946 	CXST_W2B = 0x4,
1947 	CXST_B1 = 0x5,
1948 	CXST_B2 = 0x6,
1949 	CXST_B3 = 0x7,
1950 	CXST_B4 = 0x8,
1951 	CXST_LK = 0x9,
1952 	CXST_BLK = 0xa,
1953 	CXST_E2G = 0xb,
1954 	CXST_E5G = 0xc,
1955 	CXST_EBT = 0xd,
1956 	CXST_ENULL = 0xe,
1957 	CXST_WLK = 0xf,
1958 	CXST_W1FDD = 0x10,
1959 	CXST_B1FDD = 0x11,
1960 	CXST_MAX = 0x12,
1961 };
1962 
1963 enum rtw89_btc_cxevnt {
1964 	CXEVNT_TDMA_ENTRY = 0x0,
1965 	CXEVNT_WL_TMR,
1966 	CXEVNT_B1_TMR,
1967 	CXEVNT_B2_TMR,
1968 	CXEVNT_B3_TMR,
1969 	CXEVNT_B4_TMR,
1970 	CXEVNT_W2B_TMR,
1971 	CXEVNT_B2W_TMR,
1972 	CXEVNT_BCN_EARLY,
1973 	CXEVNT_A2DP_EMPTY,
1974 	CXEVNT_LK_END,
1975 	CXEVNT_RX_ISR,
1976 	CXEVNT_RX_FC0,
1977 	CXEVNT_RX_FC1,
1978 	CXEVNT_BT_RELINK,
1979 	CXEVNT_BT_RETRY,
1980 	CXEVNT_E2G,
1981 	CXEVNT_E5G,
1982 	CXEVNT_EBT,
1983 	CXEVNT_ENULL,
1984 	CXEVNT_DRV_WLK,
1985 	CXEVNT_BCN_OK,
1986 	CXEVNT_BT_CHANGE,
1987 	CXEVNT_EBT_EXTEND,
1988 	CXEVNT_E2G_NULL1,
1989 	CXEVNT_B1FDD_TMR,
1990 	CXEVNT_MAX
1991 };
1992 
1993 enum {
1994 	CXBCN_ALL = 0x0,
1995 	CXBCN_ALL_OK,
1996 	CXBCN_BT_SLOT,
1997 	CXBCN_BT_OK,
1998 	CXBCN_MAX
1999 };
2000 
2001 enum btc_slot_type {
2002 	SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */
2003 	SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/
2004 	CXSTYPE_NUM,
2005 };
2006 
2007 enum { /* TIME */
2008 	CXT_BT = 0x0,
2009 	CXT_WL = 0x1,
2010 	CXT_MAX
2011 };
2012 
2013 enum { /* TIME-A2DP */
2014 	CXT_FLCTRL_OFF = 0x0,
2015 	CXT_FLCTRL_ON = 0x1,
2016 	CXT_FLCTRL_MAX
2017 };
2018 
2019 enum { /* STEP TYPE */
2020 	CXSTEP_NONE = 0x0,
2021 	CXSTEP_EVNT = 0x1,
2022 	CXSTEP_SLOT = 0x2,
2023 	CXSTEP_MAX,
2024 };
2025 
2026 enum rtw89_btc_afh_map_type { /*AFH MAP TYPE */
2027 	RPT_BT_AFH_SEQ_LEGACY = 0x10,
2028 	RPT_BT_AFH_SEQ_LE = 0x20
2029 };
2030 
2031 #define BTC_DBG_MAX1  32
2032 struct rtw89_btc_fbtc_gpio_dbg {
2033 	u8 fver; /* btc_ver::fcxgpiodbg */
2034 	u8 rsvd;
2035 	u16 rsvd2;
2036 	u32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */
2037 	u32 pre_state; /* the debug signal is 1 or 0  */
2038 	u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */
2039 } __packed;
2040 
2041 struct rtw89_btc_fbtc_mreg_val_v1 {
2042 	u8 fver; /* btc_ver::fcxmreg */
2043 	u8 reg_num;
2044 	__le16 rsvd;
2045 	__le32 mreg_val[CXMREG_MAX];
2046 } __packed;
2047 
2048 struct rtw89_btc_fbtc_mreg_val_v2 {
2049 	u8 fver; /* btc_ver::fcxmreg */
2050 	u8 reg_num;
2051 	__le16 rsvd;
2052 	__le32 mreg_val[CXMREG_MAX_V2];
2053 } __packed;
2054 
2055 union rtw89_btc_fbtc_mreg_val {
2056 	struct rtw89_btc_fbtc_mreg_val_v1 v1;
2057 	struct rtw89_btc_fbtc_mreg_val_v2 v2;
2058 };
2059 
2060 #define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \
2061 	{ .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \
2062 	  .offset = cpu_to_le32(__offset), }
2063 
2064 struct rtw89_btc_fbtc_mreg {
2065 	__le16 type;
2066 	__le16 bytes;
2067 	__le32 offset;
2068 } __packed;
2069 
2070 struct rtw89_btc_fbtc_slot {
2071 	__le16 dur;
2072 	__le32 cxtbl;
2073 	__le16 cxtype;
2074 } __packed;
2075 
2076 struct rtw89_btc_fbtc_slots {
2077 	u8 fver; /* btc_ver::fcxslots */
2078 	u8 tbl_num;
2079 	__le16 rsvd;
2080 	__le32 update_map;
2081 	struct rtw89_btc_fbtc_slot slot[CXST_MAX];
2082 } __packed;
2083 
2084 struct rtw89_btc_fbtc_step {
2085 	u8 type;
2086 	u8 val;
2087 	__le16 difft;
2088 } __packed;
2089 
2090 struct rtw89_btc_fbtc_steps_v2 {
2091 	u8 fver; /* btc_ver::fcxstep */
2092 	u8 rsvd;
2093 	__le16 cnt;
2094 	__le16 pos_old;
2095 	__le16 pos_new;
2096 	struct rtw89_btc_fbtc_step step[FCXMAX_STEP];
2097 } __packed;
2098 
2099 struct rtw89_btc_fbtc_steps_v3 {
2100 	u8 fver;
2101 	u8 en;
2102 	__le16 rsvd;
2103 	__le32 cnt;
2104 	struct rtw89_btc_fbtc_step step[FCXMAX_STEP];
2105 } __packed;
2106 
2107 union rtw89_btc_fbtc_steps_info {
2108 	struct rtw89_btc_fbtc_steps_v2 v2;
2109 	struct rtw89_btc_fbtc_steps_v3 v3;
2110 };
2111 
2112 struct rtw89_btc_fbtc_cysta_v2 { /* statistics for cycles */
2113 	u8 fver; /* btc_ver::fcxcysta */
2114 	u8 rsvd;
2115 	__le16 cycles; /* total cycle number */
2116 	__le16 cycles_a2dp[CXT_FLCTRL_MAX];
2117 	__le16 a2dpept; /* a2dp empty cnt */
2118 	__le16 a2dpeptto; /* a2dp empty timeout cnt*/
2119 	__le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */
2120 	__le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */
2121 	__le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */
2122 	__le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */
2123 	__le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */
2124 	__le16 tavg_a2dpept; /* avg a2dp empty time */
2125 	__le16 tmax_a2dpept; /* max a2dp empty time */
2126 	__le16 tavg_lk; /* avg leak-slot time */
2127 	__le16 tmax_lk; /* max leak-slot time */
2128 	__le32 slot_cnt[CXST_MAX]; /* slot count */
2129 	__le32 bcn_cnt[CXBCN_MAX];
2130 	__le32 leakrx_cnt; /* the rximr occur at leak slot  */
2131 	__le32 collision_cnt; /* counter for event/timer occur at same time */
2132 	__le32 skip_cnt;
2133 	__le32 exception;
2134 	__le32 except_cnt;
2135 	__le16 tslot_cycle[BTC_CYCLE_SLOT_MAX];
2136 } __packed;
2137 
2138 struct rtw89_btc_fbtc_fdd_try_info {
2139 	__le16 cycles[CXT_FLCTRL_MAX];
2140 	__le16 tavg[CXT_FLCTRL_MAX]; /* avg try BT-Slot-TDD/BT-slot-FDD time */
2141 	__le16 tmax[CXT_FLCTRL_MAX]; /* max try BT-Slot-TDD/BT-slot-FDD time */
2142 } __packed;
2143 
2144 struct rtw89_btc_fbtc_cycle_time_info {
2145 	__le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */
2146 	__le16 tmax[CXT_MAX]; /* max wl/bt cycle time */
2147 	__le16 tmaxdiff[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */
2148 } __packed;
2149 
2150 struct rtw89_btc_fbtc_cycle_time_info_v5 {
2151 	__le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */
2152 	__le16 tmax[CXT_MAX]; /* max wl/bt cycle time */
2153 } __packed;
2154 
2155 struct rtw89_btc_fbtc_a2dp_trx_stat {
2156 	u8 empty_cnt;
2157 	u8 retry_cnt;
2158 	u8 tx_rate;
2159 	u8 tx_cnt;
2160 	u8 ack_cnt;
2161 	u8 nack_cnt;
2162 	u8 rsvd1;
2163 	u8 rsvd2;
2164 } __packed;
2165 
2166 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 {
2167 	u8 empty_cnt;
2168 	u8 retry_cnt;
2169 	u8 tx_rate;
2170 	u8 tx_cnt;
2171 	u8 ack_cnt;
2172 	u8 nack_cnt;
2173 	u8 no_empty_cnt;
2174 	u8 rsvd;
2175 } __packed;
2176 
2177 struct rtw89_btc_fbtc_cycle_a2dp_empty_info {
2178 	__le16 cnt; /* a2dp empty cnt */
2179 	__le16 cnt_timeout; /* a2dp empty timeout cnt*/
2180 	__le16 tavg; /* avg a2dp empty time */
2181 	__le16 tmax; /* max a2dp empty time */
2182 } __packed;
2183 
2184 struct rtw89_btc_fbtc_cycle_leak_info {
2185 	__le32 cnt_rximr; /* the rximr occur at leak slot  */
2186 	__le16 tavg; /* avg leak-slot time */
2187 	__le16 tmax; /* max leak-slot time */
2188 } __packed;
2189 
2190 #define RTW89_BTC_FDDT_PHASE_CYCLE GENMASK(9, 0)
2191 #define RTW89_BTC_FDDT_TRAIN_STEP GENMASK(15, 10)
2192 
2193 struct rtw89_btc_fbtc_cycle_fddt_info {
2194 	__le16 train_cycle;
2195 	__le16 tp;
2196 
2197 	s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
2198 	s8 bt_tx_power; /* decrease Tx power (dB) */
2199 	s8 bt_rx_gain;  /* LNA constrain level */
2200 	u8 no_empty_cnt;
2201 
2202 	u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */
2203 	u8 cn; /* condition_num */
2204 	u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */
2205 	u8 train_result; /* refer to enum btc_fddt_check_map */
2206 } __packed;
2207 
2208 #define RTW89_BTC_FDDT_CELL_TRAIN_STATE GENMASK(3, 0)
2209 #define RTW89_BTC_FDDT_CELL_TRAIN_PHASE GENMASK(7, 4)
2210 
2211 struct rtw89_btc_fbtc_cycle_fddt_info_v5 {
2212 	__le16 train_cycle;
2213 	__le16 tp;
2214 
2215 	s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
2216 	s8 bt_tx_power; /* decrease Tx power (dB) */
2217 	s8 bt_rx_gain;  /* LNA constrain level */
2218 	u8 no_empty_cnt;
2219 
2220 	u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */
2221 	u8 cn; /* condition_num */
2222 	u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */
2223 	u8 train_result; /* refer to enum btc_fddt_check_map */
2224 } __packed;
2225 
2226 struct rtw89_btc_fbtc_fddt_cell_status {
2227 	s8 wl_tx_pwr;
2228 	s8 bt_tx_pwr;
2229 	s8 bt_rx_gain;
2230 	u8 state_phase; /* [0:3] train state, [4:7] train phase */
2231 } __packed;
2232 
2233 struct rtw89_btc_fbtc_fddt_cell_status_v5 {
2234 	s8 wl_tx_pwr;
2235 	s8 bt_tx_pwr;
2236 	s8 bt_rx_gain;
2237 } __packed;
2238 
2239 struct rtw89_btc_fbtc_cysta_v3 { /* statistics for cycles */
2240 	u8 fver;
2241 	u8 rsvd;
2242 	__le16 cycles; /* total cycle number */
2243 	__le16 slot_step_time[BTC_CYCLE_SLOT_MAX];
2244 	struct rtw89_btc_fbtc_cycle_time_info cycle_time;
2245 	struct rtw89_btc_fbtc_fdd_try_info fdd_try;
2246 	struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept;
2247 	struct rtw89_btc_fbtc_a2dp_trx_stat a2dp_trx[BTC_CYCLE_SLOT_MAX];
2248 	struct rtw89_btc_fbtc_cycle_leak_info leak_slot;
2249 	__le32 slot_cnt[CXST_MAX]; /* slot count */
2250 	__le32 bcn_cnt[CXBCN_MAX];
2251 	__le32 collision_cnt; /* counter for event/timer occur at the same time */
2252 	__le32 skip_cnt;
2253 	__le32 except_cnt;
2254 	__le32 except_map;
2255 } __packed;
2256 
2257 #define FDD_TRAIN_WL_DIRECTION 2
2258 #define FDD_TRAIN_WL_RSSI_LEVEL 5
2259 #define FDD_TRAIN_BT_RSSI_LEVEL 5
2260 
2261 struct rtw89_btc_fbtc_cysta_v4 { /* statistics for cycles */
2262 	u8 fver;
2263 	u8 rsvd;
2264 	u8 collision_cnt; /* counter for event/timer occur at the same time */
2265 	u8 except_cnt;
2266 
2267 	__le16 skip_cnt;
2268 	__le16 cycles; /* total cycle number */
2269 
2270 	__le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */
2271 	__le16 slot_cnt[CXST_MAX]; /* slot count */
2272 	__le16 bcn_cnt[CXBCN_MAX];
2273 	struct rtw89_btc_fbtc_cycle_time_info cycle_time;
2274 	struct rtw89_btc_fbtc_cycle_leak_info leak_slot;
2275 	struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept;
2276 	struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX];
2277 	struct rtw89_btc_fbtc_cycle_fddt_info fddt_trx[BTC_CYCLE_SLOT_MAX];
2278 	struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION]
2279 							 [FDD_TRAIN_WL_RSSI_LEVEL]
2280 							 [FDD_TRAIN_BT_RSSI_LEVEL];
2281 	__le32 except_map;
2282 } __packed;
2283 
2284 struct rtw89_btc_fbtc_cysta_v5 { /* statistics for cycles */
2285 	u8 fver;
2286 	u8 rsvd;
2287 	u8 collision_cnt; /* counter for event/timer occur at the same time */
2288 	u8 except_cnt;
2289 	u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX];
2290 
2291 	__le16 skip_cnt;
2292 	__le16 cycles; /* total cycle number */
2293 
2294 	__le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */
2295 	__le16 slot_cnt[CXST_MAX]; /* slot count */
2296 	__le16 bcn_cnt[CXBCN_MAX];
2297 	struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time;
2298 	struct rtw89_btc_fbtc_cycle_leak_info leak_slot;
2299 	struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept;
2300 	struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX];
2301 	struct rtw89_btc_fbtc_cycle_fddt_info_v5 fddt_trx[BTC_CYCLE_SLOT_MAX];
2302 	struct rtw89_btc_fbtc_fddt_cell_status_v5 fddt_cells[FDD_TRAIN_WL_DIRECTION]
2303 							    [FDD_TRAIN_WL_RSSI_LEVEL]
2304 							    [FDD_TRAIN_BT_RSSI_LEVEL];
2305 	__le32 except_map;
2306 } __packed;
2307 
2308 union rtw89_btc_fbtc_cysta_info {
2309 	struct rtw89_btc_fbtc_cysta_v2 v2;
2310 	struct rtw89_btc_fbtc_cysta_v3 v3;
2311 	struct rtw89_btc_fbtc_cysta_v4 v4;
2312 	struct rtw89_btc_fbtc_cysta_v5 v5;
2313 };
2314 
2315 struct rtw89_btc_fbtc_cynullsta_v1 { /* cycle null statistics */
2316 	u8 fver; /* btc_ver::fcxnullsta */
2317 	u8 rsvd;
2318 	__le16 rsvd2;
2319 	__le32 max_t[2]; /* max_t for 0:null0/1:null1 */
2320 	__le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */
2321 	__le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */
2322 } __packed;
2323 
2324 struct rtw89_btc_fbtc_cynullsta_v2 { /* cycle null statistics */
2325 	u8 fver; /* btc_ver::fcxnullsta */
2326 	u8 rsvd;
2327 	__le16 rsvd2;
2328 	__le32 max_t[2]; /* max_t for 0:null0/1:null1 */
2329 	__le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */
2330 	__le32 result[2][5]; /* 0:fail, 1:ok, 2:on_time, 3:retry, 4:tx */
2331 } __packed;
2332 
2333 union rtw89_btc_fbtc_cynullsta_info {
2334 	struct rtw89_btc_fbtc_cynullsta_v1 v1; /* info from fw */
2335 	struct rtw89_btc_fbtc_cynullsta_v2 v2;
2336 };
2337 
2338 struct rtw89_btc_fbtc_btver {
2339 	u8 fver; /* btc_ver::fcxbtver */
2340 	u8 rsvd;
2341 	__le16 rsvd2;
2342 	__le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */
2343 	__le32 fw_ver;
2344 	__le32 feature;
2345 } __packed;
2346 
2347 struct rtw89_btc_fbtc_btafh {
2348 	u8 fver; /* btc_ver::fcxbtafh */
2349 	u8 rsvd;
2350 	__le16 rsvd2;
2351 	u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */
2352 	u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */
2353 	u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */
2354 } __packed;
2355 
2356 struct rtw89_btc_fbtc_btafh_v2 {
2357 	u8 fver; /* btc_ver::fcxbtafh */
2358 	u8 rsvd;
2359 	u8 rsvd2;
2360 	u8 map_type;
2361 	u8 afh_l[4];
2362 	u8 afh_m[4];
2363 	u8 afh_h[4];
2364 	u8 afh_le_a[4];
2365 	u8 afh_le_b[4];
2366 } __packed;
2367 
2368 struct rtw89_btc_fbtc_btdevinfo {
2369 	u8 fver; /* btc_ver::fcxbtdevinfo */
2370 	u8 rsvd;
2371 	__le16 vendor_id;
2372 	__le32 dev_name; /* only 24 bits valid */
2373 	__le32 flush_time;
2374 } __packed;
2375 
2376 #define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0)
2377 struct rtw89_btc_rf_trx_para {
2378 	u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
2379 	u32 wl_rx_gain;  /* rx gain table index (TBD.) */
2380 	u8 bt_tx_power; /* decrease Tx power (dB) */
2381 	u8 bt_rx_gain;  /* LNA constrain level */
2382 };
2383 
2384 struct rtw89_btc_trx_info {
2385 	u8 tx_lvl;
2386 	u8 rx_lvl;
2387 	u8 wl_rssi;
2388 	u8 bt_rssi;
2389 
2390 	s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
2391 	s8 rx_gain;  /* rx gain table index (TBD.) */
2392 	s8 bt_tx_power; /* decrease Tx power (dB) */
2393 	s8 bt_rx_gain;  /* LNA constrain level */
2394 
2395 	u8 cn; /* condition_num */
2396 	s8 nhm;
2397 	u8 bt_profile;
2398 	u8 rsvd2;
2399 
2400 	u16 tx_rate;
2401 	u16 rx_rate;
2402 
2403 	u32 tx_tp;
2404 	u32 rx_tp;
2405 	u32 rx_err_ratio;
2406 };
2407 
2408 struct rtw89_btc_dm {
2409 	struct rtw89_btc_fbtc_slot slot[CXST_MAX];
2410 	struct rtw89_btc_fbtc_slot slot_now[CXST_MAX];
2411 	struct rtw89_btc_fbtc_tdma tdma;
2412 	struct rtw89_btc_fbtc_tdma tdma_now;
2413 	struct rtw89_mac_ax_coex_gnt gnt;
2414 	struct rtw89_btc_init_info init_info; /* pass to wl_fw if offload */
2415 	struct rtw89_btc_rf_trx_para rf_trx_para;
2416 	struct rtw89_btc_wl_tx_limit_para wl_tx_limit;
2417 	struct rtw89_btc_dm_step dm_step;
2418 	struct rtw89_btc_wl_scc_ctrl wl_scc;
2419 	struct rtw89_btc_trx_info trx_info;
2420 	union rtw89_btc_dm_error_map error;
2421 	u32 cnt_dm[BTC_DCNT_NUM];
2422 	u32 cnt_notify[BTC_NCNT_NUM];
2423 
2424 	u32 update_slot_map;
2425 	u32 set_ant_path;
2426 
2427 	u32 wl_only: 1;
2428 	u32 wl_fw_cx_offload: 1;
2429 	u32 freerun: 1;
2430 	u32 fddt_train: 1;
2431 	u32 wl_ps_ctrl: 2;
2432 	u32 wl_mimo_ps: 1;
2433 	u32 leak_ap: 1;
2434 	u32 noisy_level: 3;
2435 	u32 coex_info_map: 8;
2436 	u32 bt_only: 1;
2437 	u32 wl_btg_rx: 1;
2438 	u32 trx_para_level: 8;
2439 	u32 wl_stb_chg: 1;
2440 	u32 pta_owner: 1;
2441 	u32 tdma_instant_excute: 1;
2442 
2443 	u16 slot_dur[CXST_MAX];
2444 
2445 	u8 run_reason;
2446 	u8 run_action;
2447 
2448 	u8 wl_lna2: 1;
2449 };
2450 
2451 struct rtw89_btc_ctrl {
2452 	u32 manual: 1;
2453 	u32 igno_bt: 1;
2454 	u32 always_freerun: 1;
2455 	u32 trace_step: 16;
2456 	u32 rsvd: 12;
2457 };
2458 
2459 struct rtw89_btc_dbg {
2460 	/* cmd "rb" */
2461 	bool rb_done;
2462 	u32 rb_val;
2463 };
2464 
2465 enum rtw89_btc_btf_fw_event {
2466 	BTF_EVNT_RPT = 0,
2467 	BTF_EVNT_BT_INFO = 1,
2468 	BTF_EVNT_BT_SCBD = 2,
2469 	BTF_EVNT_BT_REG = 3,
2470 	BTF_EVNT_CX_RUNINFO = 4,
2471 	BTF_EVNT_BT_PSD = 5,
2472 	BTF_EVNT_BUF_OVERFLOW,
2473 	BTF_EVNT_C2H_LOOPBACK,
2474 	BTF_EVNT_MAX,
2475 };
2476 
2477 enum btf_fw_event_report {
2478 	BTC_RPT_TYPE_CTRL = 0x0,
2479 	BTC_RPT_TYPE_TDMA,
2480 	BTC_RPT_TYPE_SLOT,
2481 	BTC_RPT_TYPE_CYSTA,
2482 	BTC_RPT_TYPE_STEP,
2483 	BTC_RPT_TYPE_NULLSTA,
2484 	BTC_RPT_TYPE_MREG,
2485 	BTC_RPT_TYPE_GPIO_DBG,
2486 	BTC_RPT_TYPE_BT_VER,
2487 	BTC_RPT_TYPE_BT_SCAN,
2488 	BTC_RPT_TYPE_BT_AFH,
2489 	BTC_RPT_TYPE_BT_DEVICE,
2490 	BTC_RPT_TYPE_TEST,
2491 	BTC_RPT_TYPE_MAX = 31
2492 };
2493 
2494 enum rtw_btc_btf_reg_type {
2495 	REG_MAC = 0x0,
2496 	REG_BB = 0x1,
2497 	REG_RF = 0x2,
2498 	REG_BT_RF = 0x3,
2499 	REG_BT_MODEM = 0x4,
2500 	REG_BT_BLUEWIZE = 0x5,
2501 	REG_BT_VENDOR = 0x6,
2502 	REG_BT_LE = 0x7,
2503 	REG_MAX_TYPE,
2504 };
2505 
2506 struct rtw89_btc_rpt_cmn_info {
2507 	u32 rx_cnt;
2508 	u32 rx_len;
2509 	u32 req_len; /* expected rsp len */
2510 	u8 req_fver; /* expected rsp fver */
2511 	u8 rsp_fver; /* fver from fw */
2512 	u8 valid;
2513 } __packed;
2514 
2515 union rtw89_btc_fbtc_btafh_info {
2516 	struct rtw89_btc_fbtc_btafh v1;
2517 	struct rtw89_btc_fbtc_btafh_v2 v2;
2518 };
2519 
2520 struct rtw89_btc_report_ctrl_state {
2521 	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2522 	union rtw89_btc_fbtc_rpt_ctrl_ver_info finfo;
2523 };
2524 
2525 struct rtw89_btc_rpt_fbtc_tdma {
2526 	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2527 	union rtw89_btc_fbtc_tdma_le32 finfo;
2528 };
2529 
2530 struct rtw89_btc_rpt_fbtc_slots {
2531 	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2532 	struct rtw89_btc_fbtc_slots finfo; /* info from fw */
2533 };
2534 
2535 struct rtw89_btc_rpt_fbtc_cysta {
2536 	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2537 	union rtw89_btc_fbtc_cysta_info finfo;
2538 };
2539 
2540 struct rtw89_btc_rpt_fbtc_step {
2541 	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2542 	union rtw89_btc_fbtc_steps_info finfo; /* info from fw */
2543 };
2544 
2545 struct rtw89_btc_rpt_fbtc_nullsta {
2546 	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2547 	union rtw89_btc_fbtc_cynullsta_info finfo;
2548 };
2549 
2550 struct rtw89_btc_rpt_fbtc_mreg {
2551 	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2552 	union rtw89_btc_fbtc_mreg_val finfo; /* info from fw */
2553 };
2554 
2555 struct rtw89_btc_rpt_fbtc_gpio_dbg {
2556 	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2557 	struct rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */
2558 };
2559 
2560 struct rtw89_btc_rpt_fbtc_btver {
2561 	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2562 	struct rtw89_btc_fbtc_btver finfo; /* info from fw */
2563 };
2564 
2565 struct rtw89_btc_rpt_fbtc_btscan {
2566 	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2567 	union rtw89_btc_fbtc_btscan finfo; /* info from fw */
2568 };
2569 
2570 struct rtw89_btc_rpt_fbtc_btafh {
2571 	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2572 	union rtw89_btc_fbtc_btafh_info finfo;
2573 };
2574 
2575 struct rtw89_btc_rpt_fbtc_btdev {
2576 	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2577 	struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */
2578 };
2579 
2580 enum rtw89_btc_btfre_type {
2581 	BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */
2582 	BTFRE_UNDEF_TYPE,
2583 	BTFRE_EXCEPTION,
2584 	BTFRE_MAX,
2585 };
2586 
2587 struct rtw89_btc_btf_fwinfo {
2588 	u32 cnt_c2h;
2589 	u32 cnt_h2c;
2590 	u32 cnt_h2c_fail;
2591 	u32 event[BTF_EVNT_MAX];
2592 
2593 	u32 err[BTFRE_MAX];
2594 	u32 len_mismch;
2595 	u32 fver_mismch;
2596 	u32 rpt_en_map;
2597 
2598 	struct rtw89_btc_report_ctrl_state rpt_ctrl;
2599 	struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma;
2600 	struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots;
2601 	struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta;
2602 	struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step;
2603 	struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta;
2604 	struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval;
2605 	struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg;
2606 	struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver;
2607 	struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan;
2608 	struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh;
2609 	struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev;
2610 };
2611 
2612 struct rtw89_btc_ver {
2613 	enum rtw89_core_chip_id chip_id;
2614 	u32 fw_ver_code;
2615 
2616 	u8 fcxbtcrpt;
2617 	u8 fcxtdma;
2618 	u8 fcxslots;
2619 	u8 fcxcysta;
2620 	u8 fcxstep;
2621 	u8 fcxnullsta;
2622 	u8 fcxmreg;
2623 	u8 fcxgpiodbg;
2624 	u8 fcxbtver;
2625 	u8 fcxbtscan;
2626 	u8 fcxbtafh;
2627 	u8 fcxbtdevinfo;
2628 	u8 fwlrole;
2629 	u8 frptmap;
2630 	u8 fcxctrl;
2631 
2632 	u16 info_buf;
2633 	u8 max_role_num;
2634 };
2635 
2636 #define RTW89_BTC_POLICY_MAXLEN 512
2637 
2638 struct rtw89_btc {
2639 	const struct rtw89_btc_ver *ver;
2640 
2641 	struct rtw89_btc_cx cx;
2642 	struct rtw89_btc_dm dm;
2643 	struct rtw89_btc_ctrl ctrl;
2644 	struct rtw89_btc_module mdinfo;
2645 	struct rtw89_btc_btf_fwinfo fwinfo;
2646 	struct rtw89_btc_dbg dbg;
2647 
2648 	struct work_struct eapol_notify_work;
2649 	struct work_struct arp_notify_work;
2650 	struct work_struct dhcp_notify_work;
2651 	struct work_struct icmp_notify_work;
2652 
2653 	u32 bt_req_len;
2654 
2655 	u8 policy[RTW89_BTC_POLICY_MAXLEN];
2656 	u16 policy_len;
2657 	u16 policy_type;
2658 	bool bt_req_en;
2659 	bool update_policy_force;
2660 	bool lps;
2661 };
2662 
2663 enum rtw89_btc_hmsg {
2664 	RTW89_BTC_HMSG_TMR_EN = 0x0,
2665 	RTW89_BTC_HMSG_BT_REG_READBACK = 0x1,
2666 	RTW89_BTC_HMSG_SET_BT_REQ_SLOT = 0x2,
2667 	RTW89_BTC_HMSG_FW_EV = 0x3,
2668 	RTW89_BTC_HMSG_BT_LINK_CHG = 0x4,
2669 	RTW89_BTC_HMSG_SET_BT_REQ_STBC = 0x5,
2670 
2671 	NUM_OF_RTW89_BTC_HMSG,
2672 };
2673 
2674 enum rtw89_ra_mode {
2675 	RTW89_RA_MODE_CCK = BIT(0),
2676 	RTW89_RA_MODE_OFDM = BIT(1),
2677 	RTW89_RA_MODE_HT = BIT(2),
2678 	RTW89_RA_MODE_VHT = BIT(3),
2679 	RTW89_RA_MODE_HE = BIT(4),
2680 };
2681 
2682 enum rtw89_ra_report_mode {
2683 	RTW89_RA_RPT_MODE_LEGACY,
2684 	RTW89_RA_RPT_MODE_HT,
2685 	RTW89_RA_RPT_MODE_VHT,
2686 	RTW89_RA_RPT_MODE_HE,
2687 };
2688 
2689 enum rtw89_dig_noisy_level {
2690 	RTW89_DIG_NOISY_LEVEL0 = -1,
2691 	RTW89_DIG_NOISY_LEVEL1 = 0,
2692 	RTW89_DIG_NOISY_LEVEL2 = 1,
2693 	RTW89_DIG_NOISY_LEVEL3 = 2,
2694 	RTW89_DIG_NOISY_LEVEL_MAX = 3,
2695 };
2696 
2697 enum rtw89_gi_ltf {
2698 	RTW89_GILTF_LGI_4XHE32 = 0,
2699 	RTW89_GILTF_SGI_4XHE08 = 1,
2700 	RTW89_GILTF_2XHE16 = 2,
2701 	RTW89_GILTF_2XHE08 = 3,
2702 	RTW89_GILTF_1XHE16 = 4,
2703 	RTW89_GILTF_1XHE08 = 5,
2704 	RTW89_GILTF_MAX
2705 };
2706 
2707 enum rtw89_rx_frame_type {
2708 	RTW89_RX_TYPE_MGNT = 0,
2709 	RTW89_RX_TYPE_CTRL = 1,
2710 	RTW89_RX_TYPE_DATA = 2,
2711 	RTW89_RX_TYPE_RSVD = 3,
2712 };
2713 
2714 struct rtw89_ra_info {
2715 	u8 is_dis_ra:1;
2716 	/* Bit0 : CCK
2717 	 * Bit1 : OFDM
2718 	 * Bit2 : HT
2719 	 * Bit3 : VHT
2720 	 * Bit4 : HE
2721 	 * Bit5 : EHT
2722 	 */
2723 	u8 mode_ctrl:6;
2724 	u8 bw_cap:3; /* enum rtw89_bandwidth */
2725 	u8 macid;
2726 	u8 dcm_cap:1;
2727 	u8 er_cap:1;
2728 	u8 init_rate_lv:2;
2729 	u8 upd_all:1;
2730 	u8 en_sgi:1;
2731 	u8 ldpc_cap:1;
2732 	u8 stbc_cap:1;
2733 	u8 ss_num:3;
2734 	u8 giltf:3;
2735 	u8 upd_bw_nss_mask:1;
2736 	u8 upd_mask:1;
2737 	u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */
2738 	/* BFee CSI */
2739 	u8 band_num;
2740 	u8 ra_csi_rate_en:1;
2741 	u8 fixed_csi_rate_en:1;
2742 	u8 cr_tbl_sel:1;
2743 	u8 fix_giltf_en:1;
2744 	u8 fix_giltf:3;
2745 	u8 rsvd2:1;
2746 	u8 csi_mcs_ss_idx;
2747 	u8 csi_mode:2;
2748 	u8 csi_gi_ltf:3;
2749 	u8 csi_bw:3;
2750 };
2751 
2752 #define RTW89_PPDU_MAX_USR 4
2753 #define RTW89_PPDU_MAC_INFO_USR_SIZE 4
2754 #define RTW89_PPDU_MAC_INFO_SIZE 8
2755 #define RTW89_PPDU_MAC_RX_CNT_SIZE 96
2756 
2757 #define RTW89_MAX_RX_AGG_NUM 64
2758 #define RTW89_MAX_TX_AGG_NUM 128
2759 
2760 struct rtw89_ampdu_params {
2761 	u16 agg_num;
2762 	bool amsdu;
2763 };
2764 
2765 struct rtw89_ra_report {
2766 	struct rate_info txrate;
2767 	u32 bit_rate;
2768 	u16 hw_rate;
2769 	bool might_fallback_legacy;
2770 };
2771 
2772 DECLARE_EWMA(rssi, 10, 16);
2773 DECLARE_EWMA(evm, 10, 16);
2774 DECLARE_EWMA(snr, 10, 16);
2775 
2776 struct rtw89_ba_cam_entry {
2777 	struct list_head list;
2778 	u8 tid;
2779 };
2780 
2781 #define RTW89_MAX_ADDR_CAM_NUM		128
2782 #define RTW89_MAX_BSSID_CAM_NUM		20
2783 #define RTW89_MAX_SEC_CAM_NUM		128
2784 #define RTW89_MAX_BA_CAM_NUM		8
2785 #define RTW89_SEC_CAM_IN_ADDR_CAM	7
2786 
2787 struct rtw89_addr_cam_entry {
2788 	u8 addr_cam_idx;
2789 	u8 offset;
2790 	u8 len;
2791 	u8 valid	: 1;
2792 	u8 addr_mask	: 6;
2793 	u8 wapi		: 1;
2794 	u8 mask_sel	: 2;
2795 	u8 bssid_cam_idx: 6;
2796 
2797 	u8 sec_ent_mode;
2798 	DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM);
2799 	u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM];
2800 	u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM];
2801 	struct rtw89_sec_cam_entry *sec_entries[RTW89_SEC_CAM_IN_ADDR_CAM];
2802 };
2803 
2804 struct rtw89_bssid_cam_entry {
2805 	u8 bssid[ETH_ALEN];
2806 	u8 phy_idx;
2807 	u8 bssid_cam_idx;
2808 	u8 offset;
2809 	u8 len;
2810 	u8 valid : 1;
2811 	u8 num;
2812 };
2813 
2814 struct rtw89_sec_cam_entry {
2815 	u8 sec_cam_idx;
2816 	u8 offset;
2817 	u8 len;
2818 	u8 type : 4;
2819 	u8 ext_key : 1;
2820 	u8 spp_mode : 1;
2821 	/* 256 bits */
2822 	u8 key[32];
2823 };
2824 
2825 struct rtw89_sta {
2826 	u8 mac_id;
2827 	bool disassoc;
2828 	bool er_cap;
2829 	struct rtw89_dev *rtwdev;
2830 	struct rtw89_vif *rtwvif;
2831 	struct rtw89_ra_info ra;
2832 	struct rtw89_ra_report ra_report;
2833 	int max_agg_wait;
2834 	u8 prev_rssi;
2835 	struct ewma_rssi avg_rssi;
2836 	struct ewma_rssi rssi[RF_PATH_MAX];
2837 	struct ewma_snr avg_snr;
2838 	struct ewma_evm evm_min[RF_PATH_MAX];
2839 	struct ewma_evm evm_max[RF_PATH_MAX];
2840 	struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS];
2841 	struct ieee80211_rx_status rx_status;
2842 	u16 rx_hw_rate;
2843 	__le32 htc_template;
2844 	struct rtw89_addr_cam_entry addr_cam; /* AP mode or TDLS peer only */
2845 	struct rtw89_bssid_cam_entry bssid_cam; /* TDLS peer only */
2846 	struct list_head ba_cam_list;
2847 	struct sk_buff_head roc_queue;
2848 
2849 	bool use_cfg_mask;
2850 	struct cfg80211_bitrate_mask mask;
2851 
2852 	bool cctl_tx_time;
2853 	u32 ampdu_max_time:4;
2854 	bool cctl_tx_retry_limit;
2855 	u32 data_tx_cnt_lmt:6;
2856 };
2857 
2858 struct rtw89_efuse {
2859 	bool valid;
2860 	bool power_k_valid;
2861 	u8 xtal_cap;
2862 	u8 addr[ETH_ALEN];
2863 	u8 rfe_type;
2864 	char country_code[2];
2865 };
2866 
2867 struct rtw89_phy_rate_pattern {
2868 	u64 ra_mask;
2869 	u16 rate;
2870 	u8 ra_mode;
2871 	bool enable;
2872 };
2873 
2874 struct rtw89_tx_wait_info {
2875 	struct rcu_head rcu_head;
2876 	struct completion completion;
2877 	bool tx_done;
2878 };
2879 
2880 struct rtw89_tx_skb_data {
2881 	struct rtw89_tx_wait_info __rcu *wait;
2882 	u8 hci_priv[];
2883 };
2884 
2885 #define RTW89_ROC_IDLE_TIMEOUT 500
2886 #define RTW89_ROC_TX_TIMEOUT 30
2887 enum rtw89_roc_state {
2888 	RTW89_ROC_IDLE,
2889 	RTW89_ROC_NORMAL,
2890 	RTW89_ROC_MGMT,
2891 };
2892 
2893 struct rtw89_roc {
2894 	struct ieee80211_channel chan;
2895 	struct delayed_work roc_work;
2896 	enum ieee80211_roc_type type;
2897 	enum rtw89_roc_state state;
2898 	int duration;
2899 };
2900 
2901 #define RTW89_P2P_MAX_NOA_NUM 2
2902 
2903 struct rtw89_p2p_ie_head {
2904 	u8 eid;
2905 	u8 ie_len;
2906 	u8 oui[3];
2907 	u8 oui_type;
2908 } __packed;
2909 
2910 struct rtw89_noa_attr_head {
2911 	u8 attr_type;
2912 	__le16 attr_len;
2913 	u8 index;
2914 	u8 oppps_ctwindow;
2915 } __packed;
2916 
2917 struct rtw89_p2p_noa_ie {
2918 	struct rtw89_p2p_ie_head p2p_head;
2919 	struct rtw89_noa_attr_head noa_head;
2920 	struct ieee80211_p2p_noa_desc noa_desc[RTW89_P2P_MAX_NOA_NUM];
2921 } __packed;
2922 
2923 struct rtw89_p2p_noa_setter {
2924 	struct rtw89_p2p_noa_ie ie;
2925 	u8 noa_count;
2926 	u8 noa_index;
2927 };
2928 
2929 struct rtw89_vif {
2930 	struct list_head list;
2931 	struct rtw89_dev *rtwdev;
2932 	struct rtw89_roc roc;
2933 	enum rtw89_sub_entity_idx sub_entity_idx;
2934 	enum rtw89_reg_6ghz_power reg_6ghz_power;
2935 
2936 	u8 mac_id;
2937 	u8 port;
2938 	u8 mac_addr[ETH_ALEN];
2939 	u8 bssid[ETH_ALEN];
2940 	u8 phy_idx;
2941 	u8 mac_idx;
2942 	u8 net_type;
2943 	u8 wifi_role;
2944 	u8 self_role;
2945 	u8 wmm;
2946 	u8 bcn_hit_cond;
2947 	u8 hit_rule;
2948 	u8 last_noa_nr;
2949 	bool offchan;
2950 	bool trigger;
2951 	bool lsig_txop;
2952 	u8 tgt_ind;
2953 	u8 frm_tgt_ind;
2954 	bool wowlan_pattern;
2955 	bool wowlan_uc;
2956 	bool wowlan_magic;
2957 	bool is_hesta;
2958 	bool last_a_ctrl;
2959 	bool dyn_tb_bedge_en;
2960 	u8 def_tri_idx;
2961 	u32 tdls_peer;
2962 	struct work_struct update_beacon_work;
2963 	struct rtw89_addr_cam_entry addr_cam;
2964 	struct rtw89_bssid_cam_entry bssid_cam;
2965 	struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS];
2966 	struct rtw89_traffic_stats stats;
2967 	struct rtw89_phy_rate_pattern rate_pattern;
2968 	struct cfg80211_scan_request *scan_req;
2969 	struct ieee80211_scan_ies *scan_ies;
2970 	struct list_head general_pkt_list;
2971 	struct rtw89_p2p_noa_setter p2p_noa;
2972 };
2973 
2974 enum rtw89_lv1_rcvy_step {
2975 	RTW89_LV1_RCVY_STEP_1,
2976 	RTW89_LV1_RCVY_STEP_2,
2977 };
2978 
2979 struct rtw89_hci_ops {
2980 	int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req);
2981 	void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch);
2982 	void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop);
2983 	void (*reset)(struct rtw89_dev *rtwdev);
2984 	int (*start)(struct rtw89_dev *rtwdev);
2985 	void (*stop)(struct rtw89_dev *rtwdev);
2986 	void (*pause)(struct rtw89_dev *rtwdev, bool pause);
2987 	void (*switch_mode)(struct rtw89_dev *rtwdev, bool low_power);
2988 	void (*recalc_int_mit)(struct rtw89_dev *rtwdev);
2989 
2990 	u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr);
2991 	u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr);
2992 	u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr);
2993 	void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data);
2994 	void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data);
2995 	void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data);
2996 
2997 	int (*mac_pre_init)(struct rtw89_dev *rtwdev);
2998 	int (*mac_post_init)(struct rtw89_dev *rtwdev);
2999 	int (*deinit)(struct rtw89_dev *rtwdev);
3000 
3001 	u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch);
3002 	int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step);
3003 	void (*dump_err_status)(struct rtw89_dev *rtwdev);
3004 	int (*napi_poll)(struct napi_struct *napi, int budget);
3005 
3006 	/* Deal with locks inside recovery_start and recovery_complete callbacks
3007 	 * by hci instance, and handle things which need to consider under SER.
3008 	 * e.g. turn on/off interrupts except for the one for halt notification.
3009 	 */
3010 	void (*recovery_start)(struct rtw89_dev *rtwdev);
3011 	void (*recovery_complete)(struct rtw89_dev *rtwdev);
3012 
3013 	void (*ctrl_txdma_ch)(struct rtw89_dev *rtwdev, bool enable);
3014 	void (*ctrl_txdma_fw_ch)(struct rtw89_dev *rtwdev, bool enable);
3015 	void (*ctrl_trxhci)(struct rtw89_dev *rtwdev, bool enable);
3016 	int (*poll_txdma_ch)(struct rtw89_dev *rtwdev);
3017 	void (*clr_idx_all)(struct rtw89_dev *rtwdev);
3018 	void (*clear)(struct rtw89_dev *rtwdev, struct pci_dev *pdev);
3019 	void (*disable_intr)(struct rtw89_dev *rtwdev);
3020 	void (*enable_intr)(struct rtw89_dev *rtwdev);
3021 	int (*rst_bdram)(struct rtw89_dev *rtwdev);
3022 };
3023 
3024 struct rtw89_hci_info {
3025 	const struct rtw89_hci_ops *ops;
3026 	enum rtw89_hci_type type;
3027 	u32 rpwm_addr;
3028 	u32 cpwm_addr;
3029 	bool paused;
3030 };
3031 
3032 struct rtw89_chip_ops {
3033 	int (*enable_bb_rf)(struct rtw89_dev *rtwdev);
3034 	int (*disable_bb_rf)(struct rtw89_dev *rtwdev);
3035 	void (*bb_reset)(struct rtw89_dev *rtwdev,
3036 			 enum rtw89_phy_idx phy_idx);
3037 	void (*bb_sethw)(struct rtw89_dev *rtwdev);
3038 	u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
3039 		       u32 addr, u32 mask);
3040 	bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
3041 			 u32 addr, u32 mask, u32 data);
3042 	void (*set_channel)(struct rtw89_dev *rtwdev,
3043 			    const struct rtw89_chan *chan,
3044 			    enum rtw89_mac_idx mac_idx,
3045 			    enum rtw89_phy_idx phy_idx);
3046 	void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter,
3047 				 struct rtw89_channel_help_params *p,
3048 				 const struct rtw89_chan *chan,
3049 				 enum rtw89_mac_idx mac_idx,
3050 				 enum rtw89_phy_idx phy_idx);
3051 	int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map);
3052 	int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map);
3053 	void (*fem_setup)(struct rtw89_dev *rtwdev);
3054 	void (*rfe_gpio)(struct rtw89_dev *rtwdev);
3055 	void (*rfk_init)(struct rtw89_dev *rtwdev);
3056 	void (*rfk_channel)(struct rtw89_dev *rtwdev);
3057 	void (*rfk_band_changed)(struct rtw89_dev *rtwdev,
3058 				 enum rtw89_phy_idx phy_idx);
3059 	void (*rfk_scan)(struct rtw89_dev *rtwdev, bool start);
3060 	void (*rfk_track)(struct rtw89_dev *rtwdev);
3061 	void (*power_trim)(struct rtw89_dev *rtwdev);
3062 	void (*set_txpwr)(struct rtw89_dev *rtwdev,
3063 			  const struct rtw89_chan *chan,
3064 			  enum rtw89_phy_idx phy_idx);
3065 	void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev,
3066 			       enum rtw89_phy_idx phy_idx);
3067 	int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
3068 	u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path);
3069 	void (*ctrl_btg)(struct rtw89_dev *rtwdev, bool btg);
3070 	void (*query_ppdu)(struct rtw89_dev *rtwdev,
3071 			   struct rtw89_rx_phy_ppdu *phy_ppdu,
3072 			   struct ieee80211_rx_status *status);
3073 	void (*bb_ctrl_btc_preagc)(struct rtw89_dev *rtwdev, bool bt_en);
3074 	void (*cfg_txrx_path)(struct rtw89_dev *rtwdev);
3075 	void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev,
3076 				       s8 pw_ofst, enum rtw89_mac_idx mac_idx);
3077 	int (*pwr_on_func)(struct rtw89_dev *rtwdev);
3078 	int (*pwr_off_func)(struct rtw89_dev *rtwdev);
3079 	void (*query_rxdesc)(struct rtw89_dev *rtwdev,
3080 			     struct rtw89_rx_desc_info *desc_info,
3081 			     u8 *data, u32 data_offset);
3082 	void (*fill_txdesc)(struct rtw89_dev *rtwdev,
3083 			    struct rtw89_tx_desc_info *desc_info,
3084 			    void *txdesc);
3085 	void (*fill_txdesc_fwcmd)(struct rtw89_dev *rtwdev,
3086 				  struct rtw89_tx_desc_info *desc_info,
3087 				  void *txdesc);
3088 	int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl);
3089 	int (*mac_cfg_gnt)(struct rtw89_dev *rtwdev,
3090 			   const struct rtw89_mac_ax_coex_gnt *gnt_cfg);
3091 	int (*stop_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx,
3092 			   u32 *tx_en, enum rtw89_sch_tx_sel sel);
3093 	int (*resume_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en);
3094 	int (*h2c_dctl_sec_cam)(struct rtw89_dev *rtwdev,
3095 				struct rtw89_vif *rtwvif,
3096 				struct rtw89_sta *rtwsta);
3097 
3098 	void (*btc_set_rfe)(struct rtw89_dev *rtwdev);
3099 	void (*btc_init_cfg)(struct rtw89_dev *rtwdev);
3100 	void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state);
3101 	void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val);
3102 	s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val);
3103 	void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev);
3104 	void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state);
3105 	void (*btc_set_policy)(struct rtw89_dev *rtwdev, u16 policy_type);
3106 	void (*btc_set_wl_rx_gain)(struct rtw89_dev *rtwdev, u32 level);
3107 };
3108 
3109 enum rtw89_dma_ch {
3110 	RTW89_DMA_ACH0 = 0,
3111 	RTW89_DMA_ACH1 = 1,
3112 	RTW89_DMA_ACH2 = 2,
3113 	RTW89_DMA_ACH3 = 3,
3114 	RTW89_DMA_ACH4 = 4,
3115 	RTW89_DMA_ACH5 = 5,
3116 	RTW89_DMA_ACH6 = 6,
3117 	RTW89_DMA_ACH7 = 7,
3118 	RTW89_DMA_B0MG = 8,
3119 	RTW89_DMA_B0HI = 9,
3120 	RTW89_DMA_B1MG = 10,
3121 	RTW89_DMA_B1HI = 11,
3122 	RTW89_DMA_H2C = 12,
3123 	RTW89_DMA_CH_NUM = 13
3124 };
3125 
3126 enum rtw89_qta_mode {
3127 	RTW89_QTA_SCC,
3128 	RTW89_QTA_DLFW,
3129 	RTW89_QTA_WOW,
3130 
3131 	/* keep last */
3132 	RTW89_QTA_INVALID,
3133 };
3134 
3135 struct rtw89_hfc_ch_cfg {
3136 	u16 min;
3137 	u16 max;
3138 #define grp_0 0
3139 #define grp_1 1
3140 #define grp_num 2
3141 	u8 grp;
3142 };
3143 
3144 struct rtw89_hfc_ch_info {
3145 	u16 aval;
3146 	u16 used;
3147 };
3148 
3149 struct rtw89_hfc_pub_cfg {
3150 	u16 grp0;
3151 	u16 grp1;
3152 	u16 pub_max;
3153 	u16 wp_thrd;
3154 };
3155 
3156 struct rtw89_hfc_pub_info {
3157 	u16 g0_used;
3158 	u16 g1_used;
3159 	u16 g0_aval;
3160 	u16 g1_aval;
3161 	u16 pub_aval;
3162 	u16 wp_aval;
3163 };
3164 
3165 struct rtw89_hfc_prec_cfg {
3166 	u16 ch011_prec;
3167 	u16 h2c_prec;
3168 	u16 wp_ch07_prec;
3169 	u16 wp_ch811_prec;
3170 	u8 ch011_full_cond;
3171 	u8 h2c_full_cond;
3172 	u8 wp_ch07_full_cond;
3173 	u8 wp_ch811_full_cond;
3174 };
3175 
3176 struct rtw89_hfc_param {
3177 	bool en;
3178 	bool h2c_en;
3179 	u8 mode;
3180 	const struct rtw89_hfc_ch_cfg *ch_cfg;
3181 	struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM];
3182 	struct rtw89_hfc_pub_cfg pub_cfg;
3183 	struct rtw89_hfc_pub_info pub_info;
3184 	struct rtw89_hfc_prec_cfg prec_cfg;
3185 };
3186 
3187 struct rtw89_hfc_param_ini {
3188 	const struct rtw89_hfc_ch_cfg *ch_cfg;
3189 	const struct rtw89_hfc_pub_cfg *pub_cfg;
3190 	const struct rtw89_hfc_prec_cfg *prec_cfg;
3191 	u8 mode;
3192 };
3193 
3194 struct rtw89_dle_size {
3195 	u16 pge_size;
3196 	u16 lnk_pge_num;
3197 	u16 unlnk_pge_num;
3198 };
3199 
3200 struct rtw89_wde_quota {
3201 	u16 hif;
3202 	u16 wcpu;
3203 	u16 pkt_in;
3204 	u16 cpu_io;
3205 };
3206 
3207 struct rtw89_ple_quota {
3208 	u16 cma0_tx;
3209 	u16 cma1_tx;
3210 	u16 c2h;
3211 	u16 h2c;
3212 	u16 wcpu;
3213 	u16 mpdu_proc;
3214 	u16 cma0_dma;
3215 	u16 cma1_dma;
3216 	u16 bb_rpt;
3217 	u16 wd_rel;
3218 	u16 cpu_io;
3219 	u16 tx_rpt;
3220 };
3221 
3222 struct rtw89_dle_mem {
3223 	enum rtw89_qta_mode mode;
3224 	const struct rtw89_dle_size *wde_size;
3225 	const struct rtw89_dle_size *ple_size;
3226 	const struct rtw89_wde_quota *wde_min_qt;
3227 	const struct rtw89_wde_quota *wde_max_qt;
3228 	const struct rtw89_ple_quota *ple_min_qt;
3229 	const struct rtw89_ple_quota *ple_max_qt;
3230 };
3231 
3232 struct rtw89_reg_def {
3233 	u32 addr;
3234 	u32 mask;
3235 };
3236 
3237 struct rtw89_reg2_def {
3238 	u32 addr;
3239 	u32 data;
3240 };
3241 
3242 struct rtw89_reg3_def {
3243 	u32 addr;
3244 	u32 mask;
3245 	u32 data;
3246 };
3247 
3248 struct rtw89_reg5_def {
3249 	u8 flag; /* recognized by parsers */
3250 	u8 path;
3251 	u32 addr;
3252 	u32 mask;
3253 	u32 data;
3254 };
3255 
3256 struct rtw89_phy_table {
3257 	const struct rtw89_reg2_def *regs;
3258 	u32 n_regs;
3259 	enum rtw89_rf_path rf_path;
3260 	void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg,
3261 		       enum rtw89_rf_path rf_path, void *data);
3262 };
3263 
3264 struct rtw89_txpwr_table {
3265 	const void *data;
3266 	u32 size;
3267 	void (*load)(struct rtw89_dev *rtwdev,
3268 		     const struct rtw89_txpwr_table *tbl);
3269 };
3270 
3271 struct rtw89_txpwr_rule_2ghz {
3272 	const s8 (*lmt)[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
3273 		       [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
3274 		       [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
3275 	const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM]
3276 			  [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
3277 };
3278 
3279 struct rtw89_txpwr_rule_5ghz {
3280 	const s8 (*lmt)[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
3281 		       [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
3282 		       [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
3283 	const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM]
3284 			  [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
3285 };
3286 
3287 struct rtw89_txpwr_rule_6ghz {
3288 	const s8 (*lmt)[RTW89_6G_BW_NUM][RTW89_NTX_NUM]
3289 		       [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
3290 		       [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER]
3291 		       [RTW89_6G_CH_NUM];
3292 	const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM]
3293 			  [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER]
3294 			  [RTW89_6G_CH_NUM];
3295 };
3296 
3297 struct rtw89_rfe_parms {
3298 	struct rtw89_txpwr_rule_2ghz rule_2ghz;
3299 	struct rtw89_txpwr_rule_5ghz rule_5ghz;
3300 	struct rtw89_txpwr_rule_6ghz rule_6ghz;
3301 };
3302 
3303 struct rtw89_rfe_parms_conf {
3304 	const struct rtw89_rfe_parms *rfe_parms;
3305 	u8 rfe_type;
3306 };
3307 
3308 struct rtw89_page_regs {
3309 	u32 hci_fc_ctrl;
3310 	u32 ch_page_ctrl;
3311 	u32 ach_page_ctrl;
3312 	u32 ach_page_info;
3313 	u32 pub_page_info3;
3314 	u32 pub_page_ctrl1;
3315 	u32 pub_page_ctrl2;
3316 	u32 pub_page_info1;
3317 	u32 pub_page_info2;
3318 	u32 wp_page_ctrl1;
3319 	u32 wp_page_ctrl2;
3320 	u32 wp_page_info1;
3321 };
3322 
3323 struct rtw89_imr_info {
3324 	u32 wdrls_imr_set;
3325 	u32 wsec_imr_reg;
3326 	u32 wsec_imr_set;
3327 	u32 mpdu_tx_imr_set;
3328 	u32 mpdu_rx_imr_set;
3329 	u32 sta_sch_imr_set;
3330 	u32 txpktctl_imr_b0_reg;
3331 	u32 txpktctl_imr_b0_clr;
3332 	u32 txpktctl_imr_b0_set;
3333 	u32 txpktctl_imr_b1_reg;
3334 	u32 txpktctl_imr_b1_clr;
3335 	u32 txpktctl_imr_b1_set;
3336 	u32 wde_imr_clr;
3337 	u32 wde_imr_set;
3338 	u32 ple_imr_clr;
3339 	u32 ple_imr_set;
3340 	u32 host_disp_imr_clr;
3341 	u32 host_disp_imr_set;
3342 	u32 cpu_disp_imr_clr;
3343 	u32 cpu_disp_imr_set;
3344 	u32 other_disp_imr_clr;
3345 	u32 other_disp_imr_set;
3346 	u32 bbrpt_com_err_imr_reg;
3347 	u32 bbrpt_chinfo_err_imr_reg;
3348 	u32 bbrpt_err_imr_set;
3349 	u32 bbrpt_dfs_err_imr_reg;
3350 	u32 ptcl_imr_clr;
3351 	u32 ptcl_imr_set;
3352 	u32 cdma_imr_0_reg;
3353 	u32 cdma_imr_0_clr;
3354 	u32 cdma_imr_0_set;
3355 	u32 cdma_imr_1_reg;
3356 	u32 cdma_imr_1_clr;
3357 	u32 cdma_imr_1_set;
3358 	u32 phy_intf_imr_reg;
3359 	u32 phy_intf_imr_clr;
3360 	u32 phy_intf_imr_set;
3361 	u32 rmac_imr_reg;
3362 	u32 rmac_imr_clr;
3363 	u32 rmac_imr_set;
3364 	u32 tmac_imr_reg;
3365 	u32 tmac_imr_clr;
3366 	u32 tmac_imr_set;
3367 };
3368 
3369 struct rtw89_xtal_info {
3370 	u32 xcap_reg;
3371 	u32 sc_xo_mask;
3372 	u32 sc_xi_mask;
3373 };
3374 
3375 struct rtw89_rrsr_cfgs {
3376 	struct rtw89_reg3_def ref_rate;
3377 	struct rtw89_reg3_def rsc;
3378 };
3379 
3380 struct rtw89_dig_regs {
3381 	u32 seg0_pd_reg;
3382 	u32 pd_lower_bound_mask;
3383 	u32 pd_spatial_reuse_en;
3384 	u32 bmode_pd_reg;
3385 	u32 bmode_cca_rssi_limit_en;
3386 	u32 bmode_pd_lower_bound_reg;
3387 	u32 bmode_rssi_nocca_low_th_mask;
3388 	struct rtw89_reg_def p0_lna_init;
3389 	struct rtw89_reg_def p1_lna_init;
3390 	struct rtw89_reg_def p0_tia_init;
3391 	struct rtw89_reg_def p1_tia_init;
3392 	struct rtw89_reg_def p0_rxb_init;
3393 	struct rtw89_reg_def p1_rxb_init;
3394 	struct rtw89_reg_def p0_p20_pagcugc_en;
3395 	struct rtw89_reg_def p0_s20_pagcugc_en;
3396 	struct rtw89_reg_def p1_p20_pagcugc_en;
3397 	struct rtw89_reg_def p1_s20_pagcugc_en;
3398 };
3399 
3400 struct rtw89_phy_ul_tb_info {
3401 	bool dyn_tb_tri_en;
3402 	u8 def_if_bandedge;
3403 };
3404 
3405 struct rtw89_antdiv_stats {
3406 	struct ewma_rssi cck_rssi_avg;
3407 	struct ewma_rssi ofdm_rssi_avg;
3408 	struct ewma_rssi non_legacy_rssi_avg;
3409 	u16 pkt_cnt_cck;
3410 	u16 pkt_cnt_ofdm;
3411 	u16 pkt_cnt_non_legacy;
3412 	u32 evm;
3413 };
3414 
3415 struct rtw89_antdiv_info {
3416 	struct rtw89_antdiv_stats target_stats;
3417 	struct rtw89_antdiv_stats main_stats;
3418 	struct rtw89_antdiv_stats aux_stats;
3419 	u8 training_count;
3420 	u8 rssi_pre;
3421 	bool get_stats;
3422 };
3423 
3424 enum rtw89_chanctx_state {
3425 	RTW89_CHANCTX_STATE_MCC_START,
3426 	RTW89_CHANCTX_STATE_MCC_STOP,
3427 };
3428 
3429 enum rtw89_chanctx_callbacks {
3430 	RTW89_CHANCTX_CALLBACK_PLACEHOLDER,
3431 
3432 	NUM_OF_RTW89_CHANCTX_CALLBACKS,
3433 };
3434 
3435 struct rtw89_chanctx_listener {
3436 	void (*callbacks[NUM_OF_RTW89_CHANCTX_CALLBACKS])
3437 		(struct rtw89_dev *rtwdev, enum rtw89_chanctx_state state);
3438 };
3439 
3440 struct rtw89_chip_info {
3441 	enum rtw89_core_chip_id chip_id;
3442 	enum rtw89_chip_gen chip_gen;
3443 	const struct rtw89_chip_ops *ops;
3444 	const struct rtw89_mac_gen_def *mac_def;
3445 	const struct rtw89_phy_gen_def *phy_def;
3446 	const char *fw_basename;
3447 	u8 fw_format_max;
3448 	bool try_ce_fw;
3449 	u32 needed_fw_elms;
3450 	u32 fifo_size;
3451 	bool small_fifo_size;
3452 	u32 dle_scc_rsvd_size;
3453 	u16 max_amsdu_limit;
3454 	bool dis_2g_40m_ul_ofdma;
3455 	u32 rsvd_ple_ofst;
3456 	const struct rtw89_hfc_param_ini *hfc_param_ini;
3457 	const struct rtw89_dle_mem *dle_mem;
3458 	u8 wde_qempty_acq_num;
3459 	u8 wde_qempty_mgq_sel;
3460 	u32 rf_base_addr[2];
3461 	u8 support_chanctx_num;
3462 	u8 support_bands;
3463 	bool support_bw160;
3464 	bool support_unii4;
3465 	bool support_ul_tb_ctrl;
3466 	bool hw_sec_hdr;
3467 	u8 rf_path_num;
3468 	u8 tx_nss;
3469 	u8 rx_nss;
3470 	u8 acam_num;
3471 	u8 bcam_num;
3472 	u8 scam_num;
3473 	u8 bacam_num;
3474 	u8 bacam_dynamic_num;
3475 	enum rtw89_bacam_ver bacam_ver;
3476 
3477 	u8 sec_ctrl_efuse_size;
3478 	u32 physical_efuse_size;
3479 	u32 logical_efuse_size;
3480 	u32 limit_efuse_size;
3481 	u32 dav_phy_efuse_size;
3482 	u32 dav_log_efuse_size;
3483 	u32 phycap_addr;
3484 	u32 phycap_size;
3485 
3486 	const struct rtw89_pwr_cfg * const *pwr_on_seq;
3487 	const struct rtw89_pwr_cfg * const *pwr_off_seq;
3488 	const struct rtw89_phy_table *bb_table;
3489 	const struct rtw89_phy_table *bb_gain_table;
3490 	const struct rtw89_phy_table *rf_table[RF_PATH_MAX];
3491 	const struct rtw89_phy_table *nctl_table;
3492 	const struct rtw89_rfk_tbl *nctl_post_table;
3493 	const struct rtw89_txpwr_table *byr_table;
3494 	const struct rtw89_phy_dig_gain_table *dig_table;
3495 	const struct rtw89_dig_regs *dig_regs;
3496 	const struct rtw89_phy_tssi_dbw_table *tssi_dbw_table;
3497 
3498 	/* NULL if no rfe-specific, or a null-terminated array by rfe_parms */
3499 	const struct rtw89_rfe_parms_conf *rfe_parms_conf;
3500 	const struct rtw89_rfe_parms *dflt_parms;
3501 	const struct rtw89_chanctx_listener *chanctx_listener;
3502 
3503 	u8 txpwr_factor_rf;
3504 	u8 txpwr_factor_mac;
3505 
3506 	u32 para_ver;
3507 	u32 wlcx_desired;
3508 	u8 btcx_desired;
3509 	u8 scbd;
3510 	u8 mailbox;
3511 
3512 	u8 afh_guard_ch;
3513 	const u8 *wl_rssi_thres;
3514 	const u8 *bt_rssi_thres;
3515 	u8 rssi_tol;
3516 
3517 	u8 mon_reg_num;
3518 	const struct rtw89_btc_fbtc_mreg *mon_reg;
3519 	u8 rf_para_ulink_num;
3520 	const struct rtw89_btc_rf_trx_para *rf_para_ulink;
3521 	u8 rf_para_dlink_num;
3522 	const struct rtw89_btc_rf_trx_para *rf_para_dlink;
3523 	u8 ps_mode_supported;
3524 	u8 low_power_hci_modes;
3525 
3526 	u32 h2c_cctl_func_id;
3527 	u32 hci_func_en_addr;
3528 	u32 h2c_desc_size;
3529 	u32 txwd_body_size;
3530 	u32 h2c_ctrl_reg;
3531 	const u32 *h2c_regs;
3532 	struct rtw89_reg_def h2c_counter_reg;
3533 	u32 c2h_ctrl_reg;
3534 	const u32 *c2h_regs;
3535 	struct rtw89_reg_def c2h_counter_reg;
3536 	const struct rtw89_page_regs *page_regs;
3537 	bool cfo_src_fd;
3538 	bool cfo_hw_comp;
3539 	const struct rtw89_reg_def *dcfo_comp;
3540 	u8 dcfo_comp_sft;
3541 	const struct rtw89_imr_info *imr_info;
3542 	const struct rtw89_rrsr_cfgs *rrsr_cfgs;
3543 	u32 bss_clr_map_reg;
3544 	u32 dma_ch_mask;
3545 	u32 edcca_lvl_reg;
3546 	const struct wiphy_wowlan_support *wowlan_stub;
3547 	const struct rtw89_xtal_info *xtal_info;
3548 };
3549 
3550 union rtw89_bus_info {
3551 	const struct rtw89_pci_info *pci;
3552 };
3553 
3554 struct rtw89_driver_info {
3555 	const struct rtw89_chip_info *chip;
3556 	union rtw89_bus_info bus;
3557 };
3558 
3559 enum rtw89_hcifc_mode {
3560 	RTW89_HCIFC_POH = 0,
3561 	RTW89_HCIFC_STF = 1,
3562 	RTW89_HCIFC_SDIO = 2,
3563 
3564 	/* keep last */
3565 	RTW89_HCIFC_MODE_INVALID,
3566 };
3567 
3568 struct rtw89_dle_info {
3569 	enum rtw89_qta_mode qta_mode;
3570 	u16 ple_pg_size;
3571 	u16 c0_rx_qta;
3572 	u16 c1_rx_qta;
3573 };
3574 
3575 enum rtw89_host_rpr_mode {
3576 	RTW89_RPR_MODE_POH = 0,
3577 	RTW89_RPR_MODE_STF
3578 };
3579 
3580 #define RTW89_COMPLETION_BUF_SIZE 24
3581 #define RTW89_WAIT_COND_IDLE UINT_MAX
3582 
3583 struct rtw89_completion_data {
3584 	bool err;
3585 	u8 buf[RTW89_COMPLETION_BUF_SIZE];
3586 };
3587 
3588 struct rtw89_wait_info {
3589 	atomic_t cond;
3590 	struct completion completion;
3591 	struct rtw89_completion_data data;
3592 };
3593 
3594 #define RTW89_WAIT_FOR_COND_TIMEOUT msecs_to_jiffies(100)
3595 
rtw89_init_wait(struct rtw89_wait_info * wait)3596 static inline void rtw89_init_wait(struct rtw89_wait_info *wait)
3597 {
3598 	init_completion(&wait->completion);
3599 	atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE);
3600 }
3601 
3602 struct rtw89_mac_info {
3603 	struct rtw89_dle_info dle_info;
3604 	struct rtw89_hfc_param hfc_param;
3605 	enum rtw89_qta_mode qta_mode;
3606 	u8 rpwm_seq_num;
3607 	u8 cpwm_seq_num;
3608 
3609 	/* see RTW89_FW_OFLD_WAIT_COND series for wait condition */
3610 	struct rtw89_wait_info fw_ofld_wait;
3611 };
3612 
3613 enum rtw89_fw_type {
3614 	RTW89_FW_NORMAL = 1,
3615 	RTW89_FW_WOWLAN = 3,
3616 	RTW89_FW_NORMAL_CE = 5,
3617 	RTW89_FW_BBMCU0 = 64,
3618 	RTW89_FW_BBMCU1 = 65,
3619 	RTW89_FW_LOGFMT = 255,
3620 };
3621 
3622 enum rtw89_fw_feature {
3623 	RTW89_FW_FEATURE_OLD_HT_RA_FORMAT,
3624 	RTW89_FW_FEATURE_SCAN_OFFLOAD,
3625 	RTW89_FW_FEATURE_TX_WAKE,
3626 	RTW89_FW_FEATURE_CRASH_TRIGGER,
3627 	RTW89_FW_FEATURE_NO_PACKET_DROP,
3628 	RTW89_FW_FEATURE_NO_DEEP_PS,
3629 	RTW89_FW_FEATURE_NO_LPS_PG,
3630 	RTW89_FW_FEATURE_BEACON_FILTER,
3631 };
3632 
3633 struct rtw89_fw_suit {
3634 	enum rtw89_fw_type type;
3635 	const u8 *data;
3636 	u32 size;
3637 	u8 major_ver;
3638 	u8 minor_ver;
3639 	u8 sub_ver;
3640 	u8 sub_idex;
3641 	u16 build_year;
3642 	u16 build_mon;
3643 	u16 build_date;
3644 	u16 build_hour;
3645 	u16 build_min;
3646 	u8 cmd_ver;
3647 	u8 hdr_ver;
3648 	u32 commitid;
3649 };
3650 
3651 #define RTW89_FW_VER_CODE(major, minor, sub, idx)	\
3652 	(((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx))
3653 #define RTW89_FW_SUIT_VER_CODE(s)	\
3654 	RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex)
3655 
3656 #define RTW89_MFW_HDR_VER_CODE(mfw_hdr)		\
3657 	RTW89_FW_VER_CODE((mfw_hdr)->ver.major,	\
3658 			  (mfw_hdr)->ver.minor,	\
3659 			  (mfw_hdr)->ver.sub,	\
3660 			  (mfw_hdr)->ver.idx)
3661 
3662 #define RTW89_FW_HDR_VER_CODE(fw_hdr)				\
3663 	RTW89_FW_VER_CODE(le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MAJOR_VERSION),	\
3664 			  le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MINOR_VERSION),	\
3665 			  le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBVERSION),	\
3666 			  le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBINDEX))
3667 
3668 struct rtw89_fw_req_info {
3669 	const struct firmware *firmware;
3670 	struct completion completion;
3671 };
3672 
3673 struct rtw89_fw_log {
3674 	struct rtw89_fw_suit suit;
3675 	bool enable;
3676 	u32 last_fmt_id;
3677 	u32 fmt_count;
3678 	const __le32 *fmt_ids;
3679 	const char *(*fmts)[];
3680 };
3681 
3682 struct rtw89_fw_elm_info {
3683 	struct rtw89_phy_table *bb_tbl;
3684 	struct rtw89_phy_table *bb_gain;
3685 	struct rtw89_phy_table *rf_radio[RF_PATH_MAX];
3686 	struct rtw89_phy_table *rf_nctl;
3687 };
3688 
3689 struct rtw89_fw_info {
3690 	struct rtw89_fw_req_info req;
3691 	int fw_format;
3692 	u8 h2c_seq;
3693 	u8 rec_seq;
3694 	u8 h2c_counter;
3695 	u8 c2h_counter;
3696 	struct rtw89_fw_suit normal;
3697 	struct rtw89_fw_suit wowlan;
3698 	struct rtw89_fw_suit bbmcu0;
3699 	struct rtw89_fw_suit bbmcu1;
3700 	struct rtw89_fw_log log;
3701 	u32 feature_map;
3702 	struct rtw89_fw_elm_info elm_info;
3703 };
3704 
3705 #define RTW89_CHK_FW_FEATURE(_feat, _fw) \
3706 	(!!((_fw)->feature_map & BIT(RTW89_FW_FEATURE_ ## _feat)))
3707 
3708 #define RTW89_SET_FW_FEATURE(_fw_feature, _fw) \
3709 	((_fw)->feature_map |= BIT(_fw_feature))
3710 
3711 struct rtw89_cam_info {
3712 	DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM);
3713 	DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM);
3714 	DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM);
3715 	DECLARE_BITMAP(ba_cam_map, RTW89_MAX_BA_CAM_NUM);
3716 	struct rtw89_ba_cam_entry ba_cam_entry[RTW89_MAX_BA_CAM_NUM];
3717 };
3718 
3719 enum rtw89_sar_sources {
3720 	RTW89_SAR_SOURCE_NONE,
3721 	RTW89_SAR_SOURCE_COMMON,
3722 
3723 	RTW89_SAR_SOURCE_NR,
3724 };
3725 
3726 enum rtw89_sar_subband {
3727 	RTW89_SAR_2GHZ_SUBBAND,
3728 	RTW89_SAR_5GHZ_SUBBAND_1_2, /* U-NII-1 and U-NII-2 */
3729 	RTW89_SAR_5GHZ_SUBBAND_2_E, /* U-NII-2-Extended */
3730 	RTW89_SAR_5GHZ_SUBBAND_3,   /* U-NII-3 */
3731 	RTW89_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */
3732 	RTW89_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */
3733 	RTW89_SAR_6GHZ_SUBBAND_6,   /* U-NII-6 */
3734 	RTW89_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */
3735 	RTW89_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */
3736 	RTW89_SAR_6GHZ_SUBBAND_8,   /* U-NII-8 */
3737 
3738 	RTW89_SAR_SUBBAND_NR,
3739 };
3740 
3741 struct rtw89_sar_cfg_common {
3742 	bool set[RTW89_SAR_SUBBAND_NR];
3743 	s32 cfg[RTW89_SAR_SUBBAND_NR];
3744 };
3745 
3746 struct rtw89_sar_info {
3747 	/* used to decide how to acces SAR cfg union */
3748 	enum rtw89_sar_sources src;
3749 
3750 	/* reserved for different knids of SAR cfg struct.
3751 	 * supposed that a single cfg struct cannot handle various SAR sources.
3752 	 */
3753 	union {
3754 		struct rtw89_sar_cfg_common cfg_common;
3755 	};
3756 };
3757 
3758 enum rtw89_tas_state {
3759 	RTW89_TAS_STATE_DPR_OFF,
3760 	RTW89_TAS_STATE_DPR_ON,
3761 	RTW89_TAS_STATE_DPR_FORBID,
3762 };
3763 
3764 #define RTW89_TAS_MAX_WINDOW 50
3765 struct rtw89_tas_info {
3766 	s16 txpwr_history[RTW89_TAS_MAX_WINDOW];
3767 	s32 total_txpwr;
3768 	u8 cur_idx;
3769 	s8 dpr_gap;
3770 	s8 delta;
3771 	enum rtw89_tas_state state;
3772 	bool enable;
3773 };
3774 
3775 struct rtw89_chanctx_cfg {
3776 	enum rtw89_sub_entity_idx idx;
3777 };
3778 
3779 enum rtw89_entity_mode {
3780 	RTW89_ENTITY_MODE_SCC,
3781 	RTW89_ENTITY_MODE_MCC_PREPARE,
3782 	RTW89_ENTITY_MODE_MCC,
3783 
3784 	NUM_OF_RTW89_ENTITY_MODE,
3785 	RTW89_ENTITY_MODE_INVALID = NUM_OF_RTW89_ENTITY_MODE,
3786 };
3787 
3788 struct rtw89_sub_entity {
3789 	struct cfg80211_chan_def chandef;
3790 	struct rtw89_chan chan;
3791 	struct rtw89_chan_rcd rcd;
3792 	struct rtw89_chanctx_cfg *cfg;
3793 };
3794 
3795 struct rtw89_hal {
3796 	u32 rx_fltr;
3797 	u8 cv;
3798 	u8 acv;
3799 	u32 antenna_tx;
3800 	u32 antenna_rx;
3801 	u8 tx_nss;
3802 	u8 rx_nss;
3803 	bool tx_path_diversity;
3804 	bool ant_diversity;
3805 	bool ant_diversity_fixed;
3806 	bool support_cckpd;
3807 	bool support_igi;
3808 	atomic_t roc_entity_idx;
3809 
3810 	DECLARE_BITMAP(entity_map, NUM_OF_RTW89_SUB_ENTITY);
3811 	struct rtw89_sub_entity sub[NUM_OF_RTW89_SUB_ENTITY];
3812 	struct cfg80211_chan_def roc_chandef;
3813 
3814 	bool entity_active;
3815 	enum rtw89_entity_mode entity_mode;
3816 
3817 	u32 edcca_bak;
3818 };
3819 
3820 #define RTW89_MAX_MAC_ID_NUM 128
3821 #define RTW89_MAX_PKT_OFLD_NUM 255
3822 
3823 enum rtw89_flags {
3824 	RTW89_FLAG_POWERON,
3825 	RTW89_FLAG_FW_RDY,
3826 	RTW89_FLAG_RUNNING,
3827 	RTW89_FLAG_BFEE_MON,
3828 	RTW89_FLAG_BFEE_EN,
3829 	RTW89_FLAG_BFEE_TIMER_KEEP,
3830 	RTW89_FLAG_NAPI_RUNNING,
3831 	RTW89_FLAG_LEISURE_PS,
3832 	RTW89_FLAG_LOW_POWER_MODE,
3833 	RTW89_FLAG_INACTIVE_PS,
3834 	RTW89_FLAG_CRASH_SIMULATING,
3835 	RTW89_FLAG_SER_HANDLING,
3836 	RTW89_FLAG_WOWLAN,
3837 	RTW89_FLAG_FORBIDDEN_TRACK_WROK,
3838 	RTW89_FLAG_CHANGING_INTERFACE,
3839 
3840 	NUM_OF_RTW89_FLAGS,
3841 };
3842 
3843 enum rtw89_pkt_drop_sel {
3844 	RTW89_PKT_DROP_SEL_MACID_BE_ONCE,
3845 	RTW89_PKT_DROP_SEL_MACID_BK_ONCE,
3846 	RTW89_PKT_DROP_SEL_MACID_VI_ONCE,
3847 	RTW89_PKT_DROP_SEL_MACID_VO_ONCE,
3848 	RTW89_PKT_DROP_SEL_MACID_ALL,
3849 	RTW89_PKT_DROP_SEL_MG0_ONCE,
3850 	RTW89_PKT_DROP_SEL_HIQ_ONCE,
3851 	RTW89_PKT_DROP_SEL_HIQ_PORT,
3852 	RTW89_PKT_DROP_SEL_HIQ_MBSSID,
3853 	RTW89_PKT_DROP_SEL_BAND,
3854 	RTW89_PKT_DROP_SEL_BAND_ONCE,
3855 	RTW89_PKT_DROP_SEL_REL_MACID,
3856 	RTW89_PKT_DROP_SEL_REL_HIQ_PORT,
3857 	RTW89_PKT_DROP_SEL_REL_HIQ_MBSSID,
3858 };
3859 
3860 struct rtw89_pkt_drop_params {
3861 	enum rtw89_pkt_drop_sel sel;
3862 	enum rtw89_mac_idx mac_band;
3863 	u8 macid;
3864 	u8 port;
3865 	u8 mbssid;
3866 	bool tf_trs;
3867 	u32 macid_band_sel[4];
3868 };
3869 
3870 struct rtw89_pkt_stat {
3871 	u16 beacon_nr;
3872 	u32 rx_rate_cnt[RTW89_HW_RATE_NR];
3873 };
3874 
3875 DECLARE_EWMA(thermal, 4, 4);
3876 
3877 struct rtw89_phy_stat {
3878 	struct ewma_thermal avg_thermal[RF_PATH_MAX];
3879 	struct rtw89_pkt_stat cur_pkt_stat;
3880 	struct rtw89_pkt_stat last_pkt_stat;
3881 };
3882 
3883 #define RTW89_DACK_PATH_NR 2
3884 #define RTW89_DACK_IDX_NR 2
3885 #define RTW89_DACK_MSBK_NR 16
3886 struct rtw89_dack_info {
3887 	bool dack_done;
3888 	u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR];
3889 	u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR];
3890 	u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR];
3891 	u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR];
3892 	u32 dack_cnt;
3893 	bool addck_timeout[RTW89_DACK_PATH_NR];
3894 	bool dadck_timeout[RTW89_DACK_PATH_NR];
3895 	bool msbk_timeout[RTW89_DACK_PATH_NR];
3896 };
3897 
3898 #define RTW89_IQK_CHS_NR 2
3899 #define RTW89_IQK_PATH_NR 4
3900 
3901 struct rtw89_rfk_mcc_info {
3902 	u8 ch[RTW89_IQK_CHS_NR];
3903 	u8 band[RTW89_IQK_CHS_NR];
3904 	u8 table_idx;
3905 };
3906 
3907 struct rtw89_lck_info {
3908 	u8 thermal[RF_PATH_MAX];
3909 };
3910 
3911 struct rtw89_rx_dck_info {
3912 	u8 thermal[RF_PATH_MAX];
3913 };
3914 
3915 struct rtw89_iqk_info {
3916 	bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
3917 	bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
3918 	bool lok_fail[RTW89_IQK_PATH_NR];
3919 	bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
3920 	bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
3921 	u32 iqk_fail_cnt;
3922 	bool is_iqk_init;
3923 	u32 iqk_channel[RTW89_IQK_CHS_NR];
3924 	u8 iqk_band[RTW89_IQK_PATH_NR];
3925 	u8 iqk_ch[RTW89_IQK_PATH_NR];
3926 	u8 iqk_bw[RTW89_IQK_PATH_NR];
3927 	u8 iqk_times;
3928 	u8 version;
3929 	u32 nb_txcfir[RTW89_IQK_PATH_NR];
3930 	u32 nb_rxcfir[RTW89_IQK_PATH_NR];
3931 	u32 bp_txkresult[RTW89_IQK_PATH_NR];
3932 	u32 bp_rxkresult[RTW89_IQK_PATH_NR];
3933 	u32 bp_iqkenable[RTW89_IQK_PATH_NR];
3934 	bool is_wb_txiqk[RTW89_IQK_PATH_NR];
3935 	bool is_wb_rxiqk[RTW89_IQK_PATH_NR];
3936 	bool is_nbiqk;
3937 	bool iqk_fft_en;
3938 	bool iqk_xym_en;
3939 	bool iqk_sram_en;
3940 	bool iqk_cfir_en;
3941 	u32 syn1to2;
3942 	u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
3943 	u8 iqk_table_idx[RTW89_IQK_PATH_NR];
3944 	u32 lok_idac[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
3945 	u32 lok_vbuf[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
3946 };
3947 
3948 #define RTW89_DPK_RF_PATH 2
3949 #define RTW89_DPK_AVG_THERMAL_NUM 8
3950 #define RTW89_DPK_BKUP_NUM 2
3951 struct rtw89_dpk_bkup_para {
3952 	enum rtw89_band band;
3953 	enum rtw89_bandwidth bw;
3954 	u8 ch;
3955 	bool path_ok;
3956 	u8 mdpd_en;
3957 	u8 txagc_dpk;
3958 	u8 ther_dpk;
3959 	u8 gs;
3960 	u16 pwsf;
3961 };
3962 
3963 struct rtw89_dpk_info {
3964 	bool is_dpk_enable;
3965 	bool is_dpk_reload_en;
3966 	u8 dpk_gs[RTW89_PHY_MAX];
3967 	u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
3968 	u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
3969 	u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
3970 	u8 corr_idx[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
3971 	u8 cur_idx[RTW89_DPK_RF_PATH];
3972 	u8 cur_k_set;
3973 	struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
3974 };
3975 
3976 struct rtw89_fem_info {
3977 	bool elna_2g;
3978 	bool elna_5g;
3979 	bool epa_2g;
3980 	bool epa_5g;
3981 	bool epa_6g;
3982 };
3983 
3984 struct rtw89_phy_ch_info {
3985 	u8 rssi_min;
3986 	u16 rssi_min_macid;
3987 	u8 pre_rssi_min;
3988 	u8 rssi_max;
3989 	u16 rssi_max_macid;
3990 	u8 rxsc_160;
3991 	u8 rxsc_80;
3992 	u8 rxsc_40;
3993 	u8 rxsc_20;
3994 	u8 rxsc_l;
3995 	u8 is_noisy;
3996 };
3997 
3998 struct rtw89_agc_gaincode_set {
3999 	u8 lna_idx;
4000 	u8 tia_idx;
4001 	u8 rxb_idx;
4002 };
4003 
4004 #define IGI_RSSI_TH_NUM 5
4005 #define FA_TH_NUM 4
4006 #define LNA_GAIN_NUM 7
4007 #define TIA_GAIN_NUM 2
4008 struct rtw89_dig_info {
4009 	struct rtw89_agc_gaincode_set cur_gaincode;
4010 	bool force_gaincode_idx_en;
4011 	struct rtw89_agc_gaincode_set force_gaincode;
4012 	u8 igi_rssi_th[IGI_RSSI_TH_NUM];
4013 	u16 fa_th[FA_TH_NUM];
4014 	u8 igi_rssi;
4015 	u8 igi_fa_rssi;
4016 	u8 fa_rssi_ofst;
4017 	u8 dyn_igi_max;
4018 	u8 dyn_igi_min;
4019 	bool dyn_pd_th_en;
4020 	u8 dyn_pd_th_max;
4021 	u8 pd_low_th_ofst;
4022 	u8 ib_pbk;
4023 	s8 ib_pkpwr;
4024 	s8 lna_gain_a[LNA_GAIN_NUM];
4025 	s8 lna_gain_g[LNA_GAIN_NUM];
4026 	s8 *lna_gain;
4027 	s8 tia_gain_a[TIA_GAIN_NUM];
4028 	s8 tia_gain_g[TIA_GAIN_NUM];
4029 	s8 *tia_gain;
4030 	bool is_linked_pre;
4031 	bool bypass_dig;
4032 };
4033 
4034 enum rtw89_multi_cfo_mode {
4035 	RTW89_PKT_BASED_AVG_MODE = 0,
4036 	RTW89_ENTRY_BASED_AVG_MODE = 1,
4037 	RTW89_TP_BASED_AVG_MODE = 2,
4038 };
4039 
4040 enum rtw89_phy_cfo_status {
4041 	RTW89_PHY_DCFO_STATE_NORMAL = 0,
4042 	RTW89_PHY_DCFO_STATE_ENHANCE = 1,
4043 	RTW89_PHY_DCFO_STATE_HOLD = 2,
4044 	RTW89_PHY_DCFO_STATE_MAX
4045 };
4046 
4047 enum rtw89_phy_cfo_ul_ofdma_acc_mode {
4048 	RTW89_CFO_UL_OFDMA_ACC_DISABLE = 0,
4049 	RTW89_CFO_UL_OFDMA_ACC_ENABLE = 1
4050 };
4051 
4052 struct rtw89_cfo_tracking_info {
4053 	u16 cfo_timer_ms;
4054 	bool cfo_trig_by_timer_en;
4055 	enum rtw89_phy_cfo_status phy_cfo_status;
4056 	enum rtw89_phy_cfo_ul_ofdma_acc_mode cfo_ul_ofdma_acc_mode;
4057 	u8 phy_cfo_trk_cnt;
4058 	bool is_adjust;
4059 	enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode;
4060 	bool apply_compensation;
4061 	u8 crystal_cap;
4062 	u8 crystal_cap_default;
4063 	u8 def_x_cap;
4064 	s8 x_cap_ofst;
4065 	u32 sta_cfo_tolerance;
4066 	s32 cfo_tail[CFO_TRACK_MAX_USER];
4067 	u16 cfo_cnt[CFO_TRACK_MAX_USER];
4068 	s32 cfo_avg_pre;
4069 	s32 cfo_avg[CFO_TRACK_MAX_USER];
4070 	s32 pre_cfo_avg[CFO_TRACK_MAX_USER];
4071 	s32 dcfo_avg;
4072 	s32 dcfo_avg_pre;
4073 	u32 packet_count;
4074 	u32 packet_count_pre;
4075 	s32 residual_cfo_acc;
4076 	u8 phy_cfotrk_state;
4077 	u8 phy_cfotrk_cnt;
4078 	bool divergence_lock_en;
4079 	u8 x_cap_lb;
4080 	u8 x_cap_ub;
4081 	u8 lock_cnt;
4082 };
4083 
4084 enum rtw89_tssi_alimk_band {
4085 	TSSI_ALIMK_2G = 0,
4086 	TSSI_ALIMK_5GL,
4087 	TSSI_ALIMK_5GM,
4088 	TSSI_ALIMK_5GH,
4089 	TSSI_ALIMK_MAX
4090 };
4091 
4092 /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */
4093 #define TSSI_TRIM_CH_GROUP_NUM 8
4094 #define TSSI_TRIM_CH_GROUP_NUM_6G 16
4095 
4096 #define TSSI_CCK_CH_GROUP_NUM 6
4097 #define TSSI_MCS_2G_CH_GROUP_NUM 5
4098 #define TSSI_MCS_5G_CH_GROUP_NUM 14
4099 #define TSSI_MCS_6G_CH_GROUP_NUM 32
4100 #define TSSI_MCS_CH_GROUP_NUM \
4101 	(TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM)
4102 #define TSSI_MAX_CH_NUM 67
4103 #define TSSI_ALIMK_VALUE_NUM 8
4104 
4105 struct rtw89_tssi_info {
4106 	u8 thermal[RF_PATH_MAX];
4107 	s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM];
4108 	s8 tssi_trim_6g[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM_6G];
4109 	s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM];
4110 	s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM];
4111 	s8 tssi_6g_mcs[RF_PATH_MAX][TSSI_MCS_6G_CH_GROUP_NUM];
4112 	s8 extra_ofst[RF_PATH_MAX];
4113 	bool tssi_tracking_check[RF_PATH_MAX];
4114 	u8 default_txagc_offset[RF_PATH_MAX];
4115 	u32 base_thermal[RF_PATH_MAX];
4116 	bool check_backup_aligmk[RF_PATH_MAX][TSSI_MAX_CH_NUM];
4117 	u32 alignment_backup_by_ch[RF_PATH_MAX][TSSI_MAX_CH_NUM][TSSI_ALIMK_VALUE_NUM];
4118 	u32 alignment_value[RF_PATH_MAX][TSSI_ALIMK_MAX][TSSI_ALIMK_VALUE_NUM];
4119 	bool alignment_done[RF_PATH_MAX][TSSI_ALIMK_MAX];
4120 	u32 tssi_alimk_time;
4121 };
4122 
4123 struct rtw89_power_trim_info {
4124 	bool pg_thermal_trim;
4125 	bool pg_pa_bias_trim;
4126 	u8 thermal_trim[RF_PATH_MAX];
4127 	u8 pa_bias_trim[RF_PATH_MAX];
4128 };
4129 
4130 struct rtw89_regd {
4131 	char alpha2[3];
4132 	u8 txpwr_regd[RTW89_BAND_NUM];
4133 };
4134 
4135 struct rtw89_regulatory_info {
4136 	const struct rtw89_regd *regd;
4137 	enum rtw89_reg_6ghz_power reg_6ghz_power;
4138 };
4139 
4140 enum rtw89_ifs_clm_application {
4141 	RTW89_IFS_CLM_INIT = 0,
4142 	RTW89_IFS_CLM_BACKGROUND = 1,
4143 	RTW89_IFS_CLM_ACS = 2,
4144 	RTW89_IFS_CLM_DIG = 3,
4145 	RTW89_IFS_CLM_TDMA_DIG = 4,
4146 	RTW89_IFS_CLM_DBG = 5,
4147 	RTW89_IFS_CLM_DBG_MANUAL = 6
4148 };
4149 
4150 enum rtw89_env_racing_lv {
4151 	RTW89_RAC_RELEASE = 0,
4152 	RTW89_RAC_LV_1 = 1,
4153 	RTW89_RAC_LV_2 = 2,
4154 	RTW89_RAC_LV_3 = 3,
4155 	RTW89_RAC_LV_4 = 4,
4156 	RTW89_RAC_MAX_NUM = 5
4157 };
4158 
4159 struct rtw89_ccx_para_info {
4160 	enum rtw89_env_racing_lv rac_lv;
4161 	u16 mntr_time;
4162 	u8 nhm_manual_th_ofst;
4163 	u8 nhm_manual_th0;
4164 	enum rtw89_ifs_clm_application ifs_clm_app;
4165 	u32 ifs_clm_manual_th_times;
4166 	u32 ifs_clm_manual_th0;
4167 	u8 fahm_manual_th_ofst;
4168 	u8 fahm_manual_th0;
4169 	u8 fahm_numer_opt;
4170 	u8 fahm_denom_opt;
4171 };
4172 
4173 enum rtw89_ccx_edcca_opt_sc_idx {
4174 	RTW89_CCX_EDCCA_SEG0_P0 = 0,
4175 	RTW89_CCX_EDCCA_SEG0_S1 = 1,
4176 	RTW89_CCX_EDCCA_SEG0_S2 = 2,
4177 	RTW89_CCX_EDCCA_SEG0_S3 = 3,
4178 	RTW89_CCX_EDCCA_SEG1_P0 = 4,
4179 	RTW89_CCX_EDCCA_SEG1_S1 = 5,
4180 	RTW89_CCX_EDCCA_SEG1_S2 = 6,
4181 	RTW89_CCX_EDCCA_SEG1_S3 = 7
4182 };
4183 
4184 enum rtw89_ccx_edcca_opt_bw_idx {
4185 	RTW89_CCX_EDCCA_BW20_0 = 0,
4186 	RTW89_CCX_EDCCA_BW20_1 = 1,
4187 	RTW89_CCX_EDCCA_BW20_2 = 2,
4188 	RTW89_CCX_EDCCA_BW20_3 = 3,
4189 	RTW89_CCX_EDCCA_BW20_4 = 4,
4190 	RTW89_CCX_EDCCA_BW20_5 = 5,
4191 	RTW89_CCX_EDCCA_BW20_6 = 6,
4192 	RTW89_CCX_EDCCA_BW20_7 = 7
4193 };
4194 
4195 #define RTW89_NHM_TH_NUM 11
4196 #define RTW89_FAHM_TH_NUM 11
4197 #define RTW89_NHM_RPT_NUM 12
4198 #define RTW89_FAHM_RPT_NUM 12
4199 #define RTW89_IFS_CLM_NUM 4
4200 struct rtw89_env_monitor_info {
4201 	u8 ccx_watchdog_result;
4202 	bool ccx_ongoing;
4203 	u8 ccx_rac_lv;
4204 	bool ccx_manual_ctrl;
4205 	u16 ifs_clm_mntr_time;
4206 	enum rtw89_ifs_clm_application ifs_clm_app;
4207 	u16 ccx_period;
4208 	u8 ccx_unit_idx;
4209 	u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM];
4210 	u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM];
4211 	u16 ifs_clm_tx;
4212 	u16 ifs_clm_edcca_excl_cca;
4213 	u16 ifs_clm_ofdmfa;
4214 	u16 ifs_clm_ofdmcca_excl_fa;
4215 	u16 ifs_clm_cckfa;
4216 	u16 ifs_clm_cckcca_excl_fa;
4217 	u16 ifs_clm_total_ifs;
4218 	u8 ifs_clm_his[RTW89_IFS_CLM_NUM];
4219 	u16 ifs_clm_avg[RTW89_IFS_CLM_NUM];
4220 	u16 ifs_clm_cca[RTW89_IFS_CLM_NUM];
4221 	u8 ifs_clm_tx_ratio;
4222 	u8 ifs_clm_edcca_excl_cca_ratio;
4223 	u8 ifs_clm_cck_fa_ratio;
4224 	u8 ifs_clm_ofdm_fa_ratio;
4225 	u8 ifs_clm_cck_cca_excl_fa_ratio;
4226 	u8 ifs_clm_ofdm_cca_excl_fa_ratio;
4227 	u16 ifs_clm_cck_fa_permil;
4228 	u16 ifs_clm_ofdm_fa_permil;
4229 	u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM];
4230 	u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM];
4231 };
4232 
4233 enum rtw89_ser_rcvy_step {
4234 	RTW89_SER_DRV_STOP_TX,
4235 	RTW89_SER_DRV_STOP_RX,
4236 	RTW89_SER_DRV_STOP_RUN,
4237 	RTW89_SER_HAL_STOP_DMA,
4238 	RTW89_SER_SUPPRESS_LOG,
4239 	RTW89_NUM_OF_SER_FLAGS
4240 };
4241 
4242 struct rtw89_ser {
4243 	u8 state;
4244 	u8 alarm_event;
4245 	bool prehandle_l1;
4246 
4247 	struct work_struct ser_hdl_work;
4248 	struct delayed_work ser_alarm_work;
4249 	const struct state_ent *st_tbl;
4250 	const struct event_ent *ev_tbl;
4251 	struct list_head msg_q;
4252 	spinlock_t msg_q_lock; /* lock when read/write ser msg */
4253 	DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS);
4254 };
4255 
4256 enum rtw89_mac_ax_ps_mode {
4257 	RTW89_MAC_AX_PS_MODE_ACTIVE = 0,
4258 	RTW89_MAC_AX_PS_MODE_LEGACY = 1,
4259 	RTW89_MAC_AX_PS_MODE_WMMPS  = 2,
4260 	RTW89_MAC_AX_PS_MODE_MAX    = 3,
4261 };
4262 
4263 enum rtw89_last_rpwm_mode {
4264 	RTW89_LAST_RPWM_PS        = 0x0,
4265 	RTW89_LAST_RPWM_ACTIVE    = 0x6,
4266 };
4267 
4268 struct rtw89_lps_parm {
4269 	u8 macid;
4270 	u8 psmode; /* enum rtw89_mac_ax_ps_mode */
4271 	u8 lastrpwm; /* enum rtw89_last_rpwm_mode */
4272 };
4273 
4274 struct rtw89_ppdu_sts_info {
4275 	struct sk_buff_head rx_queue[RTW89_PHY_MAX];
4276 	u8 curr_rx_ppdu_cnt[RTW89_PHY_MAX];
4277 };
4278 
4279 struct rtw89_early_h2c {
4280 	struct list_head list;
4281 	u8 *h2c;
4282 	u16 h2c_len;
4283 };
4284 
4285 struct rtw89_hw_scan_info {
4286 	struct ieee80211_vif *scanning_vif;
4287 	struct list_head pkt_list[NUM_NL80211_BANDS];
4288 	struct rtw89_chan op_chan;
4289 	u32 last_chan_idx;
4290 };
4291 
4292 enum rtw89_phy_bb_gain_band {
4293 	RTW89_BB_GAIN_BAND_2G = 0,
4294 	RTW89_BB_GAIN_BAND_5G_L = 1,
4295 	RTW89_BB_GAIN_BAND_5G_M = 2,
4296 	RTW89_BB_GAIN_BAND_5G_H = 3,
4297 	RTW89_BB_GAIN_BAND_6G_L = 4,
4298 	RTW89_BB_GAIN_BAND_6G_M = 5,
4299 	RTW89_BB_GAIN_BAND_6G_H = 6,
4300 	RTW89_BB_GAIN_BAND_6G_UH = 7,
4301 
4302 	RTW89_BB_GAIN_BAND_NR,
4303 };
4304 
4305 enum rtw89_phy_bb_rxsc_num {
4306 	RTW89_BB_RXSC_NUM_40 = 9, /* SC: 0, 1~8 */
4307 	RTW89_BB_RXSC_NUM_80 = 13, /* SC: 0, 1~8, 9~12 */
4308 	RTW89_BB_RXSC_NUM_160 = 15, /* SC: 0, 1~8, 9~12, 13~14 */
4309 };
4310 
4311 struct rtw89_phy_bb_gain_info {
4312 	s8 lna_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM];
4313 	s8 tia_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][TIA_GAIN_NUM];
4314 	s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM];
4315 	s8 lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM];
4316 	s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
4317 			[LNA_GAIN_NUM + 1]; /* TIA0_LNA0~6 + TIA1_LNA6 */
4318 	s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX];
4319 	s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
4320 		      [RTW89_BB_RXSC_NUM_40];
4321 	s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
4322 		      [RTW89_BB_RXSC_NUM_80];
4323 	s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
4324 		       [RTW89_BB_RXSC_NUM_160];
4325 };
4326 
4327 struct rtw89_phy_efuse_gain {
4328 	bool offset_valid;
4329 	bool comp_valid;
4330 	s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */
4331 	s8 offset_base[RTW89_PHY_MAX]; /* S(8, 4) */
4332 	s8 rssi_base[RTW89_PHY_MAX]; /* S(8, 4) */
4333 	s8 comp[RF_PATH_MAX][RTW89_SUBBAND_NR]; /* S(8, 0) */
4334 };
4335 
4336 #define RTW89_MAX_PATTERN_NUM             18
4337 #define RTW89_MAX_PATTERN_MASK_SIZE       4
4338 #define RTW89_MAX_PATTERN_SIZE            128
4339 
4340 struct rtw89_wow_cam_info {
4341 	bool r_w;
4342 	u8 idx;
4343 	u32 mask[RTW89_MAX_PATTERN_MASK_SIZE];
4344 	u16 crc;
4345 	bool negative_pattern_match;
4346 	bool skip_mac_hdr;
4347 	bool uc;
4348 	bool mc;
4349 	bool bc;
4350 	bool valid;
4351 };
4352 
4353 struct rtw89_wow_param {
4354 	struct ieee80211_vif *wow_vif;
4355 	DECLARE_BITMAP(flags, RTW89_WOW_FLAG_NUM);
4356 	struct rtw89_wow_cam_info patterns[RTW89_MAX_PATTERN_NUM];
4357 	u8 pattern_cnt;
4358 };
4359 
4360 struct rtw89_mcc_info {
4361 	struct rtw89_wait_info wait;
4362 };
4363 
4364 struct rtw89_dev {
4365 	struct ieee80211_hw *hw;
4366 	struct device *dev;
4367 	const struct ieee80211_ops *ops;
4368 
4369 	bool dbcc_en;
4370 	struct rtw89_hw_scan_info scan_info;
4371 	const struct rtw89_chip_info *chip;
4372 	const struct rtw89_pci_info *pci_info;
4373 	const struct rtw89_rfe_parms *rfe_parms;
4374 	struct rtw89_hal hal;
4375 	struct rtw89_mcc_info mcc;
4376 	struct rtw89_mac_info mac;
4377 	struct rtw89_fw_info fw;
4378 	struct rtw89_hci_info hci;
4379 	struct rtw89_efuse efuse;
4380 	struct rtw89_traffic_stats stats;
4381 
4382 	/* ensures exclusive access from mac80211 callbacks */
4383 	struct mutex mutex;
4384 	struct list_head rtwvifs_list;
4385 	/* used to protect rf read write */
4386 	struct mutex rf_mutex;
4387 	struct workqueue_struct *txq_wq;
4388 	struct work_struct txq_work;
4389 	struct delayed_work txq_reinvoke_work;
4390 	/* used to protect ba_list and forbid_ba_list */
4391 	spinlock_t ba_lock;
4392 	/* txqs to setup ba session */
4393 	struct list_head ba_list;
4394 	/* txqs to forbid ba session */
4395 	struct list_head forbid_ba_list;
4396 	struct work_struct ba_work;
4397 	/* used to protect rpwm */
4398 	spinlock_t rpwm_lock;
4399 
4400 	struct rtw89_cam_info cam_info;
4401 
4402 	struct sk_buff_head c2h_queue;
4403 	struct work_struct c2h_work;
4404 	struct work_struct ips_work;
4405 	struct work_struct load_firmware_work;
4406 	struct work_struct cancel_6ghz_probe_work;
4407 
4408 	struct list_head early_h2c_list;
4409 
4410 	struct rtw89_ser ser;
4411 
4412 	DECLARE_BITMAP(hw_port, RTW89_PORT_NUM);
4413 	DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM);
4414 	DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS);
4415 	DECLARE_BITMAP(pkt_offload, RTW89_MAX_PKT_OFLD_NUM);
4416 
4417 	struct rtw89_phy_stat phystat;
4418 	struct rtw89_dack_info dack;
4419 	struct rtw89_iqk_info iqk;
4420 	struct rtw89_dpk_info dpk;
4421 	struct rtw89_rfk_mcc_info rfk_mcc;
4422 	struct rtw89_lck_info lck;
4423 	struct rtw89_rx_dck_info rx_dck;
4424 	bool is_tssi_mode[RF_PATH_MAX];
4425 	bool is_bt_iqk_timeout;
4426 
4427 	struct rtw89_fem_info fem;
4428 	struct rtw89_txpwr_byrate byr[RTW89_BAND_NUM];
4429 	struct rtw89_tssi_info tssi;
4430 	struct rtw89_power_trim_info pwr_trim;
4431 
4432 	struct rtw89_cfo_tracking_info cfo_tracking;
4433 	struct rtw89_env_monitor_info env_monitor;
4434 	struct rtw89_dig_info dig;
4435 	struct rtw89_phy_ch_info ch_info;
4436 	struct rtw89_phy_bb_gain_info bb_gain;
4437 	struct rtw89_phy_efuse_gain efuse_gain;
4438 	struct rtw89_phy_ul_tb_info ul_tb_info;
4439 	struct rtw89_antdiv_info antdiv;
4440 
4441 	struct delayed_work track_work;
4442 	struct delayed_work chanctx_work;
4443 	struct delayed_work coex_act1_work;
4444 	struct delayed_work coex_bt_devinfo_work;
4445 	struct delayed_work coex_rfk_chk_work;
4446 	struct delayed_work cfo_track_work;
4447 	struct delayed_work forbid_ba_work;
4448 	struct delayed_work roc_work;
4449 	struct delayed_work antdiv_work;
4450 	struct rtw89_ppdu_sts_info ppdu_sts;
4451 	u8 total_sta_assoc;
4452 	bool scanning;
4453 
4454 	struct rtw89_regulatory_info regulatory;
4455 	struct rtw89_sar_info sar;
4456 	struct rtw89_tas_info tas;
4457 
4458 	struct rtw89_btc btc;
4459 	enum rtw89_ps_mode ps_mode;
4460 	bool lps_enabled;
4461 
4462 	struct rtw89_wow_param wow;
4463 
4464 	/* napi structure */
4465 	struct net_device netdev;
4466 	struct napi_struct napi;
4467 	int napi_budget_countdown;
4468 
4469 	/* HCI related data, keep last */
4470 	u8 priv[] __aligned(sizeof(void *));
4471 };
4472 
rtw89_hci_tx_write(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)4473 static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev,
4474 				     struct rtw89_core_tx_request *tx_req)
4475 {
4476 	return rtwdev->hci.ops->tx_write(rtwdev, tx_req);
4477 }
4478 
rtw89_hci_reset(struct rtw89_dev * rtwdev)4479 static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev)
4480 {
4481 	rtwdev->hci.ops->reset(rtwdev);
4482 }
4483 
rtw89_hci_start(struct rtw89_dev * rtwdev)4484 static inline int rtw89_hci_start(struct rtw89_dev *rtwdev)
4485 {
4486 	return rtwdev->hci.ops->start(rtwdev);
4487 }
4488 
rtw89_hci_stop(struct rtw89_dev * rtwdev)4489 static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev)
4490 {
4491 	rtwdev->hci.ops->stop(rtwdev);
4492 }
4493 
rtw89_hci_deinit(struct rtw89_dev * rtwdev)4494 static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev)
4495 {
4496 	return rtwdev->hci.ops->deinit(rtwdev);
4497 }
4498 
rtw89_hci_pause(struct rtw89_dev * rtwdev,bool pause)4499 static inline void rtw89_hci_pause(struct rtw89_dev *rtwdev, bool pause)
4500 {
4501 	rtwdev->hci.ops->pause(rtwdev, pause);
4502 }
4503 
rtw89_hci_switch_mode(struct rtw89_dev * rtwdev,bool low_power)4504 static inline void rtw89_hci_switch_mode(struct rtw89_dev *rtwdev, bool low_power)
4505 {
4506 	rtwdev->hci.ops->switch_mode(rtwdev, low_power);
4507 }
4508 
rtw89_hci_recalc_int_mit(struct rtw89_dev * rtwdev)4509 static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev)
4510 {
4511 	rtwdev->hci.ops->recalc_int_mit(rtwdev);
4512 }
4513 
rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev * rtwdev,u8 txch)4514 static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch)
4515 {
4516 	return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch);
4517 }
4518 
rtw89_hci_tx_kick_off(struct rtw89_dev * rtwdev,u8 txch)4519 static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch)
4520 {
4521 	return rtwdev->hci.ops->tx_kick_off(rtwdev, txch);
4522 }
4523 
rtw89_hci_flush_queues(struct rtw89_dev * rtwdev,u32 queues,bool drop)4524 static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues,
4525 					  bool drop)
4526 {
4527 	if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags))
4528 		return;
4529 
4530 	if (rtwdev->hci.ops->flush_queues)
4531 		return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop);
4532 }
4533 
rtw89_hci_recovery_start(struct rtw89_dev * rtwdev)4534 static inline void rtw89_hci_recovery_start(struct rtw89_dev *rtwdev)
4535 {
4536 	if (rtwdev->hci.ops->recovery_start)
4537 		rtwdev->hci.ops->recovery_start(rtwdev);
4538 }
4539 
rtw89_hci_recovery_complete(struct rtw89_dev * rtwdev)4540 static inline void rtw89_hci_recovery_complete(struct rtw89_dev *rtwdev)
4541 {
4542 	if (rtwdev->hci.ops->recovery_complete)
4543 		rtwdev->hci.ops->recovery_complete(rtwdev);
4544 }
4545 
rtw89_hci_enable_intr(struct rtw89_dev * rtwdev)4546 static inline void rtw89_hci_enable_intr(struct rtw89_dev *rtwdev)
4547 {
4548 	if (rtwdev->hci.ops->enable_intr)
4549 		rtwdev->hci.ops->enable_intr(rtwdev);
4550 }
4551 
rtw89_hci_disable_intr(struct rtw89_dev * rtwdev)4552 static inline void rtw89_hci_disable_intr(struct rtw89_dev *rtwdev)
4553 {
4554 	if (rtwdev->hci.ops->disable_intr)
4555 		rtwdev->hci.ops->disable_intr(rtwdev);
4556 }
4557 
rtw89_hci_ctrl_txdma_ch(struct rtw89_dev * rtwdev,bool enable)4558 static inline void rtw89_hci_ctrl_txdma_ch(struct rtw89_dev *rtwdev, bool enable)
4559 {
4560 	if (rtwdev->hci.ops->ctrl_txdma_ch)
4561 		rtwdev->hci.ops->ctrl_txdma_ch(rtwdev, enable);
4562 }
4563 
rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev * rtwdev,bool enable)4564 static inline void rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev *rtwdev, bool enable)
4565 {
4566 	if (rtwdev->hci.ops->ctrl_txdma_fw_ch)
4567 		rtwdev->hci.ops->ctrl_txdma_fw_ch(rtwdev, enable);
4568 }
4569 
rtw89_hci_ctrl_trxhci(struct rtw89_dev * rtwdev,bool enable)4570 static inline void rtw89_hci_ctrl_trxhci(struct rtw89_dev *rtwdev, bool enable)
4571 {
4572 	if (rtwdev->hci.ops->ctrl_trxhci)
4573 		rtwdev->hci.ops->ctrl_trxhci(rtwdev, enable);
4574 }
4575 
rtw89_hci_poll_txdma_ch(struct rtw89_dev * rtwdev)4576 static inline int rtw89_hci_poll_txdma_ch(struct rtw89_dev *rtwdev)
4577 {
4578 	int ret = 0;
4579 
4580 	if (rtwdev->hci.ops->poll_txdma_ch)
4581 		ret = rtwdev->hci.ops->poll_txdma_ch(rtwdev);
4582 	return ret;
4583 }
4584 
rtw89_hci_clr_idx_all(struct rtw89_dev * rtwdev)4585 static inline void rtw89_hci_clr_idx_all(struct rtw89_dev *rtwdev)
4586 {
4587 	if (rtwdev->hci.ops->clr_idx_all)
4588 		rtwdev->hci.ops->clr_idx_all(rtwdev);
4589 }
4590 
rtw89_hci_rst_bdram(struct rtw89_dev * rtwdev)4591 static inline int rtw89_hci_rst_bdram(struct rtw89_dev *rtwdev)
4592 {
4593 	int ret = 0;
4594 
4595 	if (rtwdev->hci.ops->rst_bdram)
4596 		ret = rtwdev->hci.ops->rst_bdram(rtwdev);
4597 	return ret;
4598 }
4599 
rtw89_hci_clear(struct rtw89_dev * rtwdev,struct pci_dev * pdev)4600 static inline void rtw89_hci_clear(struct rtw89_dev *rtwdev, struct pci_dev *pdev)
4601 {
4602 	if (rtwdev->hci.ops->clear)
4603 		rtwdev->hci.ops->clear(rtwdev, pdev);
4604 }
4605 
4606 static inline
RTW89_TX_SKB_CB(struct sk_buff * skb)4607 struct rtw89_tx_skb_data *RTW89_TX_SKB_CB(struct sk_buff *skb)
4608 {
4609 	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
4610 
4611 	return (struct rtw89_tx_skb_data *)info->status.status_driver_data;
4612 }
4613 
rtw89_read8(struct rtw89_dev * rtwdev,u32 addr)4614 static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr)
4615 {
4616 	return rtwdev->hci.ops->read8(rtwdev, addr);
4617 }
4618 
rtw89_read16(struct rtw89_dev * rtwdev,u32 addr)4619 static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr)
4620 {
4621 	return rtwdev->hci.ops->read16(rtwdev, addr);
4622 }
4623 
rtw89_read32(struct rtw89_dev * rtwdev,u32 addr)4624 static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr)
4625 {
4626 	return rtwdev->hci.ops->read32(rtwdev, addr);
4627 }
4628 
rtw89_write8(struct rtw89_dev * rtwdev,u32 addr,u8 data)4629 static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data)
4630 {
4631 	rtwdev->hci.ops->write8(rtwdev, addr, data);
4632 }
4633 
rtw89_write16(struct rtw89_dev * rtwdev,u32 addr,u16 data)4634 static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data)
4635 {
4636 	rtwdev->hci.ops->write16(rtwdev, addr, data);
4637 }
4638 
rtw89_write32(struct rtw89_dev * rtwdev,u32 addr,u32 data)4639 static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data)
4640 {
4641 	rtwdev->hci.ops->write32(rtwdev, addr, data);
4642 }
4643 
4644 static inline void
rtw89_write8_set(struct rtw89_dev * rtwdev,u32 addr,u8 bit)4645 rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit)
4646 {
4647 	u8 val;
4648 
4649 	val = rtw89_read8(rtwdev, addr);
4650 	rtw89_write8(rtwdev, addr, val | bit);
4651 }
4652 
4653 static inline void
rtw89_write16_set(struct rtw89_dev * rtwdev,u32 addr,u16 bit)4654 rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit)
4655 {
4656 	u16 val;
4657 
4658 	val = rtw89_read16(rtwdev, addr);
4659 	rtw89_write16(rtwdev, addr, val | bit);
4660 }
4661 
4662 static inline void
rtw89_write32_set(struct rtw89_dev * rtwdev,u32 addr,u32 bit)4663 rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit)
4664 {
4665 	u32 val;
4666 
4667 	val = rtw89_read32(rtwdev, addr);
4668 	rtw89_write32(rtwdev, addr, val | bit);
4669 }
4670 
4671 static inline void
rtw89_write8_clr(struct rtw89_dev * rtwdev,u32 addr,u8 bit)4672 rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit)
4673 {
4674 	u8 val;
4675 
4676 	val = rtw89_read8(rtwdev, addr);
4677 	rtw89_write8(rtwdev, addr, val & ~bit);
4678 }
4679 
4680 static inline void
rtw89_write16_clr(struct rtw89_dev * rtwdev,u32 addr,u16 bit)4681 rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit)
4682 {
4683 	u16 val;
4684 
4685 	val = rtw89_read16(rtwdev, addr);
4686 	rtw89_write16(rtwdev, addr, val & ~bit);
4687 }
4688 
4689 static inline void
rtw89_write32_clr(struct rtw89_dev * rtwdev,u32 addr,u32 bit)4690 rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit)
4691 {
4692 	u32 val;
4693 
4694 	val = rtw89_read32(rtwdev, addr);
4695 	rtw89_write32(rtwdev, addr, val & ~bit);
4696 }
4697 
4698 static inline u32
rtw89_read32_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask)4699 rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask)
4700 {
4701 	u32 shift = __ffs(mask);
4702 	u32 orig;
4703 	u32 ret;
4704 
4705 	orig = rtw89_read32(rtwdev, addr);
4706 	ret = (orig & mask) >> shift;
4707 
4708 	return ret;
4709 }
4710 
4711 static inline u16
rtw89_read16_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask)4712 rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask)
4713 {
4714 	u32 shift = __ffs(mask);
4715 	u32 orig;
4716 	u32 ret;
4717 
4718 	orig = rtw89_read16(rtwdev, addr);
4719 	ret = (orig & mask) >> shift;
4720 
4721 	return ret;
4722 }
4723 
4724 static inline u8
rtw89_read8_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask)4725 rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask)
4726 {
4727 	u32 shift = __ffs(mask);
4728 	u32 orig;
4729 	u32 ret;
4730 
4731 	orig = rtw89_read8(rtwdev, addr);
4732 	ret = (orig & mask) >> shift;
4733 
4734 	return ret;
4735 }
4736 
4737 static inline void
rtw89_write32_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask,u32 data)4738 rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data)
4739 {
4740 	u32 shift = __ffs(mask);
4741 	u32 orig;
4742 	u32 set;
4743 
4744 	WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr);
4745 
4746 	orig = rtw89_read32(rtwdev, addr);
4747 	set = (orig & ~mask) | ((data << shift) & mask);
4748 	rtw89_write32(rtwdev, addr, set);
4749 }
4750 
4751 static inline void
rtw89_write16_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask,u16 data)4752 rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data)
4753 {
4754 	u32 shift;
4755 	u16 orig, set;
4756 
4757 	mask &= 0xffff;
4758 	shift = __ffs(mask);
4759 
4760 	orig = rtw89_read16(rtwdev, addr);
4761 	set = (orig & ~mask) | ((data << shift) & mask);
4762 	rtw89_write16(rtwdev, addr, set);
4763 }
4764 
4765 static inline void
rtw89_write8_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask,u8 data)4766 rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data)
4767 {
4768 	u32 shift;
4769 	u8 orig, set;
4770 
4771 	mask &= 0xff;
4772 	shift = __ffs(mask);
4773 
4774 	orig = rtw89_read8(rtwdev, addr);
4775 	set = (orig & ~mask) | ((data << shift) & mask);
4776 	rtw89_write8(rtwdev, addr, set);
4777 }
4778 
4779 static inline u32
rtw89_read_rf(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask)4780 rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
4781 	      u32 addr, u32 mask)
4782 {
4783 	u32 val;
4784 
4785 	mutex_lock(&rtwdev->rf_mutex);
4786 	val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask);
4787 	mutex_unlock(&rtwdev->rf_mutex);
4788 
4789 	return val;
4790 }
4791 
4792 static inline void
rtw89_write_rf(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask,u32 data)4793 rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
4794 	       u32 addr, u32 mask, u32 data)
4795 {
4796 	mutex_lock(&rtwdev->rf_mutex);
4797 	rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data);
4798 	mutex_unlock(&rtwdev->rf_mutex);
4799 }
4800 
rtw89_txq_to_txq(struct rtw89_txq * rtwtxq)4801 static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq)
4802 {
4803 	void *p = rtwtxq;
4804 
4805 	return container_of(p, struct ieee80211_txq, drv_priv);
4806 }
4807 
rtw89_core_txq_init(struct rtw89_dev * rtwdev,struct ieee80211_txq * txq)4808 static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev,
4809 				       struct ieee80211_txq *txq)
4810 {
4811 	struct rtw89_txq *rtwtxq;
4812 
4813 	if (!txq)
4814 		return;
4815 
4816 	rtwtxq = (struct rtw89_txq *)txq->drv_priv;
4817 	INIT_LIST_HEAD(&rtwtxq->list);
4818 }
4819 
rtwvif_to_vif(struct rtw89_vif * rtwvif)4820 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif)
4821 {
4822 	void *p = rtwvif;
4823 
4824 	return container_of(p, struct ieee80211_vif, drv_priv);
4825 }
4826 
rtwvif_to_vif_safe(struct rtw89_vif * rtwvif)4827 static inline struct ieee80211_vif *rtwvif_to_vif_safe(struct rtw89_vif *rtwvif)
4828 {
4829 	return rtwvif ? rtwvif_to_vif(rtwvif) : NULL;
4830 }
4831 
vif_to_rtwvif_safe(struct ieee80211_vif * vif)4832 static inline struct rtw89_vif *vif_to_rtwvif_safe(struct ieee80211_vif *vif)
4833 {
4834 	return vif ? (struct rtw89_vif *)vif->drv_priv : NULL;
4835 }
4836 
rtwsta_to_sta(struct rtw89_sta * rtwsta)4837 static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta)
4838 {
4839 	void *p = rtwsta;
4840 
4841 	return container_of(p, struct ieee80211_sta, drv_priv);
4842 }
4843 
rtwsta_to_sta_safe(struct rtw89_sta * rtwsta)4844 static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta)
4845 {
4846 	return rtwsta ? rtwsta_to_sta(rtwsta) : NULL;
4847 }
4848 
sta_to_rtwsta_safe(struct ieee80211_sta * sta)4849 static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta)
4850 {
4851 	return sta ? (struct rtw89_sta *)sta->drv_priv : NULL;
4852 }
4853 
rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw)4854 static inline u8 rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw)
4855 {
4856 	if (hw_bw == RTW89_CHANNEL_WIDTH_160)
4857 		return RATE_INFO_BW_160;
4858 	else if (hw_bw == RTW89_CHANNEL_WIDTH_80)
4859 		return RATE_INFO_BW_80;
4860 	else if (hw_bw == RTW89_CHANNEL_WIDTH_40)
4861 		return RATE_INFO_BW_40;
4862 	else
4863 		return RATE_INFO_BW_20;
4864 }
4865 
4866 static inline
rtw89_hw_to_nl80211_band(enum rtw89_band hw_band)4867 enum nl80211_band rtw89_hw_to_nl80211_band(enum rtw89_band hw_band)
4868 {
4869 	switch (hw_band) {
4870 	default:
4871 	case RTW89_BAND_2G:
4872 		return NL80211_BAND_2GHZ;
4873 	case RTW89_BAND_5G:
4874 		return NL80211_BAND_5GHZ;
4875 	case RTW89_BAND_6G:
4876 		return NL80211_BAND_6GHZ;
4877 	}
4878 }
4879 
4880 static inline
rtw89_nl80211_to_hw_band(enum nl80211_band nl_band)4881 enum rtw89_band rtw89_nl80211_to_hw_band(enum nl80211_band nl_band)
4882 {
4883 	switch (nl_band) {
4884 	default:
4885 	case NL80211_BAND_2GHZ:
4886 		return RTW89_BAND_2G;
4887 	case NL80211_BAND_5GHZ:
4888 		return RTW89_BAND_5G;
4889 	case NL80211_BAND_6GHZ:
4890 		return RTW89_BAND_6G;
4891 	}
4892 }
4893 
4894 static inline
nl_to_rtw89_bandwidth(enum nl80211_chan_width width)4895 enum rtw89_bandwidth nl_to_rtw89_bandwidth(enum nl80211_chan_width width)
4896 {
4897 	switch (width) {
4898 	default:
4899 		WARN(1, "Not support bandwidth %d\n", width);
4900 		fallthrough;
4901 	case NL80211_CHAN_WIDTH_20_NOHT:
4902 	case NL80211_CHAN_WIDTH_20:
4903 		return RTW89_CHANNEL_WIDTH_20;
4904 	case NL80211_CHAN_WIDTH_40:
4905 		return RTW89_CHANNEL_WIDTH_40;
4906 	case NL80211_CHAN_WIDTH_80:
4907 		return RTW89_CHANNEL_WIDTH_80;
4908 	case NL80211_CHAN_WIDTH_160:
4909 		return RTW89_CHANNEL_WIDTH_160;
4910 	}
4911 }
4912 
4913 static inline
rtw89_get_addr_cam_of(struct rtw89_vif * rtwvif,struct rtw89_sta * rtwsta)4914 struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif *rtwvif,
4915 						   struct rtw89_sta *rtwsta)
4916 {
4917 	if (rtwsta) {
4918 		struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta);
4919 
4920 		if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE || sta->tdls)
4921 			return &rtwsta->addr_cam;
4922 	}
4923 	return &rtwvif->addr_cam;
4924 }
4925 
4926 static inline
rtw89_get_bssid_cam_of(struct rtw89_vif * rtwvif,struct rtw89_sta * rtwsta)4927 struct rtw89_bssid_cam_entry *rtw89_get_bssid_cam_of(struct rtw89_vif *rtwvif,
4928 						     struct rtw89_sta *rtwsta)
4929 {
4930 	if (rtwsta) {
4931 		struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta);
4932 
4933 		if (sta->tdls)
4934 			return &rtwsta->bssid_cam;
4935 	}
4936 	return &rtwvif->bssid_cam;
4937 }
4938 
4939 static inline
rtw89_chip_set_channel_prepare(struct rtw89_dev * rtwdev,struct rtw89_channel_help_params * p,const struct rtw89_chan * chan,enum rtw89_mac_idx mac_idx,enum rtw89_phy_idx phy_idx)4940 void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev,
4941 				    struct rtw89_channel_help_params *p,
4942 				    const struct rtw89_chan *chan,
4943 				    enum rtw89_mac_idx mac_idx,
4944 				    enum rtw89_phy_idx phy_idx)
4945 {
4946 	rtwdev->chip->ops->set_channel_help(rtwdev, true, p, chan,
4947 					    mac_idx, phy_idx);
4948 }
4949 
4950 static inline
rtw89_chip_set_channel_done(struct rtw89_dev * rtwdev,struct rtw89_channel_help_params * p,const struct rtw89_chan * chan,enum rtw89_mac_idx mac_idx,enum rtw89_phy_idx phy_idx)4951 void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev,
4952 				 struct rtw89_channel_help_params *p,
4953 				 const struct rtw89_chan *chan,
4954 				 enum rtw89_mac_idx mac_idx,
4955 				 enum rtw89_phy_idx phy_idx)
4956 {
4957 	rtwdev->chip->ops->set_channel_help(rtwdev, false, p, chan,
4958 					    mac_idx, phy_idx);
4959 }
4960 
4961 static inline
rtw89_chandef_get(struct rtw89_dev * rtwdev,enum rtw89_sub_entity_idx idx)4962 const struct cfg80211_chan_def *rtw89_chandef_get(struct rtw89_dev *rtwdev,
4963 						  enum rtw89_sub_entity_idx idx)
4964 {
4965 	struct rtw89_hal *hal = &rtwdev->hal;
4966 	enum rtw89_sub_entity_idx roc_idx = atomic_read(&hal->roc_entity_idx);
4967 
4968 	if (roc_idx == idx)
4969 		return &hal->roc_chandef;
4970 
4971 	return &hal->sub[idx].chandef;
4972 }
4973 
4974 static inline
rtw89_chan_get(struct rtw89_dev * rtwdev,enum rtw89_sub_entity_idx idx)4975 const struct rtw89_chan *rtw89_chan_get(struct rtw89_dev *rtwdev,
4976 					enum rtw89_sub_entity_idx idx)
4977 {
4978 	struct rtw89_hal *hal = &rtwdev->hal;
4979 
4980 	return &hal->sub[idx].chan;
4981 }
4982 
4983 static inline
rtw89_chan_rcd_get(struct rtw89_dev * rtwdev,enum rtw89_sub_entity_idx idx)4984 const struct rtw89_chan_rcd *rtw89_chan_rcd_get(struct rtw89_dev *rtwdev,
4985 						enum rtw89_sub_entity_idx idx)
4986 {
4987 	struct rtw89_hal *hal = &rtwdev->hal;
4988 
4989 	return &hal->sub[idx].rcd;
4990 }
4991 
4992 static inline
rtw89_scan_chan_get(struct rtw89_dev * rtwdev)4993 const struct rtw89_chan *rtw89_scan_chan_get(struct rtw89_dev *rtwdev)
4994 {
4995 	struct ieee80211_vif *vif = rtwdev->scan_info.scanning_vif;
4996 	struct rtw89_vif *rtwvif = vif_to_rtwvif_safe(vif);
4997 
4998 	if (rtwvif)
4999 		return rtw89_chan_get(rtwdev, rtwvif->sub_entity_idx);
5000 	else
5001 		return rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
5002 }
5003 
rtw89_chip_fem_setup(struct rtw89_dev * rtwdev)5004 static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev)
5005 {
5006 	const struct rtw89_chip_info *chip = rtwdev->chip;
5007 
5008 	if (chip->ops->fem_setup)
5009 		chip->ops->fem_setup(rtwdev);
5010 }
5011 
rtw89_chip_rfe_gpio(struct rtw89_dev * rtwdev)5012 static inline void rtw89_chip_rfe_gpio(struct rtw89_dev *rtwdev)
5013 {
5014 	const struct rtw89_chip_info *chip = rtwdev->chip;
5015 
5016 	if (chip->ops->rfe_gpio)
5017 		chip->ops->rfe_gpio(rtwdev);
5018 }
5019 
rtw89_chip_bb_sethw(struct rtw89_dev * rtwdev)5020 static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev)
5021 {
5022 	const struct rtw89_chip_info *chip = rtwdev->chip;
5023 
5024 	if (chip->ops->bb_sethw)
5025 		chip->ops->bb_sethw(rtwdev);
5026 }
5027 
rtw89_chip_rfk_init(struct rtw89_dev * rtwdev)5028 static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev)
5029 {
5030 	const struct rtw89_chip_info *chip = rtwdev->chip;
5031 
5032 	if (chip->ops->rfk_init)
5033 		chip->ops->rfk_init(rtwdev);
5034 }
5035 
rtw89_chip_rfk_channel(struct rtw89_dev * rtwdev)5036 static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev)
5037 {
5038 	const struct rtw89_chip_info *chip = rtwdev->chip;
5039 
5040 	if (chip->ops->rfk_channel)
5041 		chip->ops->rfk_channel(rtwdev);
5042 }
5043 
rtw89_chip_rfk_band_changed(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)5044 static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev,
5045 					       enum rtw89_phy_idx phy_idx)
5046 {
5047 	const struct rtw89_chip_info *chip = rtwdev->chip;
5048 
5049 	if (chip->ops->rfk_band_changed)
5050 		chip->ops->rfk_band_changed(rtwdev, phy_idx);
5051 }
5052 
rtw89_chip_rfk_scan(struct rtw89_dev * rtwdev,bool start)5053 static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev, bool start)
5054 {
5055 	const struct rtw89_chip_info *chip = rtwdev->chip;
5056 
5057 	if (chip->ops->rfk_scan)
5058 		chip->ops->rfk_scan(rtwdev, start);
5059 }
5060 
rtw89_chip_rfk_track(struct rtw89_dev * rtwdev)5061 static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev)
5062 {
5063 	const struct rtw89_chip_info *chip = rtwdev->chip;
5064 
5065 	if (chip->ops->rfk_track)
5066 		chip->ops->rfk_track(rtwdev);
5067 }
5068 
rtw89_chip_set_txpwr_ctrl(struct rtw89_dev * rtwdev)5069 static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev)
5070 {
5071 	const struct rtw89_chip_info *chip = rtwdev->chip;
5072 
5073 	if (chip->ops->set_txpwr_ctrl)
5074 		chip->ops->set_txpwr_ctrl(rtwdev,  RTW89_PHY_0);
5075 }
5076 
rtw89_chip_power_trim(struct rtw89_dev * rtwdev)5077 static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev)
5078 {
5079 	const struct rtw89_chip_info *chip = rtwdev->chip;
5080 
5081 	if (chip->ops->power_trim)
5082 		chip->ops->power_trim(rtwdev);
5083 }
5084 
rtw89_chip_init_txpwr_unit(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)5085 static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev,
5086 					      enum rtw89_phy_idx phy_idx)
5087 {
5088 	const struct rtw89_chip_info *chip = rtwdev->chip;
5089 
5090 	if (chip->ops->init_txpwr_unit)
5091 		chip->ops->init_txpwr_unit(rtwdev, phy_idx);
5092 }
5093 
rtw89_chip_get_thermal(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path)5094 static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev,
5095 					enum rtw89_rf_path rf_path)
5096 {
5097 	const struct rtw89_chip_info *chip = rtwdev->chip;
5098 
5099 	if (!chip->ops->get_thermal)
5100 		return 0x10;
5101 
5102 	return chip->ops->get_thermal(rtwdev, rf_path);
5103 }
5104 
rtw89_chip_query_ppdu(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct ieee80211_rx_status * status)5105 static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev,
5106 					 struct rtw89_rx_phy_ppdu *phy_ppdu,
5107 					 struct ieee80211_rx_status *status)
5108 {
5109 	const struct rtw89_chip_info *chip = rtwdev->chip;
5110 
5111 	if (chip->ops->query_ppdu)
5112 		chip->ops->query_ppdu(rtwdev, phy_ppdu, status);
5113 }
5114 
rtw89_chip_bb_ctrl_btc_preagc(struct rtw89_dev * rtwdev,bool bt_en)5115 static inline void rtw89_chip_bb_ctrl_btc_preagc(struct rtw89_dev *rtwdev,
5116 						 bool bt_en)
5117 {
5118 	const struct rtw89_chip_info *chip = rtwdev->chip;
5119 
5120 	if (chip->ops->bb_ctrl_btc_preagc)
5121 		chip->ops->bb_ctrl_btc_preagc(rtwdev, bt_en);
5122 }
5123 
rtw89_chip_cfg_txrx_path(struct rtw89_dev * rtwdev)5124 static inline void rtw89_chip_cfg_txrx_path(struct rtw89_dev *rtwdev)
5125 {
5126 	const struct rtw89_chip_info *chip = rtwdev->chip;
5127 
5128 	if (chip->ops->cfg_txrx_path)
5129 		chip->ops->cfg_txrx_path(rtwdev);
5130 }
5131 
5132 static inline
rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif)5133 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,
5134 				       struct ieee80211_vif *vif)
5135 {
5136 	struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
5137 	const struct rtw89_chip_info *chip = rtwdev->chip;
5138 
5139 	if (!vif->bss_conf.he_support || !vif->cfg.assoc)
5140 		return;
5141 
5142 	if (chip->ops->set_txpwr_ul_tb_offset)
5143 		chip->ops->set_txpwr_ul_tb_offset(rtwdev, 0, rtwvif->mac_idx);
5144 }
5145 
rtw89_load_txpwr_table(struct rtw89_dev * rtwdev,const struct rtw89_txpwr_table * tbl)5146 static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev,
5147 					  const struct rtw89_txpwr_table *tbl)
5148 {
5149 	tbl->load(rtwdev, tbl);
5150 }
5151 
rtw89_regd_get(struct rtw89_dev * rtwdev,u8 band)5152 static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band)
5153 {
5154 	const struct rtw89_regd *regd = rtwdev->regulatory.regd;
5155 
5156 	return regd->txpwr_regd[band];
5157 }
5158 
rtw89_ctrl_btg(struct rtw89_dev * rtwdev,bool btg)5159 static inline void rtw89_ctrl_btg(struct rtw89_dev *rtwdev, bool btg)
5160 {
5161 	const struct rtw89_chip_info *chip = rtwdev->chip;
5162 
5163 	if (chip->ops->ctrl_btg)
5164 		chip->ops->ctrl_btg(rtwdev, btg);
5165 }
5166 
5167 static inline
rtw89_chip_query_rxdesc(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,u8 * data,u32 data_offset)5168 void rtw89_chip_query_rxdesc(struct rtw89_dev *rtwdev,
5169 			     struct rtw89_rx_desc_info *desc_info,
5170 			     u8 *data, u32 data_offset)
5171 {
5172 	const struct rtw89_chip_info *chip = rtwdev->chip;
5173 
5174 	chip->ops->query_rxdesc(rtwdev, desc_info, data, data_offset);
5175 }
5176 
5177 static inline
rtw89_chip_fill_txdesc(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)5178 void rtw89_chip_fill_txdesc(struct rtw89_dev *rtwdev,
5179 			    struct rtw89_tx_desc_info *desc_info,
5180 			    void *txdesc)
5181 {
5182 	const struct rtw89_chip_info *chip = rtwdev->chip;
5183 
5184 	chip->ops->fill_txdesc(rtwdev, desc_info, txdesc);
5185 }
5186 
5187 static inline
rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)5188 void rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev *rtwdev,
5189 				  struct rtw89_tx_desc_info *desc_info,
5190 				  void *txdesc)
5191 {
5192 	const struct rtw89_chip_info *chip = rtwdev->chip;
5193 
5194 	chip->ops->fill_txdesc_fwcmd(rtwdev, desc_info, txdesc);
5195 }
5196 
5197 static inline
rtw89_chip_mac_cfg_gnt(struct rtw89_dev * rtwdev,const struct rtw89_mac_ax_coex_gnt * gnt_cfg)5198 void rtw89_chip_mac_cfg_gnt(struct rtw89_dev *rtwdev,
5199 			    const struct rtw89_mac_ax_coex_gnt *gnt_cfg)
5200 {
5201 	const struct rtw89_chip_info *chip = rtwdev->chip;
5202 
5203 	chip->ops->mac_cfg_gnt(rtwdev, gnt_cfg);
5204 }
5205 
rtw89_chip_cfg_ctrl_path(struct rtw89_dev * rtwdev,bool wl)5206 static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl)
5207 {
5208 	const struct rtw89_chip_info *chip = rtwdev->chip;
5209 
5210 	chip->ops->cfg_ctrl_path(rtwdev, wl);
5211 }
5212 
5213 static inline
rtw89_chip_stop_sch_tx(struct rtw89_dev * rtwdev,u8 mac_idx,u32 * tx_en,enum rtw89_sch_tx_sel sel)5214 int rtw89_chip_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx,
5215 			   u32 *tx_en, enum rtw89_sch_tx_sel sel)
5216 {
5217 	const struct rtw89_chip_info *chip = rtwdev->chip;
5218 
5219 	return chip->ops->stop_sch_tx(rtwdev, mac_idx, tx_en, sel);
5220 }
5221 
5222 static inline
rtw89_chip_resume_sch_tx(struct rtw89_dev * rtwdev,u8 mac_idx,u32 tx_en)5223 int rtw89_chip_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en)
5224 {
5225 	const struct rtw89_chip_info *chip = rtwdev->chip;
5226 
5227 	return chip->ops->resume_sch_tx(rtwdev, mac_idx, tx_en);
5228 }
5229 
5230 static inline
rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,struct rtw89_sta * rtwsta)5231 int rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev *rtwdev,
5232 				struct rtw89_vif *rtwvif,
5233 				struct rtw89_sta *rtwsta)
5234 {
5235 	const struct rtw89_chip_info *chip = rtwdev->chip;
5236 
5237 	if (!chip->ops->h2c_dctl_sec_cam)
5238 		return 0;
5239 	return chip->ops->h2c_dctl_sec_cam(rtwdev, rtwvif, rtwsta);
5240 }
5241 
get_hdr_bssid(struct ieee80211_hdr * hdr)5242 static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr)
5243 {
5244 	__le16 fc = hdr->frame_control;
5245 
5246 	if (ieee80211_has_tods(fc))
5247 		return hdr->addr1;
5248 	else if (ieee80211_has_fromds(fc))
5249 		return hdr->addr2;
5250 	else
5251 		return hdr->addr3;
5252 }
5253 
rtw89_sta_has_beamformer_cap(struct ieee80211_sta * sta)5254 static inline bool rtw89_sta_has_beamformer_cap(struct ieee80211_sta *sta)
5255 {
5256 	if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) ||
5257 	    (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) ||
5258 	    (sta->deflink.he_cap.he_cap_elem.phy_cap_info[3] &
5259 			IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) ||
5260 	    (sta->deflink.he_cap.he_cap_elem.phy_cap_info[4] &
5261 			IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER))
5262 		return true;
5263 	return false;
5264 }
5265 
rtw89_fw_suit_get(struct rtw89_dev * rtwdev,enum rtw89_fw_type type)5266 static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev,
5267 						      enum rtw89_fw_type type)
5268 {
5269 	struct rtw89_fw_info *fw_info = &rtwdev->fw;
5270 
5271 	switch (type) {
5272 	case RTW89_FW_WOWLAN:
5273 		return &fw_info->wowlan;
5274 	case RTW89_FW_LOGFMT:
5275 		return &fw_info->log.suit;
5276 	case RTW89_FW_BBMCU0:
5277 		return &fw_info->bbmcu0;
5278 	case RTW89_FW_BBMCU1:
5279 		return &fw_info->bbmcu1;
5280 	default:
5281 		break;
5282 	}
5283 
5284 	return &fw_info->normal;
5285 }
5286 
rtw89_alloc_skb_for_rx(struct rtw89_dev * rtwdev,unsigned int length)5287 static inline struct sk_buff *rtw89_alloc_skb_for_rx(struct rtw89_dev *rtwdev,
5288 						     unsigned int length)
5289 {
5290 	struct sk_buff *skb;
5291 
5292 	if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) {
5293 		skb = dev_alloc_skb(length + RTW89_RADIOTAP_ROOM);
5294 		if (!skb)
5295 			return NULL;
5296 
5297 		skb_reserve(skb, RTW89_RADIOTAP_ROOM);
5298 		return skb;
5299 	}
5300 
5301 	return dev_alloc_skb(length);
5302 }
5303 
rtw89_core_tx_wait_complete(struct rtw89_dev * rtwdev,struct rtw89_tx_skb_data * skb_data,bool tx_done)5304 static inline void rtw89_core_tx_wait_complete(struct rtw89_dev *rtwdev,
5305 					       struct rtw89_tx_skb_data *skb_data,
5306 					       bool tx_done)
5307 {
5308 	struct rtw89_tx_wait_info *wait;
5309 
5310 	rcu_read_lock();
5311 
5312 	wait = rcu_dereference(skb_data->wait);
5313 	if (!wait)
5314 		goto out;
5315 
5316 	wait->tx_done = tx_done;
5317 	complete(&wait->completion);
5318 
5319 out:
5320 	rcu_read_unlock();
5321 }
5322 
5323 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
5324 			struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel);
5325 int rtw89_h2c_tx(struct rtw89_dev *rtwdev,
5326 		 struct sk_buff *skb, bool fwdl);
5327 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel);
5328 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb,
5329 				    int qsel, unsigned int timeout);
5330 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev,
5331 			    struct rtw89_tx_desc_info *desc_info,
5332 			    void *txdesc);
5333 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev,
5334 			       struct rtw89_tx_desc_info *desc_info,
5335 			       void *txdesc);
5336 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev,
5337 				     struct rtw89_tx_desc_info *desc_info,
5338 				     void *txdesc);
5339 void rtw89_core_rx(struct rtw89_dev *rtwdev,
5340 		   struct rtw89_rx_desc_info *desc_info,
5341 		   struct sk_buff *skb);
5342 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev,
5343 			     struct rtw89_rx_desc_info *desc_info,
5344 			     u8 *data, u32 data_offset);
5345 void rtw89_core_napi_start(struct rtw89_dev *rtwdev);
5346 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev);
5347 void rtw89_core_napi_init(struct rtw89_dev *rtwdev);
5348 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev);
5349 int rtw89_core_sta_add(struct rtw89_dev *rtwdev,
5350 		       struct ieee80211_vif *vif,
5351 		       struct ieee80211_sta *sta);
5352 int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev,
5353 			 struct ieee80211_vif *vif,
5354 			 struct ieee80211_sta *sta);
5355 int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev,
5356 			    struct ieee80211_vif *vif,
5357 			    struct ieee80211_sta *sta);
5358 int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev,
5359 			      struct ieee80211_vif *vif,
5360 			      struct ieee80211_sta *sta);
5361 int rtw89_core_sta_remove(struct rtw89_dev *rtwdev,
5362 			  struct ieee80211_vif *vif,
5363 			  struct ieee80211_sta *sta);
5364 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev,
5365 			       struct ieee80211_sta *sta,
5366 			       struct cfg80211_tid_config *tid_config);
5367 int rtw89_core_init(struct rtw89_dev *rtwdev);
5368 void rtw89_core_deinit(struct rtw89_dev *rtwdev);
5369 int rtw89_core_register(struct rtw89_dev *rtwdev);
5370 void rtw89_core_unregister(struct rtw89_dev *rtwdev);
5371 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device,
5372 					   u32 bus_data_size,
5373 					   const struct rtw89_chip_info *chip);
5374 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev);
5375 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev);
5376 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef);
5377 void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef,
5378 			      struct rtw89_chan *chan);
5379 void rtw89_set_channel(struct rtw89_dev *rtwdev);
5380 void rtw89_get_channel(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
5381 		       struct rtw89_chan *chan);
5382 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size);
5383 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit);
5384 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits);
5385 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev,
5386 				    struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx);
5387 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev,
5388 				    struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx);
5389 void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc);
5390 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev);
5391 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate);
5392 int rtw89_regd_setup(struct rtw89_dev *rtwdev);
5393 int rtw89_regd_init(struct rtw89_dev *rtwdev,
5394 		    void (*reg_notifier)(struct wiphy *wiphy, struct regulatory_request *request));
5395 void rtw89_regd_notifier(struct wiphy *wiphy, struct regulatory_request *request);
5396 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev,
5397 			      struct rtw89_traffic_stats *stats);
5398 int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond);
5399 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond,
5400 			 const struct rtw89_completion_data *data);
5401 int rtw89_core_start(struct rtw89_dev *rtwdev);
5402 void rtw89_core_stop(struct rtw89_dev *rtwdev);
5403 void rtw89_core_update_beacon_work(struct work_struct *work);
5404 void rtw89_roc_work(struct work_struct *work);
5405 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
5406 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
5407 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
5408 			   const u8 *mac_addr, bool hw_scan);
5409 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev,
5410 			      struct ieee80211_vif *vif, bool hw_scan);
5411 void rtw89_reg_6ghz_power_recalc(struct rtw89_dev *rtwdev,
5412 				 struct rtw89_vif *rtwvif, bool active);
5413 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event);
5414 
5415 #endif
5416