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Searched refs:RLC_CNTL (Results 1 – 14 of 14) sorted by relevance

/Linux-v6.6/drivers/gpu/drm/radeon/
Dsi.c5204 orig = data = RREG32(RLC_CNTL); in si_halt_rlc()
5208 WREG32(RLC_CNTL, data); in si_halt_rlc()
5220 tmp = RREG32(RLC_CNTL); in si_update_rlc()
5222 WREG32(RLC_CNTL, rlc); in si_update_rlc()
5816 WREG32(RLC_CNTL, 0); in si_rlc_stop()
5825 WREG32(RLC_CNTL, RLC_ENABLE); in si_rlc_start()
Dr600.c1704 WREG32(RLC_CNTL, 0); in r600_gpu_soft_reset()
1836 WREG32(RLC_CNTL, 0); in r600_gpu_pci_config_reset()
3543 WREG32(RLC_CNTL, 0); in r600_rlc_stop()
3548 WREG32(RLC_CNTL, RLC_ENABLE); in r600_rlc_start()
Dsid.h1300 #define RLC_CNTL 0xC300 macro
Dcik.c5810 tmp = RREG32(RLC_CNTL); in cik_update_rlc()
5812 WREG32(RLC_CNTL, rlc); in cik_update_rlc()
5819 orig = data = RREG32(RLC_CNTL); in cik_halt_rlc()
5825 WREG32(RLC_CNTL, data); in cik_halt_rlc()
5877 WREG32(RLC_CNTL, 0); in cik_rlc_stop()
5893 WREG32(RLC_CNTL, RLC_ENABLE); in cik_rlc_start()
Dcikd.h1393 #define RLC_CNTL 0xC300 macro
Devergreend.h384 #define RLC_CNTL 0x3f00 macro
Dr600d.h685 #define RLC_CNTL 0x3f00 macro
Devergreen.c4380 WREG32(RLC_CNTL, mask); in evergreen_rlc_start()
/Linux-v6.6/drivers/gpu/drm/amd/amdgpu/
Dsid.h1328 #define RLC_CNTL 0x30C0 macro
Dgfx_v11_0.c1774 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); in gfx_v11_0_rlc_stop()
1815 WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); in gfx_v11_0_rlc_start()
4679 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; in gfx_v11_0_is_rlc_enabled()
Dgfx_v9_4_3.c1176 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, in gfx_v9_4_3_xcc_rlc_stop()
1212 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, in gfx_v9_4_3_xcc_rlc_start()
Dgfx_v10_0.c5060 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); in gfx_v10_0_rlc_stop()
5103 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); in gfx_v10_0_rlc_start()
7462 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; in gfx_v10_0_is_rlc_enabled()
Dgfx_v8_0.c4053 WREG32_FIELD(RLC_CNTL, RLC_ENABLE_F32, 0); in gfx_v8_0_rlc_stop()
4070 WREG32_FIELD(RLC_CNTL, RLC_ENABLE_F32, 1); in gfx_v8_0_rlc_start()
Dgfx_v9_0.c2835 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 0); in gfx_v9_0_rlc_stop()
2854 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); in gfx_v9_0_rlc_start()