Home
last modified time | relevance | path

Searched refs:REG_FPGA0_IQK (Results 1 – 8 of 8) sorted by relevance

/Linux-v6.6/drivers/net/wireless/realtek/rtl8xxxu/
Drtl8xxxu_8723b.c601 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_iqk_path_a()
603 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_iqk_path_a()
638 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_iqk_path_a()
641 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_iqk_path_a()
674 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_iqk_path_a()
676 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_iqk_path_a()
711 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_rx_iqk_path_a()
713 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_rx_iqk_path_a()
748 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_rx_iqk_path_a()
751 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_rx_iqk_path_a()
[all …]
Drtl8xxxu_8188f.c700 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188fu_init_statistics()
702 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188fu_init_statistics()
842 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188fu_iqk_path_a()
844 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188fu_iqk_path_a()
861 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188fu_iqk_path_a()
864 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188fu_iqk_path_a()
885 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188fu_iqk_path_a()
887 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188fu_iqk_path_a()
915 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188fu_rx_iqk_path_a()
917 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188fu_rx_iqk_path_a()
[all …]
Drtl8xxxu_8710b.c848 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8710bu_init_statistics()
850 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8710bu_init_statistics()
1019 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8710bu_iqk_path_a()
1021 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8710bu_iqk_path_a()
1042 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8710bu_iqk_path_a()
1044 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8710bu_iqk_path_a()
1067 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8710bu_iqk_path_a()
1069 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8710bu_iqk_path_a()
1103 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8710bu_rx_iqk_path_a()
1105 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8710bu_rx_iqk_path_a()
[all …]
Drtl8xxxu_8192e.c718 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); in rtl8192eu_iqk_path_a()
726 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); in rtl8192eu_iqk_path_a()
765 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00); in rtl8192eu_rx_iqk_path_a()
783 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); in rtl8192eu_rx_iqk_path_a()
818 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); in rtl8192eu_rx_iqk_path_a()
828 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); in rtl8192eu_rx_iqk_path_a()
845 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); in rtl8192eu_rx_iqk_path_a()
871 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); in rtl8192eu_rx_iqk_path_a()
891 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); in rtl8192eu_iqk_path_b()
899 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); in rtl8192eu_iqk_path_b()
[all …]
Drtl8xxxu_8192f.c824 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); in rtl8192fu_iqk_path_a()
842 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000); in rtl8192fu_iqk_path_a()
877 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); in rtl8192fu_iqk_path_a()
913 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); in rtl8192fu_rx_iqk_path_a()
922 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000); in rtl8192fu_rx_iqk_path_a()
963 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); in rtl8192fu_rx_iqk_path_a()
975 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); in rtl8192fu_rx_iqk_path_a()
992 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000); in rtl8192fu_rx_iqk_path_a()
1026 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); in rtl8192fu_rx_iqk_path_a()
1048 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); in rtl8192fu_iqk_path_b()
[all …]
Drtl8xxxu_8188e.c666 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188eu_rx_iqk_path_a()
668 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188eu_rx_iqk_path_a()
677 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188eu_rx_iqk_path_a()
679 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188eu_rx_iqk_path_a()
718 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188eu_rx_iqk_path_a()
720 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188eu_rx_iqk_path_a()
728 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188eu_rx_iqk_path_a()
730 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188eu_rx_iqk_path_a()
850 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188eu_phy_iqcalibrate()
852 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188eu_phy_iqcalibrate()
[all …]
Drtl8xxxu_regs.h1130 #define REG_FPGA0_IQK 0x0e28 macro
Drtl8xxxu_core.c3292 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); in rtl8xxxu_phy_iqcalibrate()
3333 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x0); in rtl8xxxu_phy_iqcalibrate()
3335 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); in rtl8xxxu_phy_iqcalibrate()
3366 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0); in rtl8xxxu_phy_iqcalibrate()