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Searched refs:REGV_WR32 (Results 1 – 4 of 4) sorted by relevance

/Linux-v6.6/drivers/accel/ivpu/
Divpu_hw_37xx.c279 REGV_WR32(VPU_37XX_HOST_SS_CPR_RST_CLR, val); in ivpu_boot_host_ss_rst_clr_assert()
296 REGV_WR32(VPU_37XX_HOST_SS_CPR_RST_SET, val); in ivpu_boot_host_ss_rst_drive()
313 REGV_WR32(VPU_37XX_HOST_SS_CPR_CLK_SET, val); in ivpu_boot_host_ss_clk_drive()
388 REGV_WR32(VPU_37XX_HOST_SS_AON_VPU_IDLE_GEN, 0x0); in ivpu_boot_vpu_idle_gen_disable()
401 REGV_WR32(VPU_37XX_HOST_SS_NOC_QREQN, val); in ivpu_boot_host_ss_axi_drive()
434 REGV_WR32(MTL_VPU_TOP_NOC_QREQN, val); in ivpu_boot_host_ss_top_noc_drive()
463 REGV_WR32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, val); in ivpu_boot_pwr_island_trickle_drive()
475 REGV_WR32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0, val); in ivpu_boot_pwr_island_drive()
497 REGV_WR32(VPU_37XX_HOST_SS_AON_PWR_ISO_EN0, val); in ivpu_boot_pwr_island_isolation_drive()
509 REGV_WR32(VPU_37XX_HOST_SS_AON_DPU_ACTIVE, val); in ivpu_boot_dpu_active_drive()
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Divpu_hw_40xx.c278 REGV_WR32(VPU_40XX_HOST_SS_CPR_RST_EN, val); in ivpu_boot_host_ss_rst_drive()
295 REGV_WR32(VPU_40XX_HOST_SS_CPR_CLK_EN, val); in ivpu_boot_host_ss_clk_drive()
370 REGV_WR32(VPU_40XX_HOST_SS_AON_IDLE_GEN, val); in ivpu_boot_idle_gen_drive()
406 REGV_WR32(VPU_40XX_HOST_SS_NOC_QREQN, val); in ivpu_boot_host_ss_axi_drive()
446 REGV_WR32(VPU_40XX_TOP_NOC_QREQN, val); in ivpu_boot_host_ss_top_noc_drive()
475 REGV_WR32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, val); in ivpu_boot_pwr_island_trickle_drive()
490 REGV_WR32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0, val); in ivpu_boot_pwr_island_drive()
514 REGV_WR32(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0, val); in ivpu_boot_pwr_island_isolation_drive()
525 REGV_WR32(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, val); in ivpu_boot_no_snoop_enable()
539 REGV_WR32(VPU_40XX_HOST_IF_TBU_MMUSSIDV, val); in ivpu_boot_tbu_mmu_enable()
[all …]
Divpu_mmu.c385 REGV_WR32(reg, val); in ivpu_mmu_reg_write()
450 REGV_WR32(VPU_37XX_HOST_MMU_CMDQ_PROD, q->prod); in ivpu_mmu_cmdq_sync()
508 REGV_WR32(VPU_37XX_HOST_MMU_CR1, val); in ivpu_mmu_reset()
511 REGV_WR32(VPU_37XX_HOST_MMU_STRTAB_BASE_CFG, mmu->strtab.base_cfg); in ivpu_mmu_reset()
514 REGV_WR32(VPU_37XX_HOST_MMU_CMDQ_PROD, 0); in ivpu_mmu_reset()
515 REGV_WR32(VPU_37XX_HOST_MMU_CMDQ_CONS, 0); in ivpu_mmu_reset()
535 REGV_WR32(VPU_37XX_HOST_MMU_EVTQ_PROD_SEC, 0); in ivpu_mmu_reset()
536 REGV_WR32(VPU_37XX_HOST_MMU_EVTQ_CONS_SEC, 0); in ivpu_mmu_reset()
811 REGV_WR32(VPU_37XX_HOST_MMU_EVTQ_CONS_SEC, evtq->cons); in ivpu_mmu_get_event()
872 REGV_WR32(VPU_37XX_HOST_MMU_GERRORN, gerror_val); in ivpu_mmu_irq_gerr_handler()
Divpu_hw_reg_io.h27 #define REGV_WR32(reg, val) ivpu_hw_reg_wr32(vdev, vdev->regv, (reg), (val), #reg, __func__) macro