Searched refs:REGB_RD32 (Results 1 – 3 of 3) sorted by relevance
167 val = REGB_RD32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0); in ivpu_pll_cmd_send()172 val = REGB_RD32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD1); in ivpu_pll_cmd_send()177 val = REGB_RD32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD2); in ivpu_pll_cmd_send()182 val = REGB_RD32(VPU_40XX_BUTTRESS_WP_REQ_CMD); in ivpu_pll_cmd_send()212 fmin_fuse = REGB_RD32(VPU_40XX_BUTTRESS_FMIN_FUSE); in ivpu_pll_init_frequency_ratios()216 fmax_fuse = REGB_RD32(VPU_40XX_BUTTRESS_FMAX_FUSE); in ivpu_pll_init_frequency_ratios()661 val = REGB_RD32(VPU_40XX_BUTTRESS_D0I3_CONTROL); in ivpu_boot_d0i3_drive()699 fuse = REGB_RD32(VPU_40XX_BUTTRESS_TILE_FUSE); in ivpu_hw_40xx_info_init()745 val = REGB_RD32(VPU_40XX_BUTTRESS_IP_RESET); in ivpu_hw_40xx_reset()788 u32 val = REGB_RD32(VPU_40XX_BUTTRESS_VPU_STATUS); in ivpu_hw_40xx_profiling_freq_reg_set()[all …]
142 val = REGB_RD32(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD0); in ivpu_pll_cmd_send()147 val = REGB_RD32(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD1); in ivpu_pll_cmd_send()152 val = REGB_RD32(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD2); in ivpu_pll_cmd_send()156 val = REGB_RD32(VPU_37XX_BUTTRESS_WP_REQ_CMD); in ivpu_pll_cmd_send()191 fmin_fuse = REGB_RD32(VPU_37XX_BUTTRESS_FMIN_FUSE); in ivpu_pll_init_frequency_ratios()195 fmax_fuse = REGB_RD32(VPU_37XX_BUTTRESS_FMAX_FUSE); in ivpu_pll_init_frequency_ratios()599 val = REGB_RD32(VPU_37XX_BUTTRESS_VPU_D0I3_CONTROL); in ivpu_boot_d0i3_drive()645 val = REGB_RD32(VPU_37XX_BUTTRESS_VPU_IP_RESET); in ivpu_hw_37xx_reset()750 val = REGB_RD32(VPU_37XX_BUTTRESS_VPU_STATUS); in ivpu_hw_37xx_is_idle()811 pll_curr_ratio = REGB_RD32(VPU_37XX_BUTTRESS_CURRENT_PLL); in ivpu_hw_37xx_reg_pll_freq_get()[all …]
18 #define REGB_RD32(reg) ivpu_hw_reg_rd32(vdev, vdev->regb, (reg), #reg, __func__) macro
