Home
last modified time | relevance | path

Searched refs:PLL_VPLL (Results 1 – 23 of 23) sorted by relevance

/Linux-v6.6/arch/arm64/boot/dts/rockchip/
Drk3566-anbernic-rg353x.dtsi20 <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
Drk3566-anbernic-rg503.dts109 <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
Drk3566-radxa-cm3-io.dts267 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
Drk3568-fastrhino-r66s.dtsi474 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
Drk3566-box-demo.dts469 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
Drk3566-lubancat-1.dts579 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
Drk3568-nanopi-r5s.dtsi574 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
Drk3568-roc-pc.dts637 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
Drk3566-roc-pc.dts686 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
Drk3566-soquartz.dtsi672 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
Drk3568-lubancat-2.dts679 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
Drk3568-evb1-v10.dts676 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
Drk3568-odroid-m1.dts728 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
Drk3566-anbernic-rgxx3.dtsi775 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
Drk3566-quartz64-b.dts724 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
Drk3568-bpi-r2-pro.dts839 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
Drk3568-rock-3a.dts842 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
Drk3566-quartz64-a.dts824 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
Drk3399.dtsi1959 <&cru PLL_VPLL>;
/Linux-v6.6/include/dt-bindings/clock/
Drk3399-cru.h17 #define PLL_VPLL 7 macro
Drk3568-cru.h74 #define PLL_VPLL 5 macro
/Linux-v6.6/drivers/clk/rockchip/
Dclk-rk3399.c231 [vpll] = PLL(pll_rk3399, PLL_VPLL, "vpll", mux_pll_p, 0, RK3399_PLL_CON(48),
Dclk-rk3568.c337 [vpll] = PLL(pll_rk3328, PLL_VPLL, "vpll", mux_pll_p,