Searched refs:PLANE_CTL_YUV422_ORDER_MASK (Results 1 – 2 of 2) sorted by relevance
225 val & PLANE_CTL_YUV422_ORDER_MASK); in intel_vgpu_decode_primary_plane()
3630 #define PLANE_CTL_YUV422_ORDER_MASK REG_GENMASK(17, 16) macro3631 #define PLANE_CTL_YUV422_ORDER_YUYV REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 0)3632 #define PLANE_CTL_YUV422_ORDER_UYVY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 1)3633 #define PLANE_CTL_YUV422_ORDER_YVYU REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 2)3634 #define PLANE_CTL_YUV422_ORDER_VYUY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 3)
