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Searched refs:PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE_MASK (Results 1 – 16 of 16) sorted by relevance

/Linux-v6.6/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_11_2_sh_mask.h1675 #define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE_MASK 0x100 macro
Ddce_12_0_sh_mask.h2344 #define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE_MASK … macro
/Linux-v6.6/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_2_0_3_sh_mask.h42 #define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE_MASK … macro
Ddcn_3_0_3_sh_mask.h384 #define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE_MASK … macro
Ddcn_3_0_1_sh_mask.h691 #define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE_MASK … macro
Ddcn_2_1_0_sh_mask.h294 #define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE_MASK … macro
Ddcn_3_2_1_sh_mask.h67 #define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE_MASK … macro
Ddcn_1_0_sh_mask.h1790 #define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE_MASK … macro
Ddcn_3_1_5_sh_mask.h70 #define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE_MASK … macro
Ddcn_3_1_2_sh_mask.h563 #define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE_MASK … macro
Ddcn_3_0_2_sh_mask.h397 #define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE_MASK … macro
Ddcn_3_1_4_sh_mask.h7951 #define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE_MASK … macro
Ddcn_3_1_6_sh_mask.h1085 #define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE_MASK … macro
Ddcn_3_0_0_sh_mask.h378 #define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE_MASK … macro
Ddcn_2_0_0_sh_mask.h397 #define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE_MASK … macro
Ddcn_3_2_0_sh_mask.h68 #define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE_MASK … macro