| /Linux-v6.6/arch/arm/boot/dts/samsung/ |
| D | s3c64xx.dtsi | 147 clocks = <&clocks PCLK_UART2>, <&clocks PCLK_UART2>,
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| /Linux-v6.6/include/dt-bindings/clock/ |
| D | samsung,s3c64xx-clock.h | 86 #define PCLK_UART2 71 macro
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| D | rk3036-cru.h | 70 #define PCLK_UART2 343 macro
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| D | exynos7-clk.h | 94 #define PCLK_UART2 2 macro
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| D | rk3188-cru-common.h | 86 #define PCLK_UART2 334 macro
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| D | rk3128-cru.h | 110 #define PCLK_UART2 343 macro
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| D | rk3228-cru.h | 109 #define PCLK_UART2 343 macro
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| D | rv1108-cru.h | 118 #define PCLK_UART2 267 macro
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| D | px30-cru.h | 153 #define PCLK_UART2 330 macro
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| D | rk3308-cru.h | 178 #define PCLK_UART2 199 macro
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| D | rk3288-cru.h | 135 #define PCLK_UART2 343 macro
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| D | rk3328-cru.h | 143 #define PCLK_UART2 212 macro
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| D | rk3368-cru.h | 127 #define PCLK_UART2 343 macro
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| D | rockchip,rv1126-cru.h | 313 #define PCLK_UART2 251 macro
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| D | rk3399-cru.h | 249 #define PCLK_UART2 354 macro
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| D | rockchip,rk3588-cru.h | 175 #define PCLK_UART2 160 macro
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| D | rk3568-cru.h | 351 #define PCLK_UART2 288 macro
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| /Linux-v6.6/drivers/clk/samsung/ |
| D | clk-s3c64xx.c | 242 GATE_BUS(PCLK_UART2, "pclk_uart2", "pclk", PCLK_GATE, 3),
347 ALIAS(PCLK_UART2, "s3c6400-uart.2", "uart"),
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| /Linux-v6.6/drivers/clk/rockchip/ |
| D | clk-rk3036.c | 419 GATE(PCLK_UART2, "pclk_uart2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 2, GFLAGS),
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| D | clk-rk3128.c | 510 GATE(PCLK_UART2, "pclk_uart2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 2, GFLAGS),
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| D | clk-rk3228.c | 615 GATE(PCLK_UART2, "pclk_uart2", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 14, GFLAGS),
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| D | clk-rv1108.c | 609 GATE(PCLK_UART2, "pclk_uart2", "pclk_bus_pre", 0,
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| D | clk-rk3188.c | 522 GATE(PCLK_UART2, "pclk_uart2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 2, GFLAGS),
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| /Linux-v6.6/arch/arm/boot/dts/rockchip/ |
| D | rk3xxx.dtsi | 424 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
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| D | rv1126.dtsi | 300 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
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