1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Probe module for 8250/16550-type Exar chips PCI serial ports.
4 *
5 * Based on drivers/tty/serial/8250/8250_pci.c,
6 *
7 * Copyright (C) 2017 Sudip Mukherjee, All Rights Reserved.
8 */
9 #include <linux/acpi.h>
10 #include <linux/dmi.h>
11 #include <linux/io.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/pci.h>
15 #include <linux/property.h>
16 #include <linux/serial_core.h>
17 #include <linux/serial_reg.h>
18 #include <linux/slab.h>
19 #include <linux/string.h>
20 #include <linux/tty.h>
21 #include <linux/8250_pci.h>
22 #include <linux/delay.h>
23
24 #include <asm/byteorder.h>
25
26 #include "8250.h"
27
28 #define PCI_DEVICE_ID_ACCESSIO_COM_2S 0x1052
29 #define PCI_DEVICE_ID_ACCESSIO_COM_4S 0x105d
30 #define PCI_DEVICE_ID_ACCESSIO_COM_8S 0x106c
31 #define PCI_DEVICE_ID_ACCESSIO_COM232_8 0x10a8
32 #define PCI_DEVICE_ID_ACCESSIO_COM_2SM 0x10d2
33 #define PCI_DEVICE_ID_ACCESSIO_COM_4SM 0x10db
34 #define PCI_DEVICE_ID_ACCESSIO_COM_8SM 0x10ea
35
36 #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
37 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
38 #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
39 #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
40 #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
41 #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
42 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
43
44 #define PCI_DEVICE_ID_EXAR_XR17V4358 0x4358
45 #define PCI_DEVICE_ID_EXAR_XR17V8358 0x8358
46
47 #define PCI_SUBDEVICE_ID_USR_2980 0x0128
48 #define PCI_SUBDEVICE_ID_USR_2981 0x0129
49
50 #define PCI_DEVICE_ID_SEALEVEL_710xC 0x1001
51 #define PCI_DEVICE_ID_SEALEVEL_720xC 0x1002
52 #define PCI_DEVICE_ID_SEALEVEL_740xC 0x1004
53 #define PCI_DEVICE_ID_SEALEVEL_780xC 0x1008
54 #define PCI_DEVICE_ID_SEALEVEL_716xC 0x1010
55
56 #define UART_EXAR_INT0 0x80
57 #define UART_EXAR_8XMODE 0x88 /* 8X sampling rate select */
58 #define UART_EXAR_SLEEP 0x8b /* Sleep mode */
59 #define UART_EXAR_DVID 0x8d /* Device identification */
60
61 #define UART_EXAR_FCTR 0x08 /* Feature Control Register */
62 #define UART_FCTR_EXAR_IRDA 0x10 /* IrDa data encode select */
63 #define UART_FCTR_EXAR_485 0x20 /* Auto 485 half duplex dir ctl */
64 #define UART_FCTR_EXAR_TRGA 0x00 /* FIFO trigger table A */
65 #define UART_FCTR_EXAR_TRGB 0x60 /* FIFO trigger table B */
66 #define UART_FCTR_EXAR_TRGC 0x80 /* FIFO trigger table C */
67 #define UART_FCTR_EXAR_TRGD 0xc0 /* FIFO trigger table D programmable */
68
69 #define UART_EXAR_TXTRG 0x0a /* Tx FIFO trigger level write-only */
70 #define UART_EXAR_RXTRG 0x0b /* Rx FIFO trigger level write-only */
71
72 #define UART_EXAR_MPIOINT_7_0 0x8f /* MPIOINT[7:0] */
73 #define UART_EXAR_MPIOLVL_7_0 0x90 /* MPIOLVL[7:0] */
74 #define UART_EXAR_MPIO3T_7_0 0x91 /* MPIO3T[7:0] */
75 #define UART_EXAR_MPIOINV_7_0 0x92 /* MPIOINV[7:0] */
76 #define UART_EXAR_MPIOSEL_7_0 0x93 /* MPIOSEL[7:0] */
77 #define UART_EXAR_MPIOOD_7_0 0x94 /* MPIOOD[7:0] */
78 #define UART_EXAR_MPIOINT_15_8 0x95 /* MPIOINT[15:8] */
79 #define UART_EXAR_MPIOLVL_15_8 0x96 /* MPIOLVL[15:8] */
80 #define UART_EXAR_MPIO3T_15_8 0x97 /* MPIO3T[15:8] */
81 #define UART_EXAR_MPIOINV_15_8 0x98 /* MPIOINV[15:8] */
82 #define UART_EXAR_MPIOSEL_15_8 0x99 /* MPIOSEL[15:8] */
83 #define UART_EXAR_MPIOOD_15_8 0x9a /* MPIOOD[15:8] */
84
85 #define UART_EXAR_RS485_DLY(x) ((x) << 4)
86
87 /*
88 * IOT2040 MPIO wiring semantics:
89 *
90 * MPIO Port Function
91 * ---- ---- --------
92 * 0 2 Mode bit 0
93 * 1 2 Mode bit 1
94 * 2 2 Terminate bus
95 * 3 - <reserved>
96 * 4 3 Mode bit 0
97 * 5 3 Mode bit 1
98 * 6 3 Terminate bus
99 * 7 - <reserved>
100 * 8 2 Enable
101 * 9 3 Enable
102 * 10 - Red LED
103 * 11..15 - <unused>
104 */
105
106 /* IOT2040 MPIOs 0..7 */
107 #define IOT2040_UART_MODE_RS232 0x01
108 #define IOT2040_UART_MODE_RS485 0x02
109 #define IOT2040_UART_MODE_RS422 0x03
110 #define IOT2040_UART_TERMINATE_BUS 0x04
111
112 #define IOT2040_UART1_MASK 0x0f
113 #define IOT2040_UART2_SHIFT 4
114
115 #define IOT2040_UARTS_DEFAULT_MODE 0x11 /* both RS232 */
116 #define IOT2040_UARTS_GPIO_LO_MODE 0x88 /* reserved pins as input */
117
118 /* IOT2040 MPIOs 8..15 */
119 #define IOT2040_UARTS_ENABLE 0x03
120 #define IOT2040_UARTS_GPIO_HI_MODE 0xF8 /* enable & LED as outputs */
121
122 struct exar8250;
123
124 struct exar8250_platform {
125 int (*rs485_config)(struct uart_port *port, struct ktermios *termios,
126 struct serial_rs485 *rs485);
127 const struct serial_rs485 *rs485_supported;
128 int (*register_gpio)(struct pci_dev *, struct uart_8250_port *);
129 void (*unregister_gpio)(struct uart_8250_port *);
130 };
131
132 /**
133 * struct exar8250_board - board information
134 * @num_ports: number of serial ports
135 * @reg_shift: describes UART register mapping in PCI memory
136 * @setup: quirk run at ->probe() stage
137 * @exit: quirk run at ->remove() stage
138 */
139 struct exar8250_board {
140 unsigned int num_ports;
141 unsigned int reg_shift;
142 int (*setup)(struct exar8250 *, struct pci_dev *,
143 struct uart_8250_port *, int);
144 void (*exit)(struct pci_dev *pcidev);
145 };
146
147 struct exar8250 {
148 unsigned int nr;
149 struct exar8250_board *board;
150 void __iomem *virt;
151 int line[];
152 };
153
exar_pm(struct uart_port * port,unsigned int state,unsigned int old)154 static void exar_pm(struct uart_port *port, unsigned int state, unsigned int old)
155 {
156 /*
157 * Exar UARTs have a SLEEP register that enables or disables each UART
158 * to enter sleep mode separately. On the XR17V35x the register
159 * is accessible to each UART at the UART_EXAR_SLEEP offset, but
160 * the UART channel may only write to the corresponding bit.
161 */
162 serial_port_out(port, UART_EXAR_SLEEP, state ? 0xff : 0);
163 }
164
165 /*
166 * XR17V35x UARTs have an extra fractional divisor register (DLD)
167 * Calculate divisor with extra 4-bit fractional portion
168 */
xr17v35x_get_divisor(struct uart_port * p,unsigned int baud,unsigned int * frac)169 static unsigned int xr17v35x_get_divisor(struct uart_port *p, unsigned int baud,
170 unsigned int *frac)
171 {
172 unsigned int quot_16;
173
174 quot_16 = DIV_ROUND_CLOSEST(p->uartclk, baud);
175 *frac = quot_16 & 0x0f;
176
177 return quot_16 >> 4;
178 }
179
xr17v35x_set_divisor(struct uart_port * p,unsigned int baud,unsigned int quot,unsigned int quot_frac)180 static void xr17v35x_set_divisor(struct uart_port *p, unsigned int baud,
181 unsigned int quot, unsigned int quot_frac)
182 {
183 serial8250_do_set_divisor(p, baud, quot, quot_frac);
184
185 /* Preserve bits not related to baudrate; DLD[7:4]. */
186 quot_frac |= serial_port_in(p, 0x2) & 0xf0;
187 serial_port_out(p, 0x2, quot_frac);
188 }
189
xr17v35x_startup(struct uart_port * port)190 static int xr17v35x_startup(struct uart_port *port)
191 {
192 /*
193 * First enable access to IER [7:5], ISR [5:4], FCR [5:4],
194 * MCR [7:5] and MSR [7:0]
195 */
196 serial_port_out(port, UART_XR_EFR, UART_EFR_ECB);
197
198 /*
199 * Make sure all interrups are masked until initialization is
200 * complete and the FIFOs are cleared
201 *
202 * Synchronize UART_IER access against the console.
203 */
204 spin_lock_irq(&port->lock);
205 serial_port_out(port, UART_IER, 0);
206 spin_unlock_irq(&port->lock);
207
208 return serial8250_do_startup(port);
209 }
210
exar_shutdown(struct uart_port * port)211 static void exar_shutdown(struct uart_port *port)
212 {
213 bool tx_complete = false;
214 struct uart_8250_port *up = up_to_u8250p(port);
215 struct circ_buf *xmit = &port->state->xmit;
216 int i = 0;
217 u16 lsr;
218
219 do {
220 lsr = serial_in(up, UART_LSR);
221 if (lsr & (UART_LSR_TEMT | UART_LSR_THRE))
222 tx_complete = true;
223 else
224 tx_complete = false;
225 usleep_range(1000, 1100);
226 } while (!uart_circ_empty(xmit) && !tx_complete && i++ < 1000);
227
228 serial8250_do_shutdown(port);
229 }
230
default_setup(struct exar8250 * priv,struct pci_dev * pcidev,int idx,unsigned int offset,struct uart_8250_port * port)231 static int default_setup(struct exar8250 *priv, struct pci_dev *pcidev,
232 int idx, unsigned int offset,
233 struct uart_8250_port *port)
234 {
235 const struct exar8250_board *board = priv->board;
236 unsigned int bar = 0;
237 unsigned char status;
238
239 port->port.iotype = UPIO_MEM;
240 port->port.mapbase = pci_resource_start(pcidev, bar) + offset;
241 port->port.membase = priv->virt + offset;
242 port->port.regshift = board->reg_shift;
243
244 /*
245 * XR17V35x UARTs have an extra divisor register, DLD that gets enabled
246 * with when DLAB is set which will cause the device to incorrectly match
247 * and assign port type to PORT_16650. The EFR for this UART is found
248 * at offset 0x09. Instead check the Deice ID (DVID) register
249 * for a 2, 4 or 8 port UART.
250 */
251 status = readb(port->port.membase + UART_EXAR_DVID);
252 if (status == 0x82 || status == 0x84 || status == 0x88) {
253 port->port.type = PORT_XR17V35X;
254
255 port->port.get_divisor = xr17v35x_get_divisor;
256 port->port.set_divisor = xr17v35x_set_divisor;
257
258 port->port.startup = xr17v35x_startup;
259 } else {
260 port->port.type = PORT_XR17D15X;
261 }
262
263 port->port.pm = exar_pm;
264 port->port.shutdown = exar_shutdown;
265
266 return 0;
267 }
268
269 static int
pci_fastcom335_setup(struct exar8250 * priv,struct pci_dev * pcidev,struct uart_8250_port * port,int idx)270 pci_fastcom335_setup(struct exar8250 *priv, struct pci_dev *pcidev,
271 struct uart_8250_port *port, int idx)
272 {
273 unsigned int offset = idx * 0x200;
274 unsigned int baud = 1843200;
275 u8 __iomem *p;
276 int err;
277
278 port->port.uartclk = baud * 16;
279
280 err = default_setup(priv, pcidev, idx, offset, port);
281 if (err)
282 return err;
283
284 p = port->port.membase;
285
286 writeb(0x00, p + UART_EXAR_8XMODE);
287 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
288 writeb(32, p + UART_EXAR_TXTRG);
289 writeb(32, p + UART_EXAR_RXTRG);
290
291 /*
292 * Setup Multipurpose Input/Output pins.
293 */
294 if (idx == 0) {
295 switch (pcidev->device) {
296 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
297 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
298 writeb(0x78, p + UART_EXAR_MPIOLVL_7_0);
299 writeb(0x00, p + UART_EXAR_MPIOINV_7_0);
300 writeb(0x00, p + UART_EXAR_MPIOSEL_7_0);
301 break;
302 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
303 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
304 writeb(0x00, p + UART_EXAR_MPIOLVL_7_0);
305 writeb(0xc0, p + UART_EXAR_MPIOINV_7_0);
306 writeb(0xc0, p + UART_EXAR_MPIOSEL_7_0);
307 break;
308 }
309 writeb(0x00, p + UART_EXAR_MPIOINT_7_0);
310 writeb(0x00, p + UART_EXAR_MPIO3T_7_0);
311 writeb(0x00, p + UART_EXAR_MPIOOD_7_0);
312 }
313
314 return 0;
315 }
316
317 static int
pci_connect_tech_setup(struct exar8250 * priv,struct pci_dev * pcidev,struct uart_8250_port * port,int idx)318 pci_connect_tech_setup(struct exar8250 *priv, struct pci_dev *pcidev,
319 struct uart_8250_port *port, int idx)
320 {
321 unsigned int offset = idx * 0x200;
322 unsigned int baud = 1843200;
323
324 port->port.uartclk = baud * 16;
325 return default_setup(priv, pcidev, idx, offset, port);
326 }
327
328 static int
pci_xr17c154_setup(struct exar8250 * priv,struct pci_dev * pcidev,struct uart_8250_port * port,int idx)329 pci_xr17c154_setup(struct exar8250 *priv, struct pci_dev *pcidev,
330 struct uart_8250_port *port, int idx)
331 {
332 unsigned int offset = idx * 0x200;
333 unsigned int baud = 921600;
334
335 port->port.uartclk = baud * 16;
336 return default_setup(priv, pcidev, idx, offset, port);
337 }
338
setup_gpio(struct pci_dev * pcidev,u8 __iomem * p)339 static void setup_gpio(struct pci_dev *pcidev, u8 __iomem *p)
340 {
341 /*
342 * The Commtech adapters required the MPIOs to be driven low. The Exar
343 * devices will export them as GPIOs, so we pre-configure them safely
344 * as inputs.
345 */
346
347 u8 dir = 0x00;
348
349 if ((pcidev->vendor == PCI_VENDOR_ID_EXAR) &&
350 (pcidev->subsystem_vendor != PCI_VENDOR_ID_SEALEVEL)) {
351 // Configure GPIO as inputs for Commtech adapters
352 dir = 0xff;
353 } else {
354 // Configure GPIO as outputs for SeaLevel adapters
355 dir = 0x00;
356 }
357
358 writeb(0x00, p + UART_EXAR_MPIOINT_7_0);
359 writeb(0x00, p + UART_EXAR_MPIOLVL_7_0);
360 writeb(0x00, p + UART_EXAR_MPIO3T_7_0);
361 writeb(0x00, p + UART_EXAR_MPIOINV_7_0);
362 writeb(dir, p + UART_EXAR_MPIOSEL_7_0);
363 writeb(0x00, p + UART_EXAR_MPIOOD_7_0);
364 writeb(0x00, p + UART_EXAR_MPIOINT_15_8);
365 writeb(0x00, p + UART_EXAR_MPIOLVL_15_8);
366 writeb(0x00, p + UART_EXAR_MPIO3T_15_8);
367 writeb(0x00, p + UART_EXAR_MPIOINV_15_8);
368 writeb(dir, p + UART_EXAR_MPIOSEL_15_8);
369 writeb(0x00, p + UART_EXAR_MPIOOD_15_8);
370 }
371
__xr17v35x_register_gpio(struct pci_dev * pcidev,const struct software_node * node)372 static struct platform_device *__xr17v35x_register_gpio(struct pci_dev *pcidev,
373 const struct software_node *node)
374 {
375 struct platform_device *pdev;
376
377 pdev = platform_device_alloc("gpio_exar", PLATFORM_DEVID_AUTO);
378 if (!pdev)
379 return NULL;
380
381 pdev->dev.parent = &pcidev->dev;
382 ACPI_COMPANION_SET(&pdev->dev, ACPI_COMPANION(&pcidev->dev));
383
384 if (device_add_software_node(&pdev->dev, node) < 0 ||
385 platform_device_add(pdev) < 0) {
386 platform_device_put(pdev);
387 return NULL;
388 }
389
390 return pdev;
391 }
392
__xr17v35x_unregister_gpio(struct platform_device * pdev)393 static void __xr17v35x_unregister_gpio(struct platform_device *pdev)
394 {
395 device_remove_software_node(&pdev->dev);
396 platform_device_unregister(pdev);
397 }
398
399 static const struct property_entry exar_gpio_properties[] = {
400 PROPERTY_ENTRY_U32("exar,first-pin", 0),
401 PROPERTY_ENTRY_U32("ngpios", 16),
402 { }
403 };
404
405 static const struct software_node exar_gpio_node = {
406 .properties = exar_gpio_properties,
407 };
408
xr17v35x_register_gpio(struct pci_dev * pcidev,struct uart_8250_port * port)409 static int xr17v35x_register_gpio(struct pci_dev *pcidev, struct uart_8250_port *port)
410 {
411 if (pcidev->vendor == PCI_VENDOR_ID_EXAR)
412 port->port.private_data =
413 __xr17v35x_register_gpio(pcidev, &exar_gpio_node);
414
415 return 0;
416 }
417
xr17v35x_unregister_gpio(struct uart_8250_port * port)418 static void xr17v35x_unregister_gpio(struct uart_8250_port *port)
419 {
420 if (!port->port.private_data)
421 return;
422
423 __xr17v35x_unregister_gpio(port->port.private_data);
424 port->port.private_data = NULL;
425 }
426
generic_rs485_config(struct uart_port * port,struct ktermios * termios,struct serial_rs485 * rs485)427 static int generic_rs485_config(struct uart_port *port, struct ktermios *termios,
428 struct serial_rs485 *rs485)
429 {
430 bool is_rs485 = !!(rs485->flags & SER_RS485_ENABLED);
431 u8 __iomem *p = port->membase;
432 u8 value;
433
434 value = readb(p + UART_EXAR_FCTR);
435 if (is_rs485)
436 value |= UART_FCTR_EXAR_485;
437 else
438 value &= ~UART_FCTR_EXAR_485;
439
440 writeb(value, p + UART_EXAR_FCTR);
441
442 if (is_rs485)
443 writeb(UART_EXAR_RS485_DLY(4), p + UART_MSR);
444
445 return 0;
446 }
447
448 static const struct serial_rs485 generic_rs485_supported = {
449 .flags = SER_RS485_ENABLED,
450 };
451
452 static const struct exar8250_platform exar8250_default_platform = {
453 .register_gpio = xr17v35x_register_gpio,
454 .unregister_gpio = xr17v35x_unregister_gpio,
455 .rs485_config = generic_rs485_config,
456 .rs485_supported = &generic_rs485_supported,
457 };
458
iot2040_rs485_config(struct uart_port * port,struct ktermios * termios,struct serial_rs485 * rs485)459 static int iot2040_rs485_config(struct uart_port *port, struct ktermios *termios,
460 struct serial_rs485 *rs485)
461 {
462 bool is_rs485 = !!(rs485->flags & SER_RS485_ENABLED);
463 u8 __iomem *p = port->membase;
464 u8 mask = IOT2040_UART1_MASK;
465 u8 mode, value;
466
467 if (is_rs485) {
468 if (rs485->flags & SER_RS485_RX_DURING_TX)
469 mode = IOT2040_UART_MODE_RS422;
470 else
471 mode = IOT2040_UART_MODE_RS485;
472
473 if (rs485->flags & SER_RS485_TERMINATE_BUS)
474 mode |= IOT2040_UART_TERMINATE_BUS;
475 } else {
476 mode = IOT2040_UART_MODE_RS232;
477 }
478
479 if (port->line == 3) {
480 mask <<= IOT2040_UART2_SHIFT;
481 mode <<= IOT2040_UART2_SHIFT;
482 }
483
484 value = readb(p + UART_EXAR_MPIOLVL_7_0);
485 value &= ~mask;
486 value |= mode;
487 writeb(value, p + UART_EXAR_MPIOLVL_7_0);
488
489 return generic_rs485_config(port, termios, rs485);
490 }
491
492 static const struct serial_rs485 iot2040_rs485_supported = {
493 .flags = SER_RS485_ENABLED | SER_RS485_RX_DURING_TX | SER_RS485_TERMINATE_BUS,
494 };
495
496 static const struct property_entry iot2040_gpio_properties[] = {
497 PROPERTY_ENTRY_U32("exar,first-pin", 10),
498 PROPERTY_ENTRY_U32("ngpios", 1),
499 { }
500 };
501
502 static const struct software_node iot2040_gpio_node = {
503 .properties = iot2040_gpio_properties,
504 };
505
iot2040_register_gpio(struct pci_dev * pcidev,struct uart_8250_port * port)506 static int iot2040_register_gpio(struct pci_dev *pcidev,
507 struct uart_8250_port *port)
508 {
509 u8 __iomem *p = port->port.membase;
510
511 writeb(IOT2040_UARTS_DEFAULT_MODE, p + UART_EXAR_MPIOLVL_7_0);
512 writeb(IOT2040_UARTS_GPIO_LO_MODE, p + UART_EXAR_MPIOSEL_7_0);
513 writeb(IOT2040_UARTS_ENABLE, p + UART_EXAR_MPIOLVL_15_8);
514 writeb(IOT2040_UARTS_GPIO_HI_MODE, p + UART_EXAR_MPIOSEL_15_8);
515
516 port->port.private_data =
517 __xr17v35x_register_gpio(pcidev, &iot2040_gpio_node);
518
519 return 0;
520 }
521
522 static const struct exar8250_platform iot2040_platform = {
523 .rs485_config = iot2040_rs485_config,
524 .rs485_supported = &iot2040_rs485_supported,
525 .register_gpio = iot2040_register_gpio,
526 .unregister_gpio = xr17v35x_unregister_gpio,
527 };
528
529 /*
530 * For SIMATIC IOT2000, only IOT2040 and its variants have the Exar device,
531 * IOT2020 doesn't have. Therefore it is sufficient to match on the common
532 * board name after the device was found.
533 */
534 static const struct dmi_system_id exar_platforms[] = {
535 {
536 .matches = {
537 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"),
538 },
539 .driver_data = (void *)&iot2040_platform,
540 },
541 {}
542 };
543
exar_get_platform(void)544 static const struct exar8250_platform *exar_get_platform(void)
545 {
546 const struct dmi_system_id *dmi_match;
547
548 dmi_match = dmi_first_match(exar_platforms);
549 if (dmi_match)
550 return dmi_match->driver_data;
551
552 return &exar8250_default_platform;
553 }
554
555 static int
pci_xr17v35x_setup(struct exar8250 * priv,struct pci_dev * pcidev,struct uart_8250_port * port,int idx)556 pci_xr17v35x_setup(struct exar8250 *priv, struct pci_dev *pcidev,
557 struct uart_8250_port *port, int idx)
558 {
559 const struct exar8250_platform *platform = exar_get_platform();
560 unsigned int offset = idx * 0x400;
561 unsigned int baud = 7812500;
562 u8 __iomem *p;
563 int ret;
564
565 port->port.uartclk = baud * 16;
566 port->port.rs485_config = platform->rs485_config;
567 port->port.rs485_supported = *(platform->rs485_supported);
568
569 /*
570 * Setup the UART clock for the devices on expansion slot to
571 * half the clock speed of the main chip (which is 125MHz)
572 */
573 if (idx >= 8)
574 port->port.uartclk /= 2;
575
576 ret = default_setup(priv, pcidev, idx, offset, port);
577 if (ret)
578 return ret;
579
580 p = port->port.membase;
581
582 writeb(0x00, p + UART_EXAR_8XMODE);
583 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
584 writeb(128, p + UART_EXAR_TXTRG);
585 writeb(128, p + UART_EXAR_RXTRG);
586
587 if (idx == 0) {
588 /* Setup Multipurpose Input/Output pins. */
589 setup_gpio(pcidev, p);
590
591 ret = platform->register_gpio(pcidev, port);
592 }
593
594 return ret;
595 }
596
pci_xr17v35x_exit(struct pci_dev * pcidev)597 static void pci_xr17v35x_exit(struct pci_dev *pcidev)
598 {
599 const struct exar8250_platform *platform = exar_get_platform();
600 struct exar8250 *priv = pci_get_drvdata(pcidev);
601 struct uart_8250_port *port = serial8250_get_port(priv->line[0]);
602
603 platform->unregister_gpio(port);
604 }
605
exar_misc_clear(struct exar8250 * priv)606 static inline void exar_misc_clear(struct exar8250 *priv)
607 {
608 /* Clear all PCI interrupts by reading INT0. No effect on IIR */
609 readb(priv->virt + UART_EXAR_INT0);
610
611 /* Clear INT0 for Expansion Interface slave ports, too */
612 if (priv->board->num_ports > 8)
613 readb(priv->virt + 0x2000 + UART_EXAR_INT0);
614 }
615
616 /*
617 * These Exar UARTs have an extra interrupt indicator that could fire for a
618 * few interrupts that are not presented/cleared through IIR. One of which is
619 * a wakeup interrupt when coming out of sleep. These interrupts are only
620 * cleared by reading global INT0 or INT1 registers as interrupts are
621 * associated with channel 0. The INT[3:0] registers _are_ accessible from each
622 * channel's address space, but for the sake of bus efficiency we register a
623 * dedicated handler at the PCI device level to handle them.
624 */
exar_misc_handler(int irq,void * data)625 static irqreturn_t exar_misc_handler(int irq, void *data)
626 {
627 exar_misc_clear(data);
628
629 return IRQ_HANDLED;
630 }
631
632 static int
exar_pci_probe(struct pci_dev * pcidev,const struct pci_device_id * ent)633 exar_pci_probe(struct pci_dev *pcidev, const struct pci_device_id *ent)
634 {
635 unsigned int nr_ports, i, bar = 0, maxnr;
636 struct exar8250_board *board;
637 struct uart_8250_port uart;
638 struct exar8250 *priv;
639 int rc;
640
641 board = (struct exar8250_board *)ent->driver_data;
642 if (!board)
643 return -EINVAL;
644
645 rc = pcim_enable_device(pcidev);
646 if (rc)
647 return rc;
648
649 maxnr = pci_resource_len(pcidev, bar) >> (board->reg_shift + 3);
650
651 if (pcidev->vendor == PCI_VENDOR_ID_ACCESSIO)
652 nr_ports = BIT(((pcidev->device & 0x38) >> 3) - 1);
653 else if (board->num_ports)
654 nr_ports = board->num_ports;
655 else if (pcidev->vendor == PCI_VENDOR_ID_SEALEVEL)
656 nr_ports = pcidev->device & 0xff;
657 else
658 nr_ports = pcidev->device & 0x0f;
659
660 priv = devm_kzalloc(&pcidev->dev, struct_size(priv, line, nr_ports), GFP_KERNEL);
661 if (!priv)
662 return -ENOMEM;
663
664 priv->board = board;
665 priv->virt = pcim_iomap(pcidev, bar, 0);
666 if (!priv->virt)
667 return -ENOMEM;
668
669 pci_set_master(pcidev);
670
671 rc = pci_alloc_irq_vectors(pcidev, 1, 1, PCI_IRQ_ALL_TYPES);
672 if (rc < 0)
673 return rc;
674
675 memset(&uart, 0, sizeof(uart));
676 uart.port.flags = UPF_SHARE_IRQ | UPF_EXAR_EFR | UPF_FIXED_TYPE | UPF_FIXED_PORT;
677 uart.port.irq = pci_irq_vector(pcidev, 0);
678 uart.port.dev = &pcidev->dev;
679
680 rc = devm_request_irq(&pcidev->dev, uart.port.irq, exar_misc_handler,
681 IRQF_SHARED, "exar_uart", priv);
682 if (rc)
683 return rc;
684
685 /* Clear interrupts */
686 exar_misc_clear(priv);
687
688 for (i = 0; i < nr_ports && i < maxnr; i++) {
689 rc = board->setup(priv, pcidev, &uart, i);
690 if (rc) {
691 dev_err(&pcidev->dev, "Failed to setup port %u\n", i);
692 break;
693 }
694
695 dev_dbg(&pcidev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
696 uart.port.iobase, uart.port.irq, uart.port.iotype);
697
698 priv->line[i] = serial8250_register_8250_port(&uart);
699 if (priv->line[i] < 0) {
700 dev_err(&pcidev->dev,
701 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
702 uart.port.iobase, uart.port.irq,
703 uart.port.iotype, priv->line[i]);
704 break;
705 }
706 }
707 priv->nr = i;
708 pci_set_drvdata(pcidev, priv);
709 return 0;
710 }
711
exar_pci_remove(struct pci_dev * pcidev)712 static void exar_pci_remove(struct pci_dev *pcidev)
713 {
714 struct exar8250 *priv = pci_get_drvdata(pcidev);
715 unsigned int i;
716
717 for (i = 0; i < priv->nr; i++)
718 serial8250_unregister_port(priv->line[i]);
719
720 if (priv->board->exit)
721 priv->board->exit(pcidev);
722 }
723
exar_suspend(struct device * dev)724 static int __maybe_unused exar_suspend(struct device *dev)
725 {
726 struct pci_dev *pcidev = to_pci_dev(dev);
727 struct exar8250 *priv = pci_get_drvdata(pcidev);
728 unsigned int i;
729
730 for (i = 0; i < priv->nr; i++)
731 if (priv->line[i] >= 0)
732 serial8250_suspend_port(priv->line[i]);
733
734 /* Ensure that every init quirk is properly torn down */
735 if (priv->board->exit)
736 priv->board->exit(pcidev);
737
738 return 0;
739 }
740
exar_resume(struct device * dev)741 static int __maybe_unused exar_resume(struct device *dev)
742 {
743 struct exar8250 *priv = dev_get_drvdata(dev);
744 unsigned int i;
745
746 exar_misc_clear(priv);
747
748 for (i = 0; i < priv->nr; i++)
749 if (priv->line[i] >= 0)
750 serial8250_resume_port(priv->line[i]);
751
752 return 0;
753 }
754
755 static SIMPLE_DEV_PM_OPS(exar_pci_pm, exar_suspend, exar_resume);
756
757 static const struct exar8250_board pbn_fastcom335_2 = {
758 .num_ports = 2,
759 .setup = pci_fastcom335_setup,
760 };
761
762 static const struct exar8250_board pbn_fastcom335_4 = {
763 .num_ports = 4,
764 .setup = pci_fastcom335_setup,
765 };
766
767 static const struct exar8250_board pbn_fastcom335_8 = {
768 .num_ports = 8,
769 .setup = pci_fastcom335_setup,
770 };
771
772 static const struct exar8250_board pbn_connect = {
773 .setup = pci_connect_tech_setup,
774 };
775
776 static const struct exar8250_board pbn_exar_ibm_saturn = {
777 .num_ports = 1,
778 .setup = pci_xr17c154_setup,
779 };
780
781 static const struct exar8250_board pbn_exar_XR17C15x = {
782 .setup = pci_xr17c154_setup,
783 };
784
785 static const struct exar8250_board pbn_exar_XR17V35x = {
786 .setup = pci_xr17v35x_setup,
787 .exit = pci_xr17v35x_exit,
788 };
789
790 static const struct exar8250_board pbn_fastcom35x_2 = {
791 .num_ports = 2,
792 .setup = pci_xr17v35x_setup,
793 .exit = pci_xr17v35x_exit,
794 };
795
796 static const struct exar8250_board pbn_fastcom35x_4 = {
797 .num_ports = 4,
798 .setup = pci_xr17v35x_setup,
799 .exit = pci_xr17v35x_exit,
800 };
801
802 static const struct exar8250_board pbn_fastcom35x_8 = {
803 .num_ports = 8,
804 .setup = pci_xr17v35x_setup,
805 .exit = pci_xr17v35x_exit,
806 };
807
808 static const struct exar8250_board pbn_exar_XR17V4358 = {
809 .num_ports = 12,
810 .setup = pci_xr17v35x_setup,
811 .exit = pci_xr17v35x_exit,
812 };
813
814 static const struct exar8250_board pbn_exar_XR17V8358 = {
815 .num_ports = 16,
816 .setup = pci_xr17v35x_setup,
817 .exit = pci_xr17v35x_exit,
818 };
819
820 #define CONNECT_DEVICE(devid, sdevid, bd) { \
821 PCI_DEVICE_SUB( \
822 PCI_VENDOR_ID_EXAR, \
823 PCI_DEVICE_ID_EXAR_##devid, \
824 PCI_SUBVENDOR_ID_CONNECT_TECH, \
825 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_##sdevid), 0, 0, \
826 (kernel_ulong_t)&bd \
827 }
828
829 #define EXAR_DEVICE(vend, devid, bd) { PCI_DEVICE_DATA(vend, devid, &bd) }
830
831 #define IBM_DEVICE(devid, sdevid, bd) { \
832 PCI_DEVICE_SUB( \
833 PCI_VENDOR_ID_EXAR, \
834 PCI_DEVICE_ID_EXAR_##devid, \
835 PCI_VENDOR_ID_IBM, \
836 PCI_SUBDEVICE_ID_IBM_##sdevid), 0, 0, \
837 (kernel_ulong_t)&bd \
838 }
839
840 #define USR_DEVICE(devid, sdevid, bd) { \
841 PCI_DEVICE_SUB( \
842 PCI_VENDOR_ID_USR, \
843 PCI_DEVICE_ID_EXAR_##devid, \
844 PCI_VENDOR_ID_EXAR, \
845 PCI_SUBDEVICE_ID_USR_##sdevid), 0, 0, \
846 (kernel_ulong_t)&bd \
847 }
848
849 static const struct pci_device_id exar_pci_tbl[] = {
850 EXAR_DEVICE(ACCESSIO, COM_2S, pbn_exar_XR17C15x),
851 EXAR_DEVICE(ACCESSIO, COM_4S, pbn_exar_XR17C15x),
852 EXAR_DEVICE(ACCESSIO, COM_8S, pbn_exar_XR17C15x),
853 EXAR_DEVICE(ACCESSIO, COM232_8, pbn_exar_XR17C15x),
854 EXAR_DEVICE(ACCESSIO, COM_2SM, pbn_exar_XR17C15x),
855 EXAR_DEVICE(ACCESSIO, COM_4SM, pbn_exar_XR17C15x),
856 EXAR_DEVICE(ACCESSIO, COM_8SM, pbn_exar_XR17C15x),
857
858 CONNECT_DEVICE(XR17C152, UART_2_232, pbn_connect),
859 CONNECT_DEVICE(XR17C154, UART_4_232, pbn_connect),
860 CONNECT_DEVICE(XR17C158, UART_8_232, pbn_connect),
861 CONNECT_DEVICE(XR17C152, UART_1_1, pbn_connect),
862 CONNECT_DEVICE(XR17C154, UART_2_2, pbn_connect),
863 CONNECT_DEVICE(XR17C158, UART_4_4, pbn_connect),
864 CONNECT_DEVICE(XR17C152, UART_2, pbn_connect),
865 CONNECT_DEVICE(XR17C154, UART_4, pbn_connect),
866 CONNECT_DEVICE(XR17C158, UART_8, pbn_connect),
867 CONNECT_DEVICE(XR17C152, UART_2_485, pbn_connect),
868 CONNECT_DEVICE(XR17C154, UART_4_485, pbn_connect),
869 CONNECT_DEVICE(XR17C158, UART_8_485, pbn_connect),
870
871 IBM_DEVICE(XR17C152, SATURN_SERIAL_ONE_PORT, pbn_exar_ibm_saturn),
872
873 /* USRobotics USR298x-OEM PCI Modems */
874 USR_DEVICE(XR17C152, 2980, pbn_exar_XR17C15x),
875 USR_DEVICE(XR17C152, 2981, pbn_exar_XR17C15x),
876
877 /* Exar Corp. XR17C15[248] Dual/Quad/Octal UART */
878 EXAR_DEVICE(EXAR, XR17C152, pbn_exar_XR17C15x),
879 EXAR_DEVICE(EXAR, XR17C154, pbn_exar_XR17C15x),
880 EXAR_DEVICE(EXAR, XR17C158, pbn_exar_XR17C15x),
881
882 /* Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs */
883 EXAR_DEVICE(EXAR, XR17V352, pbn_exar_XR17V35x),
884 EXAR_DEVICE(EXAR, XR17V354, pbn_exar_XR17V35x),
885 EXAR_DEVICE(EXAR, XR17V358, pbn_exar_XR17V35x),
886 EXAR_DEVICE(EXAR, XR17V4358, pbn_exar_XR17V4358),
887 EXAR_DEVICE(EXAR, XR17V8358, pbn_exar_XR17V8358),
888 EXAR_DEVICE(COMMTECH, 4222PCIE, pbn_fastcom35x_2),
889 EXAR_DEVICE(COMMTECH, 4224PCIE, pbn_fastcom35x_4),
890 EXAR_DEVICE(COMMTECH, 4228PCIE, pbn_fastcom35x_8),
891
892 EXAR_DEVICE(COMMTECH, 4222PCI335, pbn_fastcom335_2),
893 EXAR_DEVICE(COMMTECH, 4224PCI335, pbn_fastcom335_4),
894 EXAR_DEVICE(COMMTECH, 2324PCI335, pbn_fastcom335_4),
895 EXAR_DEVICE(COMMTECH, 2328PCI335, pbn_fastcom335_8),
896
897 EXAR_DEVICE(SEALEVEL, 710xC, pbn_exar_XR17V35x),
898 EXAR_DEVICE(SEALEVEL, 720xC, pbn_exar_XR17V35x),
899 EXAR_DEVICE(SEALEVEL, 740xC, pbn_exar_XR17V35x),
900 EXAR_DEVICE(SEALEVEL, 780xC, pbn_exar_XR17V35x),
901 EXAR_DEVICE(SEALEVEL, 716xC, pbn_exar_XR17V35x),
902 { 0, }
903 };
904 MODULE_DEVICE_TABLE(pci, exar_pci_tbl);
905
906 static struct pci_driver exar_pci_driver = {
907 .name = "exar_serial",
908 .probe = exar_pci_probe,
909 .remove = exar_pci_remove,
910 .driver = {
911 .pm = &exar_pci_pm,
912 },
913 .id_table = exar_pci_tbl,
914 };
915 module_pci_driver(exar_pci_driver);
916
917 MODULE_LICENSE("GPL");
918 MODULE_DESCRIPTION("Exar Serial Driver");
919 MODULE_AUTHOR("Sudip Mukherjee <sudip.mukherjee@codethink.co.uk>");
920
