1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Actions Semi Owl SoCs SD/MMC driver
4 *
5 * Copyright (c) 2014 Actions Semi Inc.
6 * Copyright (c) 2019 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
7 *
8 * TODO: SDIO support
9 */
10
11 #include <linux/clk.h>
12 #include <linux/delay.h>
13 #include <linux/dmaengine.h>
14 #include <linux/dma-direction.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/interrupt.h>
17 #include <linux/mmc/host.h>
18 #include <linux/mmc/slot-gpio.h>
19 #include <linux/mod_devicetable.h>
20 #include <linux/module.h>
21 #include <linux/platform_device.h>
22 #include <linux/reset.h>
23 #include <linux/spinlock.h>
24
25 /*
26 * SDC registers
27 */
28 #define OWL_REG_SD_EN 0x0000
29 #define OWL_REG_SD_CTL 0x0004
30 #define OWL_REG_SD_STATE 0x0008
31 #define OWL_REG_SD_CMD 0x000c
32 #define OWL_REG_SD_ARG 0x0010
33 #define OWL_REG_SD_RSPBUF0 0x0014
34 #define OWL_REG_SD_RSPBUF1 0x0018
35 #define OWL_REG_SD_RSPBUF2 0x001c
36 #define OWL_REG_SD_RSPBUF3 0x0020
37 #define OWL_REG_SD_RSPBUF4 0x0024
38 #define OWL_REG_SD_DAT 0x0028
39 #define OWL_REG_SD_BLK_SIZE 0x002c
40 #define OWL_REG_SD_BLK_NUM 0x0030
41 #define OWL_REG_SD_BUF_SIZE 0x0034
42
43 /* SD_EN Bits */
44 #define OWL_SD_EN_RANE BIT(31)
45 #define OWL_SD_EN_RAN_SEED(x) (((x) & 0x3f) << 24)
46 #define OWL_SD_EN_S18EN BIT(12)
47 #define OWL_SD_EN_RESE BIT(10)
48 #define OWL_SD_EN_DAT1_S BIT(9)
49 #define OWL_SD_EN_CLK_S BIT(8)
50 #define OWL_SD_ENABLE BIT(7)
51 #define OWL_SD_EN_BSEL BIT(6)
52 #define OWL_SD_EN_SDIOEN BIT(3)
53 #define OWL_SD_EN_DDREN BIT(2)
54 #define OWL_SD_EN_DATAWID(x) (((x) & 0x3) << 0)
55
56 /* SD_CTL Bits */
57 #define OWL_SD_CTL_TOUTEN BIT(31)
58 #define OWL_SD_CTL_TOUTCNT(x) (((x) & 0x7f) << 24)
59 #define OWL_SD_CTL_DELAY_MSK GENMASK(23, 16)
60 #define OWL_SD_CTL_RDELAY(x) (((x) & 0xf) << 20)
61 #define OWL_SD_CTL_WDELAY(x) (((x) & 0xf) << 16)
62 #define OWL_SD_CTL_CMDLEN BIT(13)
63 #define OWL_SD_CTL_SCC BIT(12)
64 #define OWL_SD_CTL_TCN(x) (((x) & 0xf) << 8)
65 #define OWL_SD_CTL_TS BIT(7)
66 #define OWL_SD_CTL_LBE BIT(6)
67 #define OWL_SD_CTL_C7EN BIT(5)
68 #define OWL_SD_CTL_TM(x) (((x) & 0xf) << 0)
69
70 #define OWL_SD_DELAY_LOW_CLK 0x0f
71 #define OWL_SD_DELAY_MID_CLK 0x0a
72 #define OWL_SD_DELAY_HIGH_CLK 0x09
73 #define OWL_SD_RDELAY_DDR50 0x0a
74 #define OWL_SD_WDELAY_DDR50 0x08
75
76 /* SD_STATE Bits */
77 #define OWL_SD_STATE_DAT1BS BIT(18)
78 #define OWL_SD_STATE_SDIOB_P BIT(17)
79 #define OWL_SD_STATE_SDIOB_EN BIT(16)
80 #define OWL_SD_STATE_TOUTE BIT(15)
81 #define OWL_SD_STATE_BAEP BIT(14)
82 #define OWL_SD_STATE_MEMRDY BIT(12)
83 #define OWL_SD_STATE_CMDS BIT(11)
84 #define OWL_SD_STATE_DAT1AS BIT(10)
85 #define OWL_SD_STATE_SDIOA_P BIT(9)
86 #define OWL_SD_STATE_SDIOA_EN BIT(8)
87 #define OWL_SD_STATE_DAT0S BIT(7)
88 #define OWL_SD_STATE_TEIE BIT(6)
89 #define OWL_SD_STATE_TEI BIT(5)
90 #define OWL_SD_STATE_CLNR BIT(4)
91 #define OWL_SD_STATE_CLC BIT(3)
92 #define OWL_SD_STATE_WC16ER BIT(2)
93 #define OWL_SD_STATE_RC16ER BIT(1)
94 #define OWL_SD_STATE_CRC7ER BIT(0)
95
96 #define OWL_CMD_TIMEOUT_MS 30000
97
98 struct owl_mmc_host {
99 struct device *dev;
100 struct reset_control *reset;
101 void __iomem *base;
102 struct clk *clk;
103 struct completion sdc_complete;
104 spinlock_t lock;
105 int irq;
106 u32 clock;
107 bool ddr_50;
108
109 enum dma_data_direction dma_dir;
110 struct dma_chan *dma;
111 struct dma_async_tx_descriptor *desc;
112 struct dma_slave_config dma_cfg;
113 struct completion dma_complete;
114
115 struct mmc_host *mmc;
116 struct mmc_request *mrq;
117 struct mmc_command *cmd;
118 struct mmc_data *data;
119 };
120
owl_mmc_update_reg(void __iomem * reg,unsigned int val,bool state)121 static void owl_mmc_update_reg(void __iomem *reg, unsigned int val, bool state)
122 {
123 unsigned int regval;
124
125 regval = readl(reg);
126
127 if (state)
128 regval |= val;
129 else
130 regval &= ~val;
131
132 writel(regval, reg);
133 }
134
owl_irq_handler(int irq,void * devid)135 static irqreturn_t owl_irq_handler(int irq, void *devid)
136 {
137 struct owl_mmc_host *owl_host = devid;
138 u32 state;
139
140 spin_lock(&owl_host->lock);
141
142 state = readl(owl_host->base + OWL_REG_SD_STATE);
143 if (state & OWL_SD_STATE_TEI) {
144 state = readl(owl_host->base + OWL_REG_SD_STATE);
145 state |= OWL_SD_STATE_TEI;
146 writel(state, owl_host->base + OWL_REG_SD_STATE);
147 complete(&owl_host->sdc_complete);
148 }
149
150 spin_unlock(&owl_host->lock);
151
152 return IRQ_HANDLED;
153 }
154
owl_mmc_finish_request(struct owl_mmc_host * owl_host)155 static void owl_mmc_finish_request(struct owl_mmc_host *owl_host)
156 {
157 struct mmc_request *mrq = owl_host->mrq;
158 struct mmc_data *data = mrq->data;
159
160 /* Should never be NULL */
161 WARN_ON(!mrq);
162
163 owl_host->mrq = NULL;
164
165 if (data)
166 dma_unmap_sg(owl_host->dma->device->dev, data->sg, data->sg_len,
167 owl_host->dma_dir);
168
169 /* Finally finish request */
170 mmc_request_done(owl_host->mmc, mrq);
171 }
172
owl_mmc_send_cmd(struct owl_mmc_host * owl_host,struct mmc_command * cmd,struct mmc_data * data)173 static void owl_mmc_send_cmd(struct owl_mmc_host *owl_host,
174 struct mmc_command *cmd,
175 struct mmc_data *data)
176 {
177 unsigned long timeout;
178 u32 mode, state, resp[2];
179 u32 cmd_rsp_mask = 0;
180
181 init_completion(&owl_host->sdc_complete);
182
183 switch (mmc_resp_type(cmd)) {
184 case MMC_RSP_NONE:
185 mode = OWL_SD_CTL_TM(0);
186 break;
187
188 case MMC_RSP_R1:
189 if (data) {
190 if (data->flags & MMC_DATA_READ)
191 mode = OWL_SD_CTL_TM(4);
192 else
193 mode = OWL_SD_CTL_TM(5);
194 } else {
195 mode = OWL_SD_CTL_TM(1);
196 }
197 cmd_rsp_mask = OWL_SD_STATE_CLNR | OWL_SD_STATE_CRC7ER;
198
199 break;
200
201 case MMC_RSP_R1B:
202 mode = OWL_SD_CTL_TM(3);
203 cmd_rsp_mask = OWL_SD_STATE_CLNR | OWL_SD_STATE_CRC7ER;
204 break;
205
206 case MMC_RSP_R2:
207 mode = OWL_SD_CTL_TM(2);
208 cmd_rsp_mask = OWL_SD_STATE_CLNR | OWL_SD_STATE_CRC7ER;
209 break;
210
211 case MMC_RSP_R3:
212 mode = OWL_SD_CTL_TM(1);
213 cmd_rsp_mask = OWL_SD_STATE_CLNR;
214 break;
215
216 default:
217 dev_warn(owl_host->dev, "Unknown MMC command\n");
218 cmd->error = -EINVAL;
219 return;
220 }
221
222 /* Keep current WDELAY and RDELAY */
223 mode |= (readl(owl_host->base + OWL_REG_SD_CTL) & (0xff << 16));
224
225 /* Start to send corresponding command type */
226 writel(cmd->arg, owl_host->base + OWL_REG_SD_ARG);
227 writel(cmd->opcode, owl_host->base + OWL_REG_SD_CMD);
228
229 /* Set LBE to send clk at the end of last read block */
230 if (data) {
231 mode |= (OWL_SD_CTL_TS | OWL_SD_CTL_LBE | 0x64000000);
232 } else {
233 mode &= ~(OWL_SD_CTL_TOUTEN | OWL_SD_CTL_LBE);
234 mode |= OWL_SD_CTL_TS;
235 }
236
237 owl_host->cmd = cmd;
238
239 /* Start transfer */
240 writel(mode, owl_host->base + OWL_REG_SD_CTL);
241
242 if (data)
243 return;
244
245 timeout = msecs_to_jiffies(cmd->busy_timeout ? cmd->busy_timeout :
246 OWL_CMD_TIMEOUT_MS);
247
248 if (!wait_for_completion_timeout(&owl_host->sdc_complete, timeout)) {
249 dev_err(owl_host->dev, "CMD interrupt timeout\n");
250 cmd->error = -ETIMEDOUT;
251 return;
252 }
253
254 state = readl(owl_host->base + OWL_REG_SD_STATE);
255 if (mmc_resp_type(cmd) & MMC_RSP_PRESENT) {
256 if (cmd_rsp_mask & state) {
257 if (state & OWL_SD_STATE_CLNR) {
258 dev_err(owl_host->dev, "Error CMD_NO_RSP\n");
259 cmd->error = -EILSEQ;
260 return;
261 }
262
263 if (state & OWL_SD_STATE_CRC7ER) {
264 dev_err(owl_host->dev, "Error CMD_RSP_CRC\n");
265 cmd->error = -EILSEQ;
266 return;
267 }
268 }
269
270 if (mmc_resp_type(cmd) & MMC_RSP_136) {
271 cmd->resp[3] = readl(owl_host->base + OWL_REG_SD_RSPBUF0);
272 cmd->resp[2] = readl(owl_host->base + OWL_REG_SD_RSPBUF1);
273 cmd->resp[1] = readl(owl_host->base + OWL_REG_SD_RSPBUF2);
274 cmd->resp[0] = readl(owl_host->base + OWL_REG_SD_RSPBUF3);
275 } else {
276 resp[0] = readl(owl_host->base + OWL_REG_SD_RSPBUF0);
277 resp[1] = readl(owl_host->base + OWL_REG_SD_RSPBUF1);
278 cmd->resp[0] = resp[1] << 24 | resp[0] >> 8;
279 cmd->resp[1] = resp[1] >> 8;
280 }
281 }
282 }
283
owl_mmc_dma_complete(void * param)284 static void owl_mmc_dma_complete(void *param)
285 {
286 struct owl_mmc_host *owl_host = param;
287 struct mmc_data *data = owl_host->data;
288
289 if (data)
290 complete(&owl_host->dma_complete);
291 }
292
owl_mmc_prepare_data(struct owl_mmc_host * owl_host,struct mmc_data * data)293 static int owl_mmc_prepare_data(struct owl_mmc_host *owl_host,
294 struct mmc_data *data)
295 {
296 u32 total;
297
298 owl_mmc_update_reg(owl_host->base + OWL_REG_SD_EN, OWL_SD_EN_BSEL,
299 true);
300 writel(data->blocks, owl_host->base + OWL_REG_SD_BLK_NUM);
301 writel(data->blksz, owl_host->base + OWL_REG_SD_BLK_SIZE);
302 total = data->blksz * data->blocks;
303
304 if (total < 512)
305 writel(total, owl_host->base + OWL_REG_SD_BUF_SIZE);
306 else
307 writel(512, owl_host->base + OWL_REG_SD_BUF_SIZE);
308
309 if (data->flags & MMC_DATA_WRITE) {
310 owl_host->dma_dir = DMA_TO_DEVICE;
311 owl_host->dma_cfg.direction = DMA_MEM_TO_DEV;
312 } else {
313 owl_host->dma_dir = DMA_FROM_DEVICE;
314 owl_host->dma_cfg.direction = DMA_DEV_TO_MEM;
315 }
316
317 dma_map_sg(owl_host->dma->device->dev, data->sg,
318 data->sg_len, owl_host->dma_dir);
319
320 dmaengine_slave_config(owl_host->dma, &owl_host->dma_cfg);
321 owl_host->desc = dmaengine_prep_slave_sg(owl_host->dma, data->sg,
322 data->sg_len,
323 owl_host->dma_cfg.direction,
324 DMA_PREP_INTERRUPT |
325 DMA_CTRL_ACK);
326 if (!owl_host->desc) {
327 dev_err(owl_host->dev, "Can't prepare slave sg\n");
328 return -EBUSY;
329 }
330
331 owl_host->data = data;
332
333 owl_host->desc->callback = owl_mmc_dma_complete;
334 owl_host->desc->callback_param = (void *)owl_host;
335 data->error = 0;
336
337 return 0;
338 }
339
owl_mmc_request(struct mmc_host * mmc,struct mmc_request * mrq)340 static void owl_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
341 {
342 struct owl_mmc_host *owl_host = mmc_priv(mmc);
343 struct mmc_data *data = mrq->data;
344 int ret;
345
346 owl_host->mrq = mrq;
347 if (mrq->data) {
348 ret = owl_mmc_prepare_data(owl_host, data);
349 if (ret < 0) {
350 data->error = ret;
351 goto err_out;
352 }
353
354 init_completion(&owl_host->dma_complete);
355 dmaengine_submit(owl_host->desc);
356 dma_async_issue_pending(owl_host->dma);
357 }
358
359 owl_mmc_send_cmd(owl_host, mrq->cmd, data);
360
361 if (data) {
362 if (!wait_for_completion_timeout(&owl_host->sdc_complete,
363 10 * HZ)) {
364 dev_err(owl_host->dev, "CMD interrupt timeout\n");
365 mrq->cmd->error = -ETIMEDOUT;
366 dmaengine_terminate_all(owl_host->dma);
367 goto err_out;
368 }
369
370 if (!wait_for_completion_timeout(&owl_host->dma_complete,
371 5 * HZ)) {
372 dev_err(owl_host->dev, "DMA interrupt timeout\n");
373 mrq->cmd->error = -ETIMEDOUT;
374 dmaengine_terminate_all(owl_host->dma);
375 goto err_out;
376 }
377
378 if (data->stop)
379 owl_mmc_send_cmd(owl_host, data->stop, NULL);
380
381 data->bytes_xfered = data->blocks * data->blksz;
382 }
383
384 err_out:
385 owl_mmc_finish_request(owl_host);
386 }
387
owl_mmc_set_clk_rate(struct owl_mmc_host * owl_host,unsigned int rate)388 static int owl_mmc_set_clk_rate(struct owl_mmc_host *owl_host,
389 unsigned int rate)
390 {
391 unsigned long clk_rate;
392 int ret;
393 u32 reg;
394
395 reg = readl(owl_host->base + OWL_REG_SD_CTL);
396 reg &= ~OWL_SD_CTL_DELAY_MSK;
397
398 /* Set RDELAY and WDELAY based on the clock */
399 if (rate <= 1000000) {
400 writel(reg | OWL_SD_CTL_RDELAY(OWL_SD_DELAY_LOW_CLK) |
401 OWL_SD_CTL_WDELAY(OWL_SD_DELAY_LOW_CLK),
402 owl_host->base + OWL_REG_SD_CTL);
403 } else if ((rate > 1000000) && (rate <= 26000000)) {
404 writel(reg | OWL_SD_CTL_RDELAY(OWL_SD_DELAY_MID_CLK) |
405 OWL_SD_CTL_WDELAY(OWL_SD_DELAY_MID_CLK),
406 owl_host->base + OWL_REG_SD_CTL);
407 } else if ((rate > 26000000) && (rate <= 52000000) && !owl_host->ddr_50) {
408 writel(reg | OWL_SD_CTL_RDELAY(OWL_SD_DELAY_HIGH_CLK) |
409 OWL_SD_CTL_WDELAY(OWL_SD_DELAY_HIGH_CLK),
410 owl_host->base + OWL_REG_SD_CTL);
411 /* DDR50 mode has special delay chain */
412 } else if ((rate > 26000000) && (rate <= 52000000) && owl_host->ddr_50) {
413 writel(reg | OWL_SD_CTL_RDELAY(OWL_SD_RDELAY_DDR50) |
414 OWL_SD_CTL_WDELAY(OWL_SD_WDELAY_DDR50),
415 owl_host->base + OWL_REG_SD_CTL);
416 } else {
417 dev_err(owl_host->dev, "SD clock rate not supported\n");
418 return -EINVAL;
419 }
420
421 clk_rate = clk_round_rate(owl_host->clk, rate << 1);
422 ret = clk_set_rate(owl_host->clk, clk_rate);
423
424 return ret;
425 }
426
owl_mmc_set_clk(struct owl_mmc_host * owl_host,struct mmc_ios * ios)427 static void owl_mmc_set_clk(struct owl_mmc_host *owl_host, struct mmc_ios *ios)
428 {
429 if (!ios->clock)
430 return;
431
432 owl_host->clock = ios->clock;
433 owl_mmc_set_clk_rate(owl_host, ios->clock);
434 }
435
owl_mmc_set_bus_width(struct owl_mmc_host * owl_host,struct mmc_ios * ios)436 static void owl_mmc_set_bus_width(struct owl_mmc_host *owl_host,
437 struct mmc_ios *ios)
438 {
439 u32 reg;
440
441 reg = readl(owl_host->base + OWL_REG_SD_EN);
442 reg &= ~0x03;
443 switch (ios->bus_width) {
444 case MMC_BUS_WIDTH_1:
445 break;
446 case MMC_BUS_WIDTH_4:
447 reg |= OWL_SD_EN_DATAWID(1);
448 break;
449 case MMC_BUS_WIDTH_8:
450 reg |= OWL_SD_EN_DATAWID(2);
451 break;
452 }
453
454 writel(reg, owl_host->base + OWL_REG_SD_EN);
455 }
456
owl_mmc_ctr_reset(struct owl_mmc_host * owl_host)457 static void owl_mmc_ctr_reset(struct owl_mmc_host *owl_host)
458 {
459 reset_control_assert(owl_host->reset);
460 udelay(20);
461 reset_control_deassert(owl_host->reset);
462 }
463
owl_mmc_power_on(struct owl_mmc_host * owl_host)464 static void owl_mmc_power_on(struct owl_mmc_host *owl_host)
465 {
466 u32 mode;
467
468 init_completion(&owl_host->sdc_complete);
469
470 /* Enable transfer end IRQ */
471 owl_mmc_update_reg(owl_host->base + OWL_REG_SD_STATE,
472 OWL_SD_STATE_TEIE, true);
473
474 /* Send init clk */
475 mode = (readl(owl_host->base + OWL_REG_SD_CTL) & (0xff << 16));
476 mode |= OWL_SD_CTL_TS | OWL_SD_CTL_TCN(5) | OWL_SD_CTL_TM(8);
477 writel(mode, owl_host->base + OWL_REG_SD_CTL);
478
479 if (!wait_for_completion_timeout(&owl_host->sdc_complete, HZ)) {
480 dev_err(owl_host->dev, "CMD interrupt timeout\n");
481 return;
482 }
483 }
484
owl_mmc_set_ios(struct mmc_host * mmc,struct mmc_ios * ios)485 static void owl_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
486 {
487 struct owl_mmc_host *owl_host = mmc_priv(mmc);
488
489 switch (ios->power_mode) {
490 case MMC_POWER_UP:
491 dev_dbg(owl_host->dev, "Powering card up\n");
492
493 /* Reset the SDC controller to clear all previous states */
494 owl_mmc_ctr_reset(owl_host);
495 clk_prepare_enable(owl_host->clk);
496 writel(OWL_SD_ENABLE | OWL_SD_EN_RESE,
497 owl_host->base + OWL_REG_SD_EN);
498
499 break;
500
501 case MMC_POWER_ON:
502 dev_dbg(owl_host->dev, "Powering card on\n");
503 owl_mmc_power_on(owl_host);
504
505 break;
506
507 case MMC_POWER_OFF:
508 dev_dbg(owl_host->dev, "Powering card off\n");
509 clk_disable_unprepare(owl_host->clk);
510
511 return;
512
513 default:
514 dev_dbg(owl_host->dev, "Ignoring unknown card power state\n");
515 break;
516 }
517
518 if (ios->clock != owl_host->clock)
519 owl_mmc_set_clk(owl_host, ios);
520
521 owl_mmc_set_bus_width(owl_host, ios);
522
523 /* Enable DDR mode if requested */
524 if (ios->timing == MMC_TIMING_UHS_DDR50) {
525 owl_host->ddr_50 = true;
526 owl_mmc_update_reg(owl_host->base + OWL_REG_SD_EN,
527 OWL_SD_EN_DDREN, true);
528 } else {
529 owl_host->ddr_50 = false;
530 }
531 }
532
owl_mmc_start_signal_voltage_switch(struct mmc_host * mmc,struct mmc_ios * ios)533 static int owl_mmc_start_signal_voltage_switch(struct mmc_host *mmc,
534 struct mmc_ios *ios)
535 {
536 struct owl_mmc_host *owl_host = mmc_priv(mmc);
537
538 /* It is enough to change the pad ctrl bit for voltage switch */
539 switch (ios->signal_voltage) {
540 case MMC_SIGNAL_VOLTAGE_330:
541 owl_mmc_update_reg(owl_host->base + OWL_REG_SD_EN,
542 OWL_SD_EN_S18EN, false);
543 break;
544 case MMC_SIGNAL_VOLTAGE_180:
545 owl_mmc_update_reg(owl_host->base + OWL_REG_SD_EN,
546 OWL_SD_EN_S18EN, true);
547 break;
548 default:
549 return -ENOTSUPP;
550 }
551
552 return 0;
553 }
554
555 static const struct mmc_host_ops owl_mmc_ops = {
556 .request = owl_mmc_request,
557 .set_ios = owl_mmc_set_ios,
558 .get_ro = mmc_gpio_get_ro,
559 .get_cd = mmc_gpio_get_cd,
560 .start_signal_voltage_switch = owl_mmc_start_signal_voltage_switch,
561 };
562
owl_mmc_probe(struct platform_device * pdev)563 static int owl_mmc_probe(struct platform_device *pdev)
564 {
565 struct owl_mmc_host *owl_host;
566 struct mmc_host *mmc;
567 struct resource *res;
568 int ret;
569
570 mmc = mmc_alloc_host(sizeof(struct owl_mmc_host), &pdev->dev);
571 if (!mmc) {
572 dev_err(&pdev->dev, "mmc alloc host failed\n");
573 return -ENOMEM;
574 }
575 platform_set_drvdata(pdev, mmc);
576
577 owl_host = mmc_priv(mmc);
578 owl_host->dev = &pdev->dev;
579 owl_host->mmc = mmc;
580 spin_lock_init(&owl_host->lock);
581
582 owl_host->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
583 if (IS_ERR(owl_host->base)) {
584 ret = PTR_ERR(owl_host->base);
585 goto err_free_host;
586 }
587
588 owl_host->clk = devm_clk_get(&pdev->dev, NULL);
589 if (IS_ERR(owl_host->clk)) {
590 dev_err(&pdev->dev, "No clock defined\n");
591 ret = PTR_ERR(owl_host->clk);
592 goto err_free_host;
593 }
594
595 owl_host->reset = devm_reset_control_get_exclusive(&pdev->dev, NULL);
596 if (IS_ERR(owl_host->reset)) {
597 dev_err(&pdev->dev, "Could not get reset control\n");
598 ret = PTR_ERR(owl_host->reset);
599 goto err_free_host;
600 }
601
602 mmc->ops = &owl_mmc_ops;
603 mmc->max_blk_count = 512;
604 mmc->max_blk_size = 512;
605 mmc->max_segs = 256;
606 mmc->max_seg_size = 262144;
607 mmc->max_req_size = 262144;
608 /* 100kHz ~ 52MHz */
609 mmc->f_min = 100000;
610 mmc->f_max = 52000000;
611 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
612 MMC_CAP_4_BIT_DATA;
613 mmc->caps2 = (MMC_CAP2_BOOTPART_NOACC | MMC_CAP2_NO_SDIO);
614 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 |
615 MMC_VDD_165_195;
616
617 ret = mmc_of_parse(mmc);
618 if (ret)
619 goto err_free_host;
620
621 pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
622 pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
623 owl_host->dma = dma_request_chan(&pdev->dev, "mmc");
624 if (IS_ERR(owl_host->dma)) {
625 dev_err(owl_host->dev, "Failed to get external DMA channel.\n");
626 ret = PTR_ERR(owl_host->dma);
627 goto err_free_host;
628 }
629
630 dev_info(&pdev->dev, "Using %s for DMA transfers\n",
631 dma_chan_name(owl_host->dma));
632
633 owl_host->dma_cfg.src_addr = res->start + OWL_REG_SD_DAT;
634 owl_host->dma_cfg.dst_addr = res->start + OWL_REG_SD_DAT;
635 owl_host->dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
636 owl_host->dma_cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
637 owl_host->dma_cfg.device_fc = false;
638
639 owl_host->irq = platform_get_irq(pdev, 0);
640 if (owl_host->irq < 0) {
641 ret = owl_host->irq;
642 goto err_release_channel;
643 }
644
645 ret = devm_request_irq(&pdev->dev, owl_host->irq, owl_irq_handler,
646 0, dev_name(&pdev->dev), owl_host);
647 if (ret) {
648 dev_err(&pdev->dev, "Failed to request irq %d\n",
649 owl_host->irq);
650 goto err_release_channel;
651 }
652
653 ret = mmc_add_host(mmc);
654 if (ret) {
655 dev_err(&pdev->dev, "Failed to add host\n");
656 goto err_release_channel;
657 }
658
659 dev_dbg(&pdev->dev, "Owl MMC Controller Initialized\n");
660
661 return 0;
662
663 err_release_channel:
664 dma_release_channel(owl_host->dma);
665 err_free_host:
666 mmc_free_host(mmc);
667
668 return ret;
669 }
670
owl_mmc_remove(struct platform_device * pdev)671 static void owl_mmc_remove(struct platform_device *pdev)
672 {
673 struct mmc_host *mmc = platform_get_drvdata(pdev);
674 struct owl_mmc_host *owl_host = mmc_priv(mmc);
675
676 mmc_remove_host(mmc);
677 disable_irq(owl_host->irq);
678 dma_release_channel(owl_host->dma);
679 mmc_free_host(mmc);
680 }
681
682 static const struct of_device_id owl_mmc_of_match[] = {
683 {.compatible = "actions,owl-mmc",},
684 { /* sentinel */ }
685 };
686 MODULE_DEVICE_TABLE(of, owl_mmc_of_match);
687
688 static struct platform_driver owl_mmc_driver = {
689 .driver = {
690 .name = "owl_mmc",
691 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
692 .of_match_table = owl_mmc_of_match,
693 },
694 .probe = owl_mmc_probe,
695 .remove_new = owl_mmc_remove,
696 };
697 module_platform_driver(owl_mmc_driver);
698
699 MODULE_DESCRIPTION("Actions Semi Owl SoCs SD/MMC Driver");
700 MODULE_AUTHOR("Actions Semi");
701 MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
702 MODULE_LICENSE("GPL");
703
