Searched refs:NumDispClkLevelsEnabled (Results 1 – 13 of 13) sorted by relevance
585 if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS && in dcn31_clk_mgr_helper_populate_bw_params()586 clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) { in dcn31_clk_mgr_helper_populate_bw_params()587 max_dispclk = find_max_clk_value(clock_table->DispClocks, clock_table->NumDispClkLevelsEnabled); in dcn31_clk_mgr_helper_populate_bw_params()588 max_dppclk = find_max_clk_value(clock_table->DppClocks, clock_table->NumDispClkLevelsEnabled); in dcn31_clk_mgr_helper_populate_bw_params()756 smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled, in dcn31_clk_mgr_construct()767 for (i = 0; i < smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled; i++) { in dcn31_clk_mgr_construct()
141 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk member
592 if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS && in dcn314_clk_mgr_helper_populate_bw_params()593 clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) { in dcn314_clk_mgr_helper_populate_bw_params()594 max_dispclk = find_max_clk_value(clock_table->DispClocks, clock_table->NumDispClkLevelsEnabled); in dcn314_clk_mgr_helper_populate_bw_params()595 max_dppclk = find_max_clk_value(clock_table->DppClocks, clock_table->NumDispClkLevelsEnabled); in dcn314_clk_mgr_helper_populate_bw_params()801 smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled, in dcn314_clk_mgr_construct()812 for (i = 0; i < smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled; i++) { in dcn314_clk_mgr_construct()
60 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk member
503 if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS && in dcn316_clk_mgr_helper_populate_bw_params()504 clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) { in dcn316_clk_mgr_helper_populate_bw_params()505 max_dispclk = find_max_clk_value(clock_table->DispClocks, clock_table->NumDispClkLevelsEnabled); in dcn316_clk_mgr_helper_populate_bw_params()506 max_dppclk = find_max_clk_value(clock_table->DppClocks, clock_table->NumDispClkLevelsEnabled); in dcn316_clk_mgr_helper_populate_bw_params()
87 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk member
120 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk member
132 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk member
145 uint8_t NumDispClkLevelsEnabled; //applies to both dispclk and dppclk member
133 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk member
79 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk member
524 …table.entries[i-1].dispclk_mhz = clock_table->DispClocks[clock_table->NumDispClkLevelsEnabled - 1]; in dcn315_clk_mgr_helper_populate_bw_params()525 …k_table.entries[i-1].dppclk_mhz = clock_table->DppClocks[clock_table->NumDispClkLevelsEnabled - 1]; in dcn315_clk_mgr_helper_populate_bw_params()675 smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled, in dcn315_clk_mgr_construct()686 for (i = 0; i < smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled; i++) { in dcn315_clk_mgr_construct()
116 uint8_t NumDispClkLevelsEnabled; //applies to both dispclk and dppclk member