Searched refs:NUM_CHANNELS (Results 1 – 13 of 13) sorted by relevance
26 #define NUM_CHANNELS 15 macro30 u8 channel_set[NUM_CHANNELS];31 u8 channel_cck_power[NUM_CHANNELS]; /*dbm*/32 u8 channel_ofdm_power[NUM_CHANNELS];/*dbm*/
18 enum { CH_RX, CH_TX, NUM_CHANNELS }; enumerator36 struct most_channel_capability capabilities[NUM_CHANNELS];74 BUG_ON(ch_idx < 0 || ch_idx >= NUM_CHANNELS); in configure_channel()128 BUG_ON(ch_idx < 0 || ch_idx >= NUM_CHANNELS); in enqueue()173 BUG_ON(ch_idx < 0 || ch_idx >= NUM_CHANNELS); in poison_channel()303 for (i = 0; i < NUM_CHANNELS; i++) { in i2c_probe()315 dev->most_iface.num_channels = NUM_CHANNELS; in i2c_probe()
54 #define NUM_CHANNELS (NUM_IP22ZILOG * 2) macro961 alloc_one_table(NUM_CHANNELS * sizeof(struct uart_ip22zilog_port)); in ip22zilog_alloc_tables()1069 .nr = NUM_CHANNELS,1085 for (channel = 0; channel < NUM_CHANNELS; channel++) in ip22zilog_prepare()1088 ip22zilog_irq_chain = &ip22zilog_port_table[NUM_CHANNELS - 1]; in ip22zilog_prepare()1090 for (channel = NUM_CHANNELS - 1 ; channel > 0; channel--) in ip22zilog_prepare()1132 for (channel = 0; channel < NUM_CHANNELS; channel++) { in ip22zilog_prepare()1169 for (i = 0; i < NUM_CHANNELS; i++) { in ip22zilog_ports_init()1193 for (i = 0; i < NUM_CHANNELS; i++) { in ip22zilog_exit()
50 #define NUM_CHANNELS MAX(SKX_NUM_CHANNELS, I10NM_NUM_CHANNELS) macro121 } chan[NUM_CHANNELS];
45 #define NUM_CHANNELS 2 /* Max channels */ macro151 u64 dimm_s_size[NUM_CHANNELS];152 u64 dimm_l_size[NUM_CHANNELS];153 int dimm_l_map[NUM_CHANNELS];812 for (i = 0; i < NUM_CHANNELS; i++) { in igen6_get_dimm_config()879 for (i = 0; i < NUM_CHANNELS; i++) { in igen6_reg_dump()1021 layers[0].size = NUM_CHANNELS; in igen6_register_mci()
286 #define NUM_CHANNELS 6 /* Max channels per MC */ macro389 struct pci_dev *pci_tad[NUM_CHANNELS];394 struct sbridge_channel channel[NUM_CHANNELS];1592 : NUM_CHANNELS; in __populate_dimms()1868 for (i = 0; i < NUM_CHANNELS; i++) { in get_memory_layout()1888 for (i = 0; i < NUM_CHANNELS; i++) { in get_memory_layout()2379 if (channel >= NUM_CHANNELS) { in get_memory_error_data_from_mce()3202 first_channel = find_first_bit(&channel_mask, NUM_CHANNELS); in sbridge_mce_output_error()3358 KNL_MAX_CHANNELS : NUM_CHANNELS; in sbridge_register_mci()
458 layers[0].size = NUM_CHANNELS; in skx_register_mci()707 for (j = 0; j < NUM_CHANNELS; j++) { in skx_remove()
59 for (i = 0; i < NUM_CHANNELS; i++) { in orinoco_wiphy_register()183 if ((channel < 1) || (channel > NUM_CHANNELS) || in orinoco_set_monitor_channel()
21 #define NUM_CHANNELS 14 macro
1195 if ((channel < 1) || (channel > NUM_CHANNELS)) { in orinoco_hw_get_freq()
457 if ((chan < 1) || (chan > NUM_CHANNELS) || in orinoco_ioctl_setfreq()
29 #define NUM_CHANNELS 8 macro
52 #define NUM_CHANNELS ARRAY_SIZE(channel_freq) macro315 i < NUM_CHANNELS && chs < IW_MAX_FREQUENCIES; i++) in gelic_wl_get_range()
