Searched refs:NIX_TXSCH_LVL_TL1 (Results 1 – 6 of 6) sorted by relevance
36 {NIX_TXSCH_LVL_TL1, 1, 0xFFFF, {{0x0C00, 0x0D98} } },
139 NIX_TXSCH_LVL_TL1 = 0x4, enumerator
1648 case NIX_TXSCH_LVL_TL1: in handle_txschq_shaper_update()1770 case NIX_TXSCH_LVL_TL1: in nix_reset_tx_shaping()1851 case NIX_TXSCH_LVL_TL1: in nix_clear_tx_xoff()2146 for (lvl = NIX_TXSCH_LVL_SMQ; lvl <= NIX_TXSCH_LVL_TL1; lvl++) { in nix_smq_flush_fill_ctx()2148 if (lvl == NIX_TXSCH_LVL_TL1) { in nix_smq_flush_fill_ctx()2227 for (lvl = NIX_TXSCH_LVL_SMQ; lvl <= NIX_TXSCH_LVL_TL1; lvl++) { in nix_smq_flush_enadis_rate()2236 if (lvl != NIX_TXSCH_LVL_TL1) in nix_smq_flush_enadis_rate()2240 if (lvl != NIX_TXSCH_LVL_TL1) in nix_smq_flush_enadis_rate()2343 nix_clear_tx_xoff(rvu, blkaddr, NIX_TXSCH_LVL_TL1, in nix_txschq_free()2350 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL1]; in nix_txschq_free()[all …]
65 hw->cap.nix_tx_aggr_lvl = NIX_TXSCH_LVL_TL1; in rvu_setup_hw_capabilities()1984 rsp->schq_nix1[NIX_TXSCH_LVL_TL1] = 1; in rvu_mbox_handler_free_rsrc_cnt()1986 rsp->schq[NIX_TXSCH_LVL_TL1] = 1; in rvu_mbox_handler_free_rsrc_cnt()
219 else if (parent->level == NIX_TXSCH_LVL_TL1) in otx2_qos_txschq_set_parent_topology()411 node->level = NIX_TXSCH_LVL_TL1; in otx2_qos_alloc_root()1043 if (root->level == NIX_TXSCH_LVL_TL1) { in otx2_qos_root_add()1050 root->level == NIX_TXSCH_LVL_TL1) { in otx2_qos_root_add()1156 if (parent->level == NIX_TXSCH_LVL_TL1) in otx2_reset_dwrr_prio()1624 if (root->level != NIX_TXSCH_LVL_TL1) { in otx2_qos_config_txschq()
671 parent = schq_list[NIX_TXSCH_LVL_TL1][prio]; in otx2_txschq_config()687 } else if (lvl == NIX_TXSCH_LVL_TL1) { in otx2_txschq_config()
