| /Linux-v6.6/drivers/mtd/nand/raw/ |
| D | Kconfig | 3 tristate "Raw/Parallel NAND Device Support"
8 NAND flash devices. For further information see
13 comment "Raw/parallel NAND flash controllers"
19 tristate "Denali NAND controller on Intel Moorestown"
23 Enable the driver for NAND flash on Intel Moorestown, using the
24 Denali NAND controller core.
27 tristate "Denali NAND controller as a DT device"
31 Enable the driver for NAND flash on platforms using a Denali NAND
35 tristate "Amstrad E3 NAND controller"
39 Support for NAND flash on Amstrad E3 (Delta).
[all …]
|
| /Linux-v6.6/drivers/mtd/nand/raw/brcmnand/ |
| D | Kconfig | 2 tristate "Broadcom STB NAND controller"
6 Enables the Broadcom NAND controller driver. The controller was
13 tristate "Broadcom BCM63xx NAND controller glue"
16 Enables the BRCMNAND glue driver to register the NAND controller
20 tristate "Broadcom BCMA NAND controller"
29 tristate "Broadcom BCMBCA NAND controller glue"
32 Enables the BRCMNAND glue driver to register the NAND controller
39 Enables the BRCMNAND glue driver to register the NAND controller
43 tristate "Broadcom iProc NAND controller glue"
46 Enables the BRCMNAND controller glue driver to register the NAND
|
| /Linux-v6.6/Documentation/devicetree/bindings/mtd/ |
| D | nvidia-tegra20-nand.txt | 1 NVIDIA Tegra NAND Flash controller
18 Individual NAND chips are children of the NAND controller node. Currently
19 only one NAND chip supported.
25 - nand-ecc-mode: String, operation mode of the NAND ecc mode. Currently only
27 - nand-ecc-algo: string, algorithm of NAND ECC.
41 Optional child node of NAND chip nodes:
|
| D | fsmc-nand.txt | 2 NAND Interface
13 - timings: array of 6 bytes for NAND timings. The meanings of these bytes
27 NAND flash in response to SMWAITn. Zero means 1 cycle,
32 - bank: default NAND bank to use (0-3 are valid, 0 is the default).
47 0xd2000000 0x0010 /* NAND Base DATA */
48 0xd2020000 0x0010 /* NAND Base ADDR */
49 0xd2010000 0x0010>; /* NAND Base CMD */
|
| D | gpio-control-nand.txt | 1 GPIO assisted NAND flash
3 The GPIO assisted NAND flash uses a memory mapped interface to
4 read/write the NAND commands and data and GPIO pins for the control
10 resource describes the data bus connected to the NAND flash and all accesses
14 - gpios : Specifies the GPIO pins to control the NAND device. The order of
24 the GPIO's and the NAND flash data bus. If present, then after changing
|
| D | atmel-nand.txt | 1 Atmel NAND flash controller bindings
3 The NAND flash controller node should be defined under the EBI bus (see
5 One or several NAND devices can be defined under this NAND controller.
6 The NAND controller might be connected to an ECC engine.
8 * NAND controller bindings:
30 * NAND device/chip bindings:
33 - reg: describes the CS lines assigned to the NAND device. If the NAND device
36 1st entry: the CS line this NAND chip is connected to
42 - rb-gpios: the GPIO(s) used to check the Ready/Busy status of the NAND.
64 SAMA5 SoCs embed an advanced NAND controller logic to automate READ/WRITE page
[all …]
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| D | vf610-nfc.txt | 1 Freescale's NAND flash controller (NFC)
3 This variant of the Freescale NAND flash controller (NFC) can be found on
13 - assigned-clock-rates: The NAND bus timing is derived from this clock
14 rate and should not exceed maximum timing for any NAND memory chip
15 in a board stuffing. Typical NAND memory timings derived from this
24 only handle one NAND chip.
|
| D | davinci-nand.txt | 1 Device tree bindings for Texas instruments Davinci/Keystone NAND controller
4 NAND interface contains.
29 address for the chip select space the NAND Flash
35 address for the chip select space the NAND Flash
42 - nand-ecc-mode: operation mode of the NAND ecc mode. ECC mode
58 - ti,davinci-ecc-mode: operation mode of the NAND ecc mode. ECC mode
71 the address space. See partition.txt for more detail. The NAND Flash timing
|
| D | lpc32xx-mlc.txt | 1 NXP LPC32xx SoC NAND MLC controller
6 - interrupts: The NAND interrupt specification
7 - gpios: GPIO specification for NAND write protect
10 User Manual 7.5.14 MLC NAND Timing Register (the values here are specified in
|
| D | cadence-nand-controller.txt | 1 * Cadence NAND controller
16 - dmas: shall reference DMA channel associated to the NAND controller
24 Child nodes represent the available NAND chips.
26 Required properties of NAND chips:
|
| D | mxic-nand.txt | 1 Macronix Raw NAND Controller Device Tree Bindings
9 - interrupts: interrupt line connected to this raw NAND controller
15 - children nodes represent the available NAND chips.
|
| /Linux-v6.6/drivers/pinctrl/tegra/ |
| D | pinctrl-tegra30.c | 2194 …PINGROUP(gmi_wp_n_pc7, RSVD1, NAND, GMI, GMI_ALT, 0x31c0, N, …
2219 …PINGROUP(gmi_ad0_pg0, RSVD1, NAND, GMI, RSVD4, 0x31f0, N, …
2220 …PINGROUP(gmi_ad1_pg1, RSVD1, NAND, GMI, RSVD4, 0x31f4, N, …
2221 …PINGROUP(gmi_ad2_pg2, RSVD1, NAND, GMI, RSVD4, 0x31f8, N, …
2222 …PINGROUP(gmi_ad3_pg3, RSVD1, NAND, GMI, RSVD4, 0x31fc, N, …
2223 …PINGROUP(gmi_ad4_pg4, RSVD1, NAND, GMI, RSVD4, 0x3200, N, …
2224 …PINGROUP(gmi_ad5_pg5, RSVD1, NAND, GMI, RSVD4, 0x3204, N, …
2225 …PINGROUP(gmi_ad6_pg6, RSVD1, NAND, GMI, RSVD4, 0x3208, N, …
2226 …PINGROUP(gmi_ad7_pg7, RSVD1, NAND, GMI, RSVD4, 0x320c, N, …
2227 …PINGROUP(gmi_ad8_ph0, PWM0, NAND, GMI, RSVD4, 0x3210, N, …
[all …]
|
| D | pinctrl-tegra114.c | 1662 …PINGROUP(gmi_wp_n_pc7, RSVD1, NAND, GMI, GMI_ALT, 0x31c0, N, N…
1664 …PINGROUP(gmi_wait_pi7, SPI4, NAND, GMI, DTV, 0x31c8, N, N…
1665 …PINGROUP(gmi_adv_n_pk0, RSVD1, NAND, GMI, TRACE, 0x31cc, N, N…
1666 …PINGROUP(gmi_clk_pk1, SDMMC2, NAND, GMI, TRACE, 0x31d0, N, N…
1667 …PINGROUP(gmi_cs0_n_pj0, RSVD1, NAND, GMI, USB, 0x31d4, N, N…
1668 …PINGROUP(gmi_cs1_n_pj2, RSVD1, NAND, GMI, SOC, 0x31d8, N, N…
1669 …PINGROUP(gmi_cs2_n_pk3, SDMMC2, NAND, GMI, TRACE, 0x31dc, N, N…
1670 …PINGROUP(gmi_cs3_n_pk4, SDMMC2, NAND, GMI, GMI_ALT, 0x31e0, N, N…
1671 …PINGROUP(gmi_cs4_n_pk2, USB, NAND, GMI, TRACE, 0x31e4, N, N…
1672 …PINGROUP(gmi_cs6_n_pi3, NAND, NAND_ALT, GMI, SPI4, 0x31e8, N, N…
[all …]
|
| /Linux-v6.6/arch/powerpc/boot/dts/fsl/ |
| D | p1010rdb-pa.dtsi | 40 label = "NAND U-Boot Image";
47 label = "NAND DTB Image";
53 label = "NAND Linux Kernel Image";
59 label = "NAND Compressed RFS Image";
65 label = "NAND JFFS2 Root File System";
71 label = "NAND User area";
|
| D | p2020rdb.dts | 31 /* NOR and NAND Flashes */
93 label = "NAND (RO) U-Boot Image";
100 label = "NAND (RO) DTB Image";
107 label = "NAND (RO) Linux Kernel Image";
114 label = "NAND (RO) Compressed RFS Image";
121 label = "NAND (RW) JFFS2 Root File System";
127 label = "NAND (RW) Writable User area";
|
| D | p1021mds.dts | 25 /* NAND Flash, BCSR, PMC0/1*/
42 label = "NAND (RO) U-Boot Image";
49 label = "NAND (RO) DTB Image";
56 label = "NAND (RO) Linux Kernel Image";
63 label = "NAND (RO) Compressed RFS Image";
70 label = "NAND (RW) JFFS2 Root File System";
76 label = "NAND (RW) Writable User area";
82 label = "NAND (RO) QE Ucode";
|
| /Linux-v6.6/arch/arm64/boot/dts/marvell/ |
| D | cn9130-db.dts | 14 /* Setup A has SPI1 flash as a boot device, while setup B uses NAND flash.
15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
16 * simultaneously. When SPI controller is enabled, NAND should be disabled.
|
| D | cn9131-db.dts | 14 /* Setup A has SPI1 flash as a boot device, while setup B uses NAND flash.
15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
16 * simultaneously. When SPI controller is enabled, NAND should be disabled.
|
| D | cn9132-db-B.dts | 14 /* Setup B has NAND flash as a boot device, while regular setup uses SPI flash.
15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
16 * simultaneously. When NAND controller is enabled, SPI1 should be disabled.
|
| D | cn9132-db.dts | 14 /* Setup A has SPI1 flash as a boot device, while setup B uses NAND flash.
15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
16 * simultaneously. When SPI controller is enabled, NAND should be disabled.
|
| D | cn9130-db-B.dts | 14 /* Setup B has NAND flash as a boot device, while regular setup uses SPI flash.
15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
16 * simultaneously. When NAND controller is enabled, SPI1 should be disabled.
|
| D | cn9131-db-B.dts | 14 /* Setup B has NAND flash as a boot device, while regular setup uses SPI flash.
15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
16 * simultaneously. When NAND controller is enabled, SPI1 should be disabled.
|
| /Linux-v6.6/drivers/mtd/nand/ |
| D | Kconfig | 3 menu "NAND" menu
26 widely used with old parts, newer NAND chips usually require
31 bool "NAND ECC Smart Media byte order"
46 ECC codes. They are used with NAND devices requiring more than 1 bit
|
| /Linux-v6.6/arch/arm/boot/dts/ti/omap/ |
| D | dra72-evm-common.dtsi | 311 * support NAND on dra72-evm. Keep it disabled. Enabling it
317 /* To use NAND, DIP switch SW5 must be set like so:
354 * NAND flash this is equal to size of erase-block */
358 label = "NAND.SPL";
362 label = "NAND.SPL.backup1";
366 label = "NAND.SPL.backup2";
370 label = "NAND.SPL.backup3";
374 label = "NAND.u-boot-spl-os";
378 label = "NAND.u-boot";
382 label = "NAND.u-boot-env";
[all …]
|
| D | dra7-evm.dts | 442 * support NAND on dra7-evm. Keep it disabled. Enabling it
481 * NAND flash this is equal to size of erase-block */
485 label = "NAND.SPL";
489 label = "NAND.SPL.backup1";
493 label = "NAND.SPL.backup2";
497 label = "NAND.SPL.backup3";
501 label = "NAND.u-boot-spl-os";
505 label = "NAND.u-boot";
509 label = "NAND.u-boot-env";
513 label = "NAND.u-boot-env.backup1";
[all …]
|
