Searched refs:MTL_GSC_HECI1_BASE (Results 1 – 4 of 4) sorted by relevance
19 u32 fw_status = intel_uncore_read(uncore, HECI_FWSTS(MTL_GSC_HECI1_BASE, 1)); in gsc_is_in_reset()33 fw_status = intel_uncore_read(uncore, HECI_FWSTS(MTL_GSC_HECI1_BASE, 1)); in gsc_uc_get_fw_status()311 HECI_FWSTS(MTL_GSC_HECI1_BASE, 1), in gsc_fw_wait()
356 HECI_FWSTS(MTL_GSC_HECI1_BASE, i)); in intel_gsc_uc_load_status()
313 huc->status[INTEL_HUC_AUTH_BY_GSC].reg = HECI_FWSTS(MTL_GSC_HECI1_BASE, 5); in intel_huc_init_early()
931 #define MTL_GSC_HECI1_BASE 0x00116000 macro
