Searched refs:MPIC (Results 1 – 25 of 32) sorted by relevance
12
4 MPIC interrupt controller9 - KVM_DEV_TYPE_FSL_MPIC_20 Freescale MPIC v2.010 - KVM_DEV_TYPE_FSL_MPIC_42 Freescale MPIC v4.212 Only one MPIC instance, of any type, may be instantiated. The created13 MPIC will act as the system interrupt controller, connecting to each21 Base address of the 256 KiB MPIC register space. Must be26 Access an MPIC register, as if the access were made from the guest.27 "attr" is the byte offset into the MPIC register space. Accesses46 The MPIC emulation supports IRQ routing. Only a single MPIC device can53 The numbering is the same as the MPIC device tree binding -- based on
68 MPIC: interrupt-controller { label88 interrupt-parent = <&MPIC>;114 interrupt-parent = <&MPIC>;125 interrupt-parent = <&MPIC>;132 interrupt-parent = <&MPIC>;140 interrupt-parent = <&MPIC>;146 interrupt-parent = <&MPIC>;153 interrupt-parent = <&MPIC>;182 interrupt-map = </*Status*/ 0x0 &MPIC 81 0x4183 /*Wake*/ 0x1 &MPIC 82 0x4>;[all …]
67 MPIC: interrupt-controller { label102 interrupt-parent = <&MPIC>;114 interrupt-parent = <&MPIC>;157 0x0 0x0 0x0 0x1 &MPIC 46 0x2 /* int A */158 0x0 0x0 0x0 0x2 &MPIC 47 0x2 /* int B */159 0x0 0x0 0x0 0x3 &MPIC 48 0x2 /* int C */160 0x0 0x0 0x0 0x4 &MPIC 49 0x2 /* int D */>;194 0x0 0x0 0x0 0x1 &MPIC 38 0x2 /* int A */195 0x0 0x0 0x0 0x2 &MPIC 39 0x2 /* int B */196 0x0 0x0 0x0 0x3 &MPIC 40 0x2 /* int C */[all …]
55 interrupt-parent = <&MPIC>;86 interrupt-parent = <&MPIC>;99 interrupt-parent = <&MPIC>;112 interrupt-parent = <&MPIC>;123 interrupt-parent = <&MPIC>;127 MPIC: pic@7400 { label153 interrupt-parent = <&MPIC>;189 interrupt-parent = <&MPIC>;
104 MPIC: interrupt-controller { label137 interrupt-parent = <&MPIC>;
2 Freescale MPIC Interrupt Controller Node6 The Freescale MPIC interrupt controller is found on all PowerQUICC17 Definition: Shall include "fsl,mpic". Freescale MPIC20 0x10 in the MPIC.51 MPIC must not be reset by the client program, and that63 If present the MPIC will be assumed to be big-endian. Some64 device-trees omit this property on MPIC nodes even when the MPIC is70 If present the MPIC will be assumed to only be able to route71 non-IPI interrupts to a single CPU at a time (EG: Freescale MPIC).112 MPIC a block of registers referred to as[all …]
1 * FSL MPIC Message Registers4 representation of the message register blocks found in some FSL MPIC12 the MPIC containing the message registers.
1 * Freescale MPIC timers
30 MPIC v4.3 does not support this property because the 32 interrupts of an
90 config MPIC config94 bool "MPIC Global Timer"95 depends on MPIC && FSL_SOC97 The MPIC global timer is a hardware timer inside the105 tristate "Freescale MPIC global timer wakeup driver"108 The driver provides a way to wake up the system by MPIC120 bool "MPIC message register support"121 depends on MPIC123 Enables support for the MPIC message registers. These161 depends on MPIC[all …]
9 select MPIC24 select MPIC44 select MPIC57 select MPIC
21 - interrupts: If defined, then it indicates that this MPIC is23 typically the case on Armada 375 and Armada 38x, where the MPIC is25 indicate to which GIC interrupt the MPIC output is connected.
5 select MPIC17 select MPIC
52 select MPIC61 select MPIC
6 select MPIC
18 default y if MPIC
5 select MPIC
225 bool "KVM in-kernel MPIC emulation"232 Enable support for emulating MPIC devices inside the235 Freescale's MPIC implementation.
2 * PQ3 MPIC Message (Group B) device tree stub [ controller @ offset 0x42400 ]
2 * PQ3 MPIC Timer (Group B) device tree stub [ controller @ offset 0x42100 ]
2 * PQ3 MPIC device tree stub [ controller @ offset 0x40000 ]
2 * QorIQ MPIC device tree stub [ controller @ offset 0x40000 ]
19 select MPIC
