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Searched refs:MPCC0_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT (Results 1 – 13 of 13) sorted by relevance

/Linux-v6.6/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_2_0_3_sh_mask.h10834 #define MPCC0_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT … macro
Ddcn_3_0_3_sh_mask.h24152 #define MPCC0_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT … macro
Ddcn_3_0_1_sh_mask.h40103 #define MPCC0_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT … macro
Ddcn_2_1_0_sh_mask.h20218 #define MPCC0_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT … macro
Ddcn_3_2_1_sh_mask.h15069 #define MPCC0_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT … macro
Ddcn_3_1_5_sh_mask.h20582 #define MPCC0_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT … macro
Ddcn_3_1_2_sh_mask.h22565 #define MPCC0_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT … macro
Ddcn_3_0_2_sh_mask.h47105 #define MPCC0_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT … macro
Ddcn_3_1_4_sh_mask.h55788 #define MPCC0_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT … macro
Ddcn_3_1_6_sh_mask.h23323 #define MPCC0_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT … macro
Ddcn_3_0_0_sh_mask.h54256 #define MPCC0_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT … macro
Ddcn_2_0_0_sh_mask.h23286 #define MPCC0_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT … macro
Ddcn_3_2_0_sh_mask.h15066 #define MPCC0_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT … macro