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Searched refs:MPCC0_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT (Results 1 – 14 of 14) sorted by relevance

/Linux-v6.6/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_2_0_3_sh_mask.h10794 #define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
Ddcn_3_0_3_sh_mask.h24112 #define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
Ddcn_3_0_1_sh_mask.h40063 #define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
Ddcn_2_1_0_sh_mask.h20178 #define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
Ddcn_3_2_1_sh_mask.h15029 #define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
Ddcn_1_0_sh_mask.h18804 #define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
Ddcn_3_1_5_sh_mask.h20542 #define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
Ddcn_3_1_2_sh_mask.h22525 #define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
Ddcn_3_0_2_sh_mask.h47065 #define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
Ddcn_3_1_4_sh_mask.h55748 #define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
Ddcn_3_1_6_sh_mask.h23283 #define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
Ddcn_3_0_0_sh_mask.h54216 #define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
Ddcn_2_0_0_sh_mask.h23246 #define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
Ddcn_3_2_0_sh_mask.h15026 #define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro