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/Linux-v6.6/Documentation/translations/zh_CN/PCI/
Dpci.rst54 - 请求MMIO/IOP资源
69 - 释放MMIO/IOP资源
182 - 请求MMIO/IOP资源
227 请求MMIO/IOP资源
229 内存(MMIO)和I/O端口地址不应该直接从PCI设备配置空间中读取。使用 ``pci_dev`` 结构体
241 后确定MMIO和IO端口资源的可用性。
243 ``pci_request_region()`` 的通用风格是 ``request_mem_region()`` (用于MMIO
321 3) 免控制数据过期都很重要。这个保证允许驱动程序省略MMIO读取,以刷新DMA流。
337 - 禁用设备对MMIO/IO端口地址的响应
338 - 释放MMIO/IO端口资源
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/Linux-v6.6/Documentation/translations/zh_CN/userspace-api/accelerators/
Docxl.rst72 存上下文、内存映射IO(MMIO)区域的大小等。
76 MMIO chapter
79 OpenCAPI为每个AFU定义了两个MMIO区域:
81 * 全局MMIO区域,保存和整个AFU相关的寄存器。
82 * 每个进程的MMIO区域,对于每个上下文固定大小。
168 一个进程可以mmap每个进程的MMIO区域来和AFU交互。
/Linux-v6.6/Documentation/devicetree/bindings/misc/
Dpvpanic-mmio.txt1 * QEMU PVPANIC MMIO Configuration bindings
4 MMIO Configuration interface on the "virt" machine.
14 - reg: the MMIO region used by the device.
/Linux-v6.6/Documentation/admin-guide/hw-vuln/
Dprocessor_mmio_stale_data.rst2 Processor MMIO Stale Data Vulnerabilities
5 Processor MMIO Stale Data Vulnerabilities are a class of memory-mapped I/O
6 (MMIO) vulnerabilities that can expose data. The sequences of operations for
8 vulnerabilities require the attacker to have access to MMIO, many environments
9 are not affected. System environments using virtualization where MMIO access is
22 one microarchitectural buffer or register to another. Processor MMIO Stale Data
49 processors, MMIO primary reads will return 64 bytes of data to the core fill
57 Some endpoint MMIO registers incorrectly handle writes that are smaller than
117 specific variants of Processor MMIO Stale Data vulnerabilities and mitigation
145 is more critical, or the untrusted software has no MMIO access). Note that
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/Linux-v6.6/Documentation/devicetree/bindings/security/tpm/
Dtpm_tis_mmio.txt1 Trusted Computing Group MMIO Trusted Platform Module
4 is the standard protocol defined to access the TPM via MMIO. Typically
15 - reg: The location of the MMIO registers, should be at least 0x5000 bytes
/Linux-v6.6/Documentation/userspace-api/accelerators/
Docxl.rst66 work with, the size of its MMIO areas, ...
70 MMIO chapter
73 OpenCAPI defines two MMIO areas for each AFU:
75 * the global MMIO area, with registers pertinent to the whole AFU.
76 * a per-process MMIO area, which has a fixed size for each context.
158 MMIO areas, the AFU version, and the PASID for the current context.
175 A process can mmap the per-process MMIO area for interactions with the
/Linux-v6.6/arch/x86/kernel/cpu/
Dcommon.c1261 #define MMIO BIT(1) macro
1278 VULNBL_INTEL_STEPPINGS(HASWELL_X, X86_STEPPING_ANY, MMIO),
1279 VULNBL_INTEL_STEPPINGS(BROADWELL_D, X86_STEPPING_ANY, MMIO),
1281 VULNBL_INTEL_STEPPINGS(BROADWELL_X, X86_STEPPING_ANY, MMIO),
1283 VULNBL_INTEL_STEPPINGS(SKYLAKE_X, X86_STEPPING_ANY, MMIO | RETBLEED | GDS),
1284 VULNBL_INTEL_STEPPINGS(SKYLAKE_L, X86_STEPPING_ANY, MMIO | RETBLEED | GDS | SRBDS),
1285 VULNBL_INTEL_STEPPINGS(SKYLAKE, X86_STEPPING_ANY, MMIO | RETBLEED | GDS | SRBDS),
1286 VULNBL_INTEL_STEPPINGS(KABYLAKE_L, X86_STEPPING_ANY, MMIO | RETBLEED | GDS | SRBDS),
1287 VULNBL_INTEL_STEPPINGS(KABYLAKE, X86_STEPPING_ANY, MMIO | RETBLEED | GDS | SRBDS),
1289 VULNBL_INTEL_STEPPINGS(ICELAKE_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED | GDS),
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/Linux-v6.6/drivers/gpio/
DTODO55 driver infrastructure for doing simpler MMIO GPIO devices and there was
83 - Get rid of struct of_mm_gpio_chip altogether: use the generic MMIO
112 Generic MMIO GPIO
114 The GPIO drivers can utilize the generic MMIO helper library in many
115 cases, and the helper library should be as helpful as possible for MMIO
121 dry-code conversions to MMIO GPIO for maintainers to test
123 - Expand the MMIO GPIO or write a new library for regmap-based I/O
127 - Expand the MMIO GPIO or write a new library for port-mapped I/O
134 In the very similar way to Generic MMIO GPIO convert the users which can
136 MMIO case the regmap MMIO with gpio-regmap.c is preferable over gpio-mmio.c.
/Linux-v6.6/drivers/misc/pvpanic/
DKconfig16 tristate "pvpanic MMIO device support"
19 This driver provides support for the MMIO pvpanic device.
/Linux-v6.6/Documentation/arch/ia64/
Daliasing.rst49 address space because some machines omit some or all of the MMIO
54 This contains only system memory; it does not contain MMIO space.
108 Since the EFI memory map does not describe MMIO on some
115 only allows mmap of the one megabyte "legacy MMIO" area for a
129 This is an MMIO mmap of PCI functions, which additionally may or
147 but could be accessed this way. For example, registers in MMIO
175 mmap of various MMIO regions from /dev/mem by "X" on Intel platforms
178 The EFI memory map may not report these MMIO regions.
226 0x00000-0xFFFFF WB only (no VGA MMIO hole)
/Linux-v6.6/Documentation/powerpc/
Dcxl.rst99 MMIO space
102 A portion of the accelerator MMIO space can be directly mapped
141 context. Master contexts have access to the full MMIO space an
143 MMIO space an AFU provides.
147 /dev/cxl/afu0.0d. This will have access to the entire MMIO space
251 An AFU may have an MMIO space to facilitate communication with the
252 AFU. If it does, the MMIO space can be accessed via mmap. The size
257 the MMIO space and slave contexts are allowed to only map the per
258 process MMIO space associated with the context. In dedicated
259 process mode the entire MMIO space can always be mapped.
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Dpci_iov_resource_on_powernv.rst13 This document describes the requirement from hardware for PCI MMIO resource
29 state bits (one for MMIO and one for DMA, they get set together but can be
37 The interesting part is how the various PCIe transactions (MMIO, DMA, ...)
96 maps each segment to a PE#. That allows portions of the MMIO space
101 SR-IOV). We basically use the trick of forcing the bridge MMIO windows
222 The IODA2 platform has 16 M64 windows, which are used to map MMIO
223 range to PE#. Each M64 window defines one MMIO range and this range is
232 device's MMIO range.
236 segments [total_VFs, 255] of the M64 window may map to some MMIO range on
287 In IODA2, the MMIO address determines the PE#. If the address is in an M32
/Linux-v6.6/Documentation/devicetree/bindings/regmap/
Dregmap.txt10 Regmap defaults to little-endian register access on MMIO based
18 of the CPU and a byteswap for MMIO registers (e.g. many Broadcom MIPS
/Linux-v6.6/Documentation/PCI/
Dpci.rst46 - Request MMIO/IOP resources
62 - Release MMIO/IOP resources
183 - Request MMIO/IOP resources
236 Request MMIO/IOP resources
238 Memory (MMIO), and I/O port addresses should NOT be read directly
254 determine MMIO and IO Port resource availability _after_ calling
258 (for MMIO ranges) and request_region() (for IO Port ranges).
354 This guarantee allows the driver to omit MMIO reads to flush
372 - Disable device from responding to MMIO/IO Port addresses
373 - Release MMIO/IO Port resource(s)
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/Linux-v6.6/Documentation/mhi/
Dmhi.rst25 MMIO section in MHI Internals
28 MMIO (Memory mapped IO) consists of a set of registers in the device hardware,
30 Following are the major components of MMIO register space:
160 to access device MMIO register space.
165 programming MMIO registers.
192 the device's MMIO register space. To initialize the MHI in a device,
198 * Programs MHI MMIO registers and sets device into MHI_M0 state.
/Linux-v6.6/Documentation/translations/ko_KR/
Dmemory-barriers.txt121 - 캐시 일관성 vs MMIO.
1833 합니다. 하지만, 느슨한 순서 규칙의 메모리 I/O 윈도우를 통한 MMIO 의 효과를
1910 사용하면 캐시 일관성이 있는 메모리 (cache coherent memory) 쓰기가 MMIO
2515 readX() 와 writeX() MMIO 액세스 함수는 접근되는 주변장치로의 포인터를
2520 순서지어집니다. 이는 같은 CPU 쓰레드에 의한 특정 디바이스로의 MMIO
2526 호출된 MMIO 레지스터 쓰기는 해당 락의 획득에 일관적인 순서로 도달할
2533 전송을 시작시키기 위해 MMIO 컨트롤 레지스터에 쓰기를 할 때 DMA
2539 읽기는 이 DMA 수신의 완료를 표시하는 DMA 엔진의 MMIO 상태 레지스터
2544 주변장치로의 두개의 MMIO 레지스터 쓰기가 행해지는데 첫번째 쓰기가
2568 readsX() 와 writesX() MMIO 액세스 함수는 DMA 를 수행하는데 적절치 않은,
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/Linux-v6.6/Documentation/trace/
Dmmiotrace.rst10 MMIO tracing was originally developed by Intel around 2003 for their Fault
12 Jeff Muizelaar created a tool for tracing MMIO accesses with the Nouveau
67 Load the driver you want to trace and use it. Mmiotrace will only catch MMIO
126 MMIO accesses are recorded via page faults. Just before __ioremap() returns,
166 zero if it is not recorded. PID is always zero as tracing MMIO accesses
182 - replaying MMIO logs, i.e., re-executing the recorded writes
/Linux-v6.6/Documentation/networking/device_drivers/ethernet/freescale/dpaa2/
Doverview.rst121 A DPRC has a mappable MMIO region (an MC portal) that can be used
172 supports and a summary of key resources of the object (MMIO regions
180 - MMIO regions: none
191 - MMIO regions: none
201 from the queues themselves. The DPIO provides an MMIO interface to
203 to the DPIO MMIO region, which includes the target queue number.
208 - MMIO regions: queue operations, buffer management
217 - MMIO regions: none
227 - MMIO regions: MC command portal
/Linux-v6.6/drivers/soc/aspeed/
DKconfig38 tristate "ASPEED P2A (VGA MMIO to BMC) bridge control"
43 Control ASPEED P2A VGA MMIO to BMC mappings through ioctl()s. The
/Linux-v6.6/drivers/mux/
DKconfig49 tristate "MMIO/Regmap register bitfield-controlled Multiplexer"
52 MMIO/Regmap register bitfield-controlled Multiplexer controller.
/Linux-v6.6/drivers/net/ethernet/dlink/
DKconfig46 bool "Use MMIO instead of PIO"
50 Do NOT enable this by default, PIO (enabled when MMIO is disabled)
/Linux-v6.6/Documentation/virt/kvm/x86/
Dmmu.rst313 accessing MMIO and cached MMIO information is available.
317 MMIO sptes" below)
440 Fast invalidation of MMIO sptes
443 As mentioned in "Reaction to events" above, kvm will cache MMIO
449 MMIO sptes have a few spare bits, which are used to store a
454 When KVM finds an MMIO spte, it checks the generation number of the spte.
456 number, it will ignore the cached MMIO information and handle the page
464 stored into the MMIO spte. Thus, the MMIO spte might be created based on
470 want to use an MMIO sptes created with an odd generation number, and we can do
471 this without losing a bit in the MMIO spte. The "update in-progress" bit of the
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/Linux-v6.6/drivers/net/ethernet/via/
DKconfig36 bool "Use MMIO instead of PIO"
39 This instructs the driver to use PCI shared memory (MMIO) instead of
/Linux-v6.6/Documentation/arch/x86/
Dtdx.rst125 MMIO for virtual devices is implemented as shared memory. The guest must
126 be careful not to access device MMIO regions unless it is also prepared to
169 MMIO handling
172 In non-TDX VMs, MMIO is usually implemented by giving a guest access to a
178 In TDX, MMIO regions typically trigger a #VE exception in the guest. The
179 guest #VE handler then emulates the MMIO instruction inside the guest and
183 MMIO addresses on x86 are just special physical addresses. They can
188 MMIO access via other means (like structure overlays) may result in an
/Linux-v6.6/Documentation/devicetree/bindings/interrupt-controller/
Dmsi.txt5 write to an MMIO address.
14 - The doorbell (the MMIO address written to).
34 An MSI controller signals interrupts to a CPU when a write is made to an MMIO

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