| /Linux-v6.6/drivers/gpu/drm/renesas/rcar-du/ |
| D | rcar_mipi_dsi.c | 31 #define MHZ(v) ((u32)((v) * 1000000U)) macro
102 { MHZ(80), 0x00 }, { MHZ(90), 0x10 }, { MHZ(100), 0x20 },
103 { MHZ(110), 0x30 }, { MHZ(120), 0x01 }, { MHZ(130), 0x11 },
104 { MHZ(140), 0x21 }, { MHZ(150), 0x31 }, { MHZ(160), 0x02 },
105 { MHZ(170), 0x12 }, { MHZ(180), 0x22 }, { MHZ(190), 0x32 },
106 { MHZ(205), 0x03 }, { MHZ(220), 0x13 }, { MHZ(235), 0x23 },
107 { MHZ(250), 0x33 }, { MHZ(275), 0x04 }, { MHZ(300), 0x14 },
108 { MHZ(325), 0x25 }, { MHZ(350), 0x35 }, { MHZ(400), 0x05 },
109 { MHZ(450), 0x16 }, { MHZ(500), 0x26 }, { MHZ(550), 0x37 },
110 { MHZ(600), 0x07 }, { MHZ(650), 0x18 }, { MHZ(700), 0x28 },
[all …]
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| /Linux-v6.6/drivers/clk/samsung/ |
| D | clk-exynos3250.c | 675 PLL_35XX_RATE(24 * MHZ, 1200000000, 400, 4, 1),
676 PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1),
677 PLL_35XX_RATE(24 * MHZ, 1066000000, 533, 6, 1),
678 PLL_35XX_RATE(24 * MHZ, 1000000000, 250, 3, 1),
679 PLL_35XX_RATE(24 * MHZ, 960000000, 320, 4, 1),
680 PLL_35XX_RATE(24 * MHZ, 900000000, 300, 4, 1),
681 PLL_35XX_RATE(24 * MHZ, 850000000, 425, 6, 1),
682 PLL_35XX_RATE(24 * MHZ, 800000000, 200, 3, 1),
683 PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1),
684 PLL_35XX_RATE(24 * MHZ, 667000000, 667, 12, 1),
[all …]
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| D | clk-exynos4.c | 1075 PLL_4508_RATE(24 * MHZ, 1200000000, 150, 3, 1, 28),
1076 PLL_4508_RATE(24 * MHZ, 1000000000, 250, 6, 1, 28),
1077 PLL_4508_RATE(24 * MHZ, 800000000, 200, 6, 1, 28),
1078 PLL_4508_RATE(24 * MHZ, 666857142, 389, 14, 1, 13),
1079 PLL_4508_RATE(24 * MHZ, 600000000, 100, 4, 1, 13),
1080 PLL_4508_RATE(24 * MHZ, 533000000, 533, 24, 1, 5),
1081 PLL_4508_RATE(24 * MHZ, 500000000, 250, 6, 2, 28),
1082 PLL_4508_RATE(24 * MHZ, 400000000, 200, 6, 2, 28),
1083 PLL_4508_RATE(24 * MHZ, 200000000, 200, 6, 3, 28),
1088 PLL_4600_RATE(24 * MHZ, 192000000, 48, 3, 1, 0, 0),
[all …]
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| D | clk-exynos5420.c | 1403 PLL_35XX_RATE(24 * MHZ, 2000000000, 250, 3, 0),
1404 PLL_35XX_RATE(24 * MHZ, 1900000000, 475, 6, 0),
1405 PLL_35XX_RATE(24 * MHZ, 1800000000, 225, 3, 0),
1406 PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0),
1407 PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),
1408 PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),
1409 PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),
1410 PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),
1411 PLL_35XX_RATE(24 * MHZ, 1200000000, 200, 2, 1),
1412 PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1),
[all …]
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| D | clk-exynos5250.c | 694 PLL_36XX_RATE(24 * MHZ, 266000000, 266, 3, 3, 0),
696 PLL_36XX_RATE(24 * MHZ, 70500000, 94, 2, 4, 0),
703 PLL_36XX_RATE(24 * MHZ, 192000000, 64, 2, 2, 0),
704 PLL_36XX_RATE(24 * MHZ, 180633605, 90, 3, 2, 20762),
705 PLL_36XX_RATE(24 * MHZ, 180000000, 90, 3, 2, 0),
706 PLL_36XX_RATE(24 * MHZ, 73728000, 98, 2, 4, 19923),
707 PLL_36XX_RATE(24 * MHZ, 67737602, 90, 2, 4, 20762),
708 PLL_36XX_RATE(24 * MHZ, 49152000, 98, 3, 4, 19923),
709 PLL_36XX_RATE(24 * MHZ, 45158401, 90, 3, 4, 20762),
710 PLL_36XX_RATE(24 * MHZ, 32768001, 131, 3, 5, 4719),
[all …]
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| D | clk-exynos5260.c | 38 PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0),
39 PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),
40 PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),
41 PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),
42 PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),
43 PLL_35XX_RATE(24 * MHZ, 1200000000, 400, 4, 1),
44 PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1),
45 PLL_35XX_RATE(24 * MHZ, 1000000000, 250, 3, 1),
46 PLL_35XX_RATE(24 * MHZ, 933000000, 311, 4, 1),
47 PLL_35XX_RATE(24 * MHZ, 900000000, 300, 4, 1),
[all …]
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| D | clk-exynos5410.c | 230 PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0),
231 PLL_36XX_RATE(24 * MHZ, 333000000U, 111, 2, 2, 0),
232 PLL_36XX_RATE(24 * MHZ, 300000000U, 100, 2, 2, 0),
233 PLL_36XX_RATE(24 * MHZ, 266000000U, 266, 3, 3, 0),
234 PLL_36XX_RATE(24 * MHZ, 200000000U, 200, 3, 3, 0),
235 PLL_36XX_RATE(24 * MHZ, 192000000U, 192, 3, 3, 0),
236 PLL_36XX_RATE(24 * MHZ, 166000000U, 166, 3, 3, 0),
237 PLL_36XX_RATE(24 * MHZ, 133000000U, 266, 3, 4, 0),
238 PLL_36XX_RATE(24 * MHZ, 100000000U, 200, 3, 4, 0),
239 PLL_36XX_RATE(24 * MHZ, 66000000U, 176, 2, 5, 0),
[all …]
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| D | clk-exynos5433.c | 738 PLL_35XX_RATE(24 * MHZ, 2500000000U, 625, 6, 0),
739 PLL_35XX_RATE(24 * MHZ, 2400000000U, 500, 5, 0),
740 PLL_35XX_RATE(24 * MHZ, 2300000000U, 575, 6, 0),
741 PLL_35XX_RATE(24 * MHZ, 2200000000U, 550, 6, 0),
742 PLL_35XX_RATE(24 * MHZ, 2100000000U, 350, 4, 0),
743 PLL_35XX_RATE(24 * MHZ, 2000000000U, 500, 6, 0),
744 PLL_35XX_RATE(24 * MHZ, 1900000000U, 475, 6, 0),
745 PLL_35XX_RATE(24 * MHZ, 1800000000U, 375, 5, 0),
746 PLL_35XX_RATE(24 * MHZ, 1700000000U, 425, 6, 0),
747 PLL_35XX_RATE(24 * MHZ, 1600000000U, 400, 6, 0),
[all …]
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| /Linux-v6.6/drivers/clk/mediatek/ |
| D | clk-mt8365-apmixedsys.c | 15 #define MT8365_PLL_FMAX (3800UL * MHZ)
16 #define MT8365_PLL_FMIN (1500UL * MHZ)
57 { .div = 1, .freq = 1500 * MHZ },
58 { .div = 2, .freq = 750 * MHZ },
59 { .div = 3, .freq = 375 * MHZ },
66 { .div = 1, .freq = 1600 * MHZ },
67 { .div = 2, .freq = 800 * MHZ },
68 { .div = 3, .freq = 400 * MHZ },
69 { .div = 4, .freq = 200 * MHZ },
75 { .div = 1, .freq = 1600 * MHZ },
[all …]
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| D | clk-mt8183-apmixedsys.c | 51 #define MT8183_PLL_FMAX (3800UL * MHZ)
52 #define MT8183_PLL_FMIN (1500UL * MHZ)
94 { .div = 1, .freq = 1500 * MHZ },
95 { .div = 2, .freq = 750 * MHZ },
96 { .div = 3, .freq = 375 * MHZ },
103 { .div = 1, .freq = 1600 * MHZ },
104 { .div = 2, .freq = 800 * MHZ },
105 { .div = 3, .freq = 400 * MHZ },
106 { .div = 4, .freq = 200 * MHZ },
|
| D | clk-mt2701.c | 29 108 * MHZ),
31 400 * MHZ),
35 340 * MHZ),
37 340 * MHZ),
39 340 * MHZ),
41 27 * MHZ),
43 416 * MHZ),
45 143 * MHZ),
47 27 * MHZ),
910 #define MT8590_PLL_FMAX (2000 * MHZ)
|
| /Linux-v6.6/Documentation/userspace-api/media/dvb/ |
| D | fe-bandwidth-t.rst | 30 - .. _BANDWIDTH-1-712-MHZ:
38 - .. _BANDWIDTH-5-MHZ:
46 - .. _BANDWIDTH-6-MHZ:
54 - .. _BANDWIDTH-7-MHZ:
62 - .. _BANDWIDTH-8-MHZ:
70 - .. _BANDWIDTH-10-MHZ:
|
| /Linux-v6.6/drivers/clk/ |
| D | clk-nspire.c | 13 #define MHZ (1000 * 1000) macro
44 clk->base_clock = 48 * MHZ; in nspire_clkinfo_cx()
46 clk->base_clock = 6 * EXTRACT(val, CX_BASE) * MHZ; in nspire_clkinfo_cx()
55 clk->base_clock = 27 * MHZ; in nspire_clkinfo_classic()
57 clk->base_clock = (300 - 6 * EXTRACT(val, CLASSIC_BASE)) * MHZ; in nspire_clkinfo_classic()
132 info.base_clock / MHZ, in nspire_clk_setup()
133 info.base_clock / info.base_cpu_ratio / MHZ, in nspire_clk_setup()
134 info.base_clock / info.base_ahb_ratio / MHZ); in nspire_clk_setup()
|
| /Linux-v6.6/drivers/net/can/softing/ |
| D | softing_cs.c | 26 #define MHZ (1000*1000) macro
33 .freq = 16 * MHZ, .max_brp = 32, .max_sjw = 4,
45 .freq = 16 * MHZ, .max_brp = 32, .max_sjw = 4,
57 .freq = 20 * MHZ, .max_brp = 32, .max_sjw = 4,
69 .freq = 24 * MHZ, .max_brp = 64, .max_sjw = 4,
81 .freq = 16 * MHZ, .max_brp = 64, .max_sjw = 4,
93 .freq = 20 * MHZ, .max_brp = 32, .max_sjw = 4,
105 .freq = 24 * MHZ, .max_brp = 64, .max_sjw = 4,
117 .freq = 16 * MHZ, .max_brp = 64, .max_sjw = 4,
129 .freq = 24 * MHZ, .max_brp = 64, .max_sjw = 4,
|
| /Linux-v6.6/arch/arm/mach-s3c/ |
| D | cpu.h | 45 #ifndef MHZ
46 #define MHZ (1000*1000) macro
49 #define print_mhz(m) ((m) / MHZ), (((m) / 1000) % 1000)
|
| D | setup-usb-phy-s3c64xx.c | 36 case 12 * MHZ: in s3c_usb_otgphy_init()
39 case 24 * MHZ: in s3c_usb_otgphy_init()
43 case 48 * MHZ: in s3c_usb_otgphy_init()
|
| /Linux-v6.6/drivers/phy/samsung/ |
| D | phy-exynos4x12-usb2.c | 140 case 10 * MHZ: in exynos4x12_rate_to_clk()
143 case 12 * MHZ: in exynos4x12_rate_to_clk()
149 case 20 * MHZ: in exynos4x12_rate_to_clk()
152 case 24 * MHZ: in exynos4x12_rate_to_clk()
155 case 50 * MHZ: in exynos4x12_rate_to_clk()
|
| D | phy-s5pv210-usb2.c | 73 case 12 * MHZ: in s5pv210_rate_to_clk()
76 case 24 * MHZ: in s5pv210_rate_to_clk()
79 case 48 * MHZ: in s5pv210_rate_to_clk()
|
| D | phy-exynos5250-usb2.c | 149 case 10 * MHZ: in exynos5250_rate_to_clk()
152 case 12 * MHZ: in exynos5250_rate_to_clk()
158 case 20 * MHZ: in exynos5250_rate_to_clk()
161 case 24 * MHZ: in exynos5250_rate_to_clk()
164 case 50 * MHZ: in exynos5250_rate_to_clk()
|
| /Linux-v6.6/drivers/soc/samsung/ |
| D | exynos-asv.c | 23 #define MHZ 1000000U macro
49 opp = dev_pm_opp_find_freq_exact(cpu, opp_freq * MHZ, true); in exynos_asv_update_cpu_opps()
64 ret = dev_pm_opp_adjust_voltage(cpu, opp_freq * MHZ, in exynos_asv_update_cpu_opps()
|
| /Linux-v6.6/drivers/clk/hisilicon/ |
| D | clk-hi3660-stub.c | 25 #define MHZ (1000 * 1000) macro
66 stub_clk->rate = readl(freq_reg + (stub_clk->id << 2)) * MHZ; in hi3660_stub_clk_recalc_rate()
86 stub_clk->msg[1] = rate / MHZ; in hi3660_stub_clk_set_rate()
|
| /Linux-v6.6/arch/powerpc/boot/ |
| D | redboot-83xx.c | 20 #define MHZ(x) ((x + 500000) / 1000000) macro
33 bd.bi_busfreq, MHZ(bd.bi_busfreq)); in platform_fixups()
|
| D | redboot-8xx.c | 19 #define MHZ(x) ((x + 500000) / 1000000) macro
32 bd.bi_busfreq, MHZ(bd.bi_busfreq)); in platform_fixups()
|
| D | devtree.c | 61 #define MHZ(x) ((x + 500000) / 1000000) macro
67 printf("CPU clock-frequency <- 0x%x (%dMHz)\n\r", cpu, MHZ(cpu)); in dt_fixup_cpu_clocks()
68 printf("CPU timebase-frequency <- 0x%x (%dMHz)\n\r", tb, MHZ(tb)); in dt_fixup_cpu_clocks()
70 printf("CPU bus-frequency <- 0x%x (%dMHz)\n\r", bus, MHZ(bus)); in dt_fixup_cpu_clocks()
87 printf("%s: clock-frequency <- %x (%dMHz)\n\r", path, freq, MHZ(freq)); in dt_fixup_clock()
|
| /Linux-v6.6/drivers/gpu/drm/bridge/ |
| D | samsung-dsim.c | 545 #ifndef MHZ
546 #define MHZ (1000 * 1000) macro
562 p_min = DIV_ROUND_UP(fin, (12 * MHZ)); in samsung_dsim_pll_find_pms()
563 p_max = fin / (6 * MHZ); in samsung_dsim_pll_find_pms()
578 if (tmp < driver_data->min_freq * MHZ || in samsung_dsim_pll_find_pms()
579 tmp > driver_data->max_freq * MHZ) in samsung_dsim_pll_find_pms()
632 100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ, in samsung_dsim_set_pll()
633 270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ, in samsung_dsim_set_pll()
634 510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ, in samsung_dsim_set_pll()
635 770 * MHZ, 870 * MHZ, 950 * MHZ, in samsung_dsim_set_pll()
[all …]
|
