Searched refs:MASK_05 (Results 1 – 4 of 4) sorted by relevance
341 saa7146_write(dev, MC2, (MASK_05 | MASK_06 | MASK_21 | MASK_22) ); in saa7146_set_window()353 saa7146_write(dev, MC2, (MASK_05 | MASK_21)); in saa7146_set_output_format()370 saa7146_write(dev, MC2, (MASK_05 | MASK_21)); in saa7146_set_hps_source_and_sync()661 WRITE_RPS0(MASK_05 | MASK_21); /* => mask */ in program_capture_engine()662 WRITE_RPS0(MASK_05 | MASK_21); /* => values */ in program_capture_engine()689 WRITE_RPS0(MASK_05 | MASK_21); /* => mask */ in program_capture_engine()715 saa7146_write(dev, MC2, (MASK_05 | MASK_21)); in saa7146_disable_clipping()
413 1 * (MASK_05 | MASK_21) | // HPS_CTRL2 in budget_patch_attach()431 MASK_10 | MASK_09 | MASK_08 | MASK_06 | MASK_05 | MASK_04 | MASK_03 | MASK_02 ); in budget_patch_attach()
2394 0 * (MASK_05 | MASK_21) | // HPS_CTRL2 in av7110_attach()
242 #define MASK_05 0x00000020 /* Mask value for bit 5 */ macro
