1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Reset driver for NXP LPC18xx/43xx Reset Generation Unit (RGU).
4 *
5 * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
6 */
7
8 #include <linux/clk.h>
9 #include <linux/delay.h>
10 #include <linux/err.h>
11 #include <linux/io.h>
12 #include <linux/init.h>
13 #include <linux/of.h>
14 #include <linux/platform_device.h>
15 #include <linux/reboot.h>
16 #include <linux/reset-controller.h>
17 #include <linux/spinlock.h>
18
19 /* LPC18xx RGU registers */
20 #define LPC18XX_RGU_CTRL0 0x100
21 #define LPC18XX_RGU_CTRL1 0x104
22 #define LPC18XX_RGU_ACTIVE_STATUS0 0x150
23 #define LPC18XX_RGU_ACTIVE_STATUS1 0x154
24
25 #define LPC18XX_RGU_RESETS_PER_REG 32
26
27 /* Internal reset outputs */
28 #define LPC18XX_RGU_CORE_RST 0
29 #define LPC43XX_RGU_M0SUB_RST 12
30 #define LPC43XX_RGU_M0APP_RST 56
31
32 struct lpc18xx_rgu_data {
33 struct reset_controller_dev rcdev;
34 struct notifier_block restart_nb;
35 struct clk *clk_delay;
36 struct clk *clk_reg;
37 void __iomem *base;
38 spinlock_t lock;
39 u32 delay_us;
40 };
41
42 #define to_rgu_data(p) container_of(p, struct lpc18xx_rgu_data, rcdev)
43
lpc18xx_rgu_restart(struct notifier_block * nb,unsigned long mode,void * cmd)44 static int lpc18xx_rgu_restart(struct notifier_block *nb, unsigned long mode,
45 void *cmd)
46 {
47 struct lpc18xx_rgu_data *rc = container_of(nb, struct lpc18xx_rgu_data,
48 restart_nb);
49
50 writel(BIT(LPC18XX_RGU_CORE_RST), rc->base + LPC18XX_RGU_CTRL0);
51 mdelay(2000);
52
53 pr_emerg("%s: unable to restart system\n", __func__);
54
55 return NOTIFY_DONE;
56 }
57
58 /*
59 * The LPC18xx RGU has mostly self-deasserting resets except for the
60 * two reset lines going to the internal Cortex-M0 cores.
61 *
62 * To prevent the M0 core resets from accidentally getting deasserted
63 * status register must be check and bits in control register set to
64 * preserve the state.
65 */
lpc18xx_rgu_setclear_reset(struct reset_controller_dev * rcdev,unsigned long id,bool set)66 static int lpc18xx_rgu_setclear_reset(struct reset_controller_dev *rcdev,
67 unsigned long id, bool set)
68 {
69 struct lpc18xx_rgu_data *rc = to_rgu_data(rcdev);
70 u32 stat_offset = LPC18XX_RGU_ACTIVE_STATUS0;
71 u32 ctrl_offset = LPC18XX_RGU_CTRL0;
72 unsigned long flags;
73 u32 stat, rst_bit;
74
75 stat_offset += (id / LPC18XX_RGU_RESETS_PER_REG) * sizeof(u32);
76 ctrl_offset += (id / LPC18XX_RGU_RESETS_PER_REG) * sizeof(u32);
77 rst_bit = 1 << (id % LPC18XX_RGU_RESETS_PER_REG);
78
79 spin_lock_irqsave(&rc->lock, flags);
80 stat = ~readl(rc->base + stat_offset);
81 if (set)
82 writel(stat | rst_bit, rc->base + ctrl_offset);
83 else
84 writel(stat & ~rst_bit, rc->base + ctrl_offset);
85 spin_unlock_irqrestore(&rc->lock, flags);
86
87 return 0;
88 }
89
lpc18xx_rgu_assert(struct reset_controller_dev * rcdev,unsigned long id)90 static int lpc18xx_rgu_assert(struct reset_controller_dev *rcdev,
91 unsigned long id)
92 {
93 return lpc18xx_rgu_setclear_reset(rcdev, id, true);
94 }
95
lpc18xx_rgu_deassert(struct reset_controller_dev * rcdev,unsigned long id)96 static int lpc18xx_rgu_deassert(struct reset_controller_dev *rcdev,
97 unsigned long id)
98 {
99 return lpc18xx_rgu_setclear_reset(rcdev, id, false);
100 }
101
102 /* Only M0 cores require explicit reset deassert */
lpc18xx_rgu_reset(struct reset_controller_dev * rcdev,unsigned long id)103 static int lpc18xx_rgu_reset(struct reset_controller_dev *rcdev,
104 unsigned long id)
105 {
106 struct lpc18xx_rgu_data *rc = to_rgu_data(rcdev);
107
108 lpc18xx_rgu_assert(rcdev, id);
109 udelay(rc->delay_us);
110
111 switch (id) {
112 case LPC43XX_RGU_M0SUB_RST:
113 case LPC43XX_RGU_M0APP_RST:
114 lpc18xx_rgu_setclear_reset(rcdev, id, false);
115 }
116
117 return 0;
118 }
119
lpc18xx_rgu_status(struct reset_controller_dev * rcdev,unsigned long id)120 static int lpc18xx_rgu_status(struct reset_controller_dev *rcdev,
121 unsigned long id)
122 {
123 struct lpc18xx_rgu_data *rc = to_rgu_data(rcdev);
124 u32 bit, offset = LPC18XX_RGU_ACTIVE_STATUS0;
125
126 offset += (id / LPC18XX_RGU_RESETS_PER_REG) * sizeof(u32);
127 bit = 1 << (id % LPC18XX_RGU_RESETS_PER_REG);
128
129 return !(readl(rc->base + offset) & bit);
130 }
131
132 static const struct reset_control_ops lpc18xx_rgu_ops = {
133 .reset = lpc18xx_rgu_reset,
134 .assert = lpc18xx_rgu_assert,
135 .deassert = lpc18xx_rgu_deassert,
136 .status = lpc18xx_rgu_status,
137 };
138
lpc18xx_rgu_probe(struct platform_device * pdev)139 static int lpc18xx_rgu_probe(struct platform_device *pdev)
140 {
141 struct lpc18xx_rgu_data *rc;
142 u32 fcclk, firc;
143 int ret;
144
145 rc = devm_kzalloc(&pdev->dev, sizeof(*rc), GFP_KERNEL);
146 if (!rc)
147 return -ENOMEM;
148
149 rc->base = devm_platform_ioremap_resource(pdev, 0);
150 if (IS_ERR(rc->base))
151 return PTR_ERR(rc->base);
152
153 rc->clk_reg = devm_clk_get(&pdev->dev, "reg");
154 if (IS_ERR(rc->clk_reg)) {
155 dev_err(&pdev->dev, "reg clock not found\n");
156 return PTR_ERR(rc->clk_reg);
157 }
158
159 rc->clk_delay = devm_clk_get(&pdev->dev, "delay");
160 if (IS_ERR(rc->clk_delay)) {
161 dev_err(&pdev->dev, "delay clock not found\n");
162 return PTR_ERR(rc->clk_delay);
163 }
164
165 ret = clk_prepare_enable(rc->clk_reg);
166 if (ret) {
167 dev_err(&pdev->dev, "unable to enable reg clock\n");
168 return ret;
169 }
170
171 ret = clk_prepare_enable(rc->clk_delay);
172 if (ret) {
173 dev_err(&pdev->dev, "unable to enable delay clock\n");
174 goto dis_clk_reg;
175 }
176
177 fcclk = clk_get_rate(rc->clk_reg) / USEC_PER_SEC;
178 firc = clk_get_rate(rc->clk_delay) / USEC_PER_SEC;
179 if (fcclk == 0 || firc == 0)
180 rc->delay_us = 2;
181 else
182 rc->delay_us = DIV_ROUND_UP(fcclk, firc * firc);
183
184 spin_lock_init(&rc->lock);
185
186 rc->rcdev.owner = THIS_MODULE;
187 rc->rcdev.nr_resets = 64;
188 rc->rcdev.ops = &lpc18xx_rgu_ops;
189 rc->rcdev.of_node = pdev->dev.of_node;
190
191 ret = reset_controller_register(&rc->rcdev);
192 if (ret) {
193 dev_err(&pdev->dev, "unable to register device\n");
194 goto dis_clks;
195 }
196
197 rc->restart_nb.priority = 192,
198 rc->restart_nb.notifier_call = lpc18xx_rgu_restart,
199 ret = register_restart_handler(&rc->restart_nb);
200 if (ret)
201 dev_warn(&pdev->dev, "failed to register restart handler\n");
202
203 return 0;
204
205 dis_clks:
206 clk_disable_unprepare(rc->clk_delay);
207 dis_clk_reg:
208 clk_disable_unprepare(rc->clk_reg);
209
210 return ret;
211 }
212
213 static const struct of_device_id lpc18xx_rgu_match[] = {
214 { .compatible = "nxp,lpc1850-rgu" },
215 { }
216 };
217
218 static struct platform_driver lpc18xx_rgu_driver = {
219 .probe = lpc18xx_rgu_probe,
220 .driver = {
221 .name = "lpc18xx-reset",
222 .of_match_table = lpc18xx_rgu_match,
223 .suppress_bind_attrs = true,
224 },
225 };
226 builtin_platform_driver(lpc18xx_rgu_driver);
227
