Searched refs:JH71X0_CLK_DIV_MASK (Results 1 – 9 of 9) sorted by relevance
71 u32 div = jh71x0_clk_reg_get(clk) & JH71X0_CLK_DIV_MASK; in jh71x0_clk_recalc_rate()113 jh71x0_clk_reg_rmw(clk, JH71X0_CLK_DIV_MASK, div); in jh71x0_clk_set_rate()156 jh71x0_clk_reg_rmw(clk, JH71X0_CLK_DIV_MASK, value); in jh71x0_clk_frac_set_rate()303 if (max & JH71X0_CLK_DIV_MASK) { in starfive_jh71x0_clk_ops()
15 #define JH71X0_CLK_DIV_MASK GENMASK(23, 0) macro
123 clk->max_div = max & JH71X0_CLK_DIV_MASK; in jh7110_aoncrg_probe()
141 clk->max_div = max & JH71X0_CLK_DIV_MASK; in jh7110_stgcrg_probe()
142 clk->max_div = max & JH71X0_CLK_DIV_MASK; in jh7100_audclk_probe()
182 clk->max_div = max & JH71X0_CLK_DIV_MASK; in jh7110_ispcrg_probe()
189 clk->max_div = max & JH71X0_CLK_DIV_MASK; in jh7110_voutcrg_probe()
347 clk->max_div = max & JH71X0_CLK_DIV_MASK; in clk_starfive_jh7100_probe()
493 clk->max_div = max & JH71X0_CLK_DIV_MASK; in jh7110_syscrg_probe()